CN113127287B - Control method and device of processor and electronic equipment - Google Patents
Control method and device of processor and electronic equipment Download PDFInfo
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- CN113127287B CN113127287B CN201911405007.0A CN201911405007A CN113127287B CN 113127287 B CN113127287 B CN 113127287B CN 201911405007 A CN201911405007 A CN 201911405007A CN 113127287 B CN113127287 B CN 113127287B
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- 238000012544 monitoring process Methods 0.000 claims abstract description 51
- 238000004590 computer program Methods 0.000 claims description 10
- 230000006870 function Effects 0.000 description 13
- 238000004891 communication Methods 0.000 description 4
- 230000008878 coupling Effects 0.000 description 3
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3024—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a central processing unit [CPU]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
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Abstract
The invention provides a control method and device of a processor and electronic equipment. A control method of a processor, comprising the steps of: after the processor sends a control instruction, monitoring a response signal aiming at the control instruction; if the answer signal is not monitored within the preset time, ending the monitoring of the answer signal. In this way, in the embodiment of the invention, the answer signal of the control instruction sent by the processor is monitored within the preset time, so that if the module for the control instruction fails and the answer signal responding to the control instruction cannot be returned even if the module for the control instruction fails, the processor can end the monitoring of the answer signal after the preset time, thereby avoiding the load of the processor from being increased by continuously monitoring the answer signal.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a method and an apparatus for controlling a processor, and an electronic device.
Background
As shown in fig. 1, in embedded system applications in various fields, an MCU (Microcontroller Unit, micro control unit) 100 is an essential device. The MCU100 internally includes a processor 101 and a plurality of on-chip modules 103 connected to the processor 101 through an on-chip communication interface 102, and may be connected to the off-chip modules 300 through different communication interfaces 200 to implement different functions.
During operation, the processor typically sends control instructions to the functional modules, such as on-chip modules or off-chip modules, and waits for responses from the functional modules. If the processor is not responded in time due to faults and other reasons of the functional modules, the processor is caused to continuously wait for the response, so that the working resources of the processor are occupied, and the load of the processor is increased.
Disclosure of Invention
The embodiment of the invention provides a control method and device of a processor and electronic equipment, and aims to solve the problem that the load of the processor is possibly increased in the existing control method of the processor.
In order to solve the technical problems, the invention is realized as follows:
in a first aspect, an embodiment of the present invention provides a method for controlling a processor, including the following steps:
after the processor sends a control instruction to the functional module, monitoring a response signal aiming at the control instruction;
if the answer signal is not monitored within the preset time, ending the monitoring of the answer signal.
Optionally, after the processor sends the control instruction, the method further includes:
establishing a first timer with the timing duration being the preset duration;
the monitoring response signals for the control instruction comprises the following steps:
monitoring a response signal aiming at the control instruction in the timing time of the first timer;
and if the answer signal is not monitored within the preset time, ending the monitoring of the answer signal, including:
And if the response signal is not monitored at the end of the timing of the first timer, ending the monitoring of the response signal.
Optionally, after the monitoring of the response signal to the control instruction, the method further includes:
And if the response signal is monitored, closing the first timer.
Optionally, after the ending of the listening for the answer signal, the method further comprises:
closing the first timer.
Optionally, after the ending of the listening for the answer signal, the method further includes:
acquiring the working state of the functional module aimed at by the control instruction;
and if the functional module is in a fault state, sending a fault prompt signal to a user.
Optionally, after detecting the working state of the functional module for which the control instruction is directed, the method further includes:
Determining the importance level of the control instruction;
and if the functional module is in a non-fault state and the importance level of the control instruction is greater than a preset level threshold, the control instruction is sent to the functional module again.
Optionally, the resending the control instruction to the functional module further includes:
and establishing a second timer, and monitoring a response signal for the retransmitted control instruction within the timing duration of the second timer.
Optionally, the timing duration of the second timer is smaller than the timing duration of the first timer.
In a second aspect, an embodiment of the present invention provides a control apparatus for a processor, including:
the monitoring module is used for monitoring response signals aiming at the control instructions after the processor sends the control instructions to the functional module;
And the interruption module is used for ending the monitoring of the response signal if the response signal is not monitored within the preset duration.
Optionally, the method further comprises:
the establishing module is used for establishing a first timer with the timing duration being the preset duration;
the monitoring module is specifically configured to monitor a response signal for the control instruction in a timing time of the first timer;
The interrupt module is specifically configured to terminate monitoring of the response signal if the response signal is not monitored when the first timer is finished.
Optionally, the device further comprises a closing module, configured to close the first timer if the response signal is monitored.
Optionally, the method further comprises:
the acquisition module is used for acquiring the working state of the functional module aimed at by the control instruction;
and the first sending module is used for sending a fault prompt signal to a user if the functional module is in a fault state.
Optionally, the method further comprises:
the determining module is used for determining the importance level of the control instruction;
and the second sending module is used for sending the control instruction to the functional module again if the functional module is in a non-fault state and the importance level of the control instruction is greater than a preset level threshold.
In a third aspect, an embodiment of the present invention provides an electronic device, including a processor, a memory, and a computer program stored on the memory and executable on the processor, the computer program implementing the steps of the method for controlling a processor according to any one of the preceding claims when executed by the processor.
In a fourth aspect, embodiments of the present invention provide a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the method of controlling a processor of any of the above.
In this way, in the embodiment of the invention, the answer signal of the control instruction sent by the processor is monitored within the preset time, so that if the module for the control instruction fails and the answer signal responding to the control instruction cannot be returned even if the module for the control instruction fails, the processor can end the monitoring of the answer signal after the preset time, thereby avoiding the load of the processor from being increased by continuously monitoring the answer signal.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments of the present invention will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.
FIG. 1 is a schematic diagram of a microcontroller and an off-chip module connected to the microcontroller;
FIG. 2 is a flow chart of a control method of a processor according to an embodiment of the present invention;
FIG. 3 is a flow chart of a control method of a processor according to an embodiment of the present invention;
fig. 4 is a block diagram of a control device of a processor according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The embodiment of the invention provides a control method of a processor.
As shown in fig. 2, the method comprises the steps of:
Step 201: and after the processor sends a control instruction to the functional module, monitoring a response signal aiming at the control instruction.
In the technical solution of this embodiment, a control instruction is sent by a processor to a corresponding functional module to control the corresponding functional module to implement a corresponding function.
The functional module may be an actual module system or chip, and the method is applied to a vehicle as an example, the processor may be a processor in an on-board computer of the vehicle or an MCU in a vehicle controller, and the functional module may refer to an on-chip module of the MCU, or may be an off-chip module, for example, a control chip of an air conditioning system of the vehicle, or the like. The functional modules may also refer to virtual modules, such as computer program modules or the like that perform particular functions.
When the processor phase functional module sends a corresponding control instruction, the corresponding functional module returns a response signal for the control instruction according to the requirement so that the processor can acquire the execution condition or other information of the control instruction.
Step 202: if the answer signal is not monitored within the preset time, ending the monitoring of the answer signal.
In this embodiment, the monitoring of the answer signal is performed within a preset time period, and the preset time period may be set according to needs, for example, various time periods such as 1 minute, 5 minutes, 10 minutes, and the like.
If a response signal is monitored within the preset time period, further relevant operations are performed as required, and specific reference may be made to the relevant technology, which is not further defined and described herein.
If the answer signal is not monitored within the preset time period, the monitoring of the answer signal is ended, and the hardware load provided by monitoring the answer signal, such as the corresponding working process of the processor, the corresponding memory load and the like, is recovered.
In a specific embodiment, the listening process for the answer signal specifically turns on a receiving function for a specific signal, and the answer signal is the specific signal, so that the processor can receive and process the answer signal if the preset duration is long.
After the preset time length is reached, the receiving function of the specific signal is closed, and at the moment, whether the response signal is returned or not, the processor cannot receive the response signal, and correspondingly, the load is not required to be consumed to process the response signal.
In this way, in the embodiment of the invention, the answer signal of the control instruction sent by the processor is monitored within the preset time, so that if the module for the control instruction fails and the answer signal responding to the control instruction cannot be returned even if the module for the control instruction fails, the processor can end the monitoring of the answer signal after the preset time, thereby avoiding the load of the processor from being increased by continuously monitoring the answer signal.
Optionally, after the processor sends the control instruction, the method further includes:
establishing a first timer with the timing duration being the preset duration;
the monitoring response signals for the control instruction comprises the following steps:
monitoring a response signal aiming at the control instruction in the timing time of the first timer;
and if the answer signal is not monitored within the preset time, ending the monitoring of the answer signal, including:
And if the response signal is not monitored at the end of the timing of the first timer, ending the monitoring of the response signal.
In this embodiment, the preset duration is determined by establishing a countdown timer, and before the countdown timer ends, the processor may receive the response signal, or it may be understood that the function of receiving the response signal is in an on state.
When the timer is finished, if the response signal is not received yet, the monitoring of the response signal is finished, so that the load of the processor is saved.
Furthermore, after the timer completes the function, the timer is also closed, and the recovery of the hardware performance can be realized. Specifically, if the response signal is monitored, the first timer is closed. And if the response signal is not monitored, closing the first timer when the timing of the timer is finished.
Thus, whether the response signal is received or not, the first timer is closed under a certain condition, and the maximum time of the first timer is not longer than the time duration of the first timer, so that the occupation of the hardware load is reduced.
Optionally, after the ending of the listening for the answer signal, the method further includes:
acquiring the working state of the functional module aimed at by the control instruction;
and if the functional module is in a fault state, sending a fault prompt signal to a user.
In this embodiment, if no response signal is received, it is indicated that the functional module for which the control instruction is directed is in an abnormal state, specifically, a fault may occur, or the response signal is not normally transmitted due to other reasons, such as a large system data processing amount.
Therefore, in this embodiment, the working state of the functional module is further detected, and the specific detection method may refer to the related art, and the specific detection method is not further limited herein.
If the functional module is found to be faulty, a corresponding prompt signal is sent to the user in one or more modes including but not limited to voice, popup window, image and vibration so as to prompt the existence of the fault, so that the user can know the existing problem and timely remove the fault.
Optionally, after detecting the working state of the functional module for which the control instruction is directed, the method further includes:
Determining the importance level of the control instruction;
and if the functional module is in a non-fault state and the importance level of the control instruction is greater than a preset level threshold, the control instruction is sent to the functional module again.
If the functional module is in a non-fault state, the indication may be that the control command fails to normally transmit or the response signal fails to normally return due to various factors such as data transmission, temporary busy of the functional module, and the like.
If the importance of the processor to send the task that the control instruction performs is low, whether it is not so much affected by the success of its execution, it is not necessary to send the control instruction again, in order to avoid taking up the load of the processor.
Conversely, if the task is relatively important, the control command is resent once to increase the likelihood that the task is being executed normally.
Optionally, the resending the control instruction to the functional module further includes:
and establishing a second timer, and monitoring a response signal for the retransmitted control instruction within the timing duration of the second timer.
Similarly, after the control instruction is resent, in this embodiment, a second timer is further established to monitor the response signal during the time duration of the second timer, which is similar to the above process, and if the response signal is received during the time duration of the second timer, it is indicated that the control instruction is executed in the functional module.
By repeatedly transmitting a relatively important control instruction without receiving a response signal corresponding to the control instruction transmitted for the first time, it is possible to improve the possibility that the control instruction is executed.
In an alternative embodiment, the timing duration of the second timer is less than the timing duration of the first timer.
In this embodiment, if the control command is transmitted for the second time, a valid response signal is not obtained, and the possibility of obtaining a response signal later is low. Therefore, in this embodiment, the timing duration of the second timer is controlled to be smaller than the timing duration of the first timer, and of course, the timing duration of the second timer cannot be shorter than the normal return duration of the response signal. Thus, by setting the timing duration of the second timer, the possibility of receiving the response signal can be improved to a certain extent, and the processor load which may be increased due to the excessively long waiting time can be avoided.
As shown in fig. 3, the control method of the processor of this embodiment may be understood that when a certain command needs to be executed, the processor first sends a control command to the functional module, establishes a timer (the first timer) at the same time, and then starts a function of receiving a response signal corresponding to the control command.
In the timing time range of the timer (the preset time length), if the response signal is received, the function module is indicated to work normally, and at this time, the timer and the function of receiving the response signal can be closed.
If the timer is overtime, that is, the response signal is not received within the preset time length, the functional module may have a fault, and at this time, the timer and the function of receiving the response signal are also closed, so as to reduce the load of the processor.
As shown in fig. 4, an embodiment of the present invention further provides a control device 400 of a processor, including:
a monitoring module 401, configured to monitor a response signal for a control instruction after the processor sends the control instruction to the functional module;
and the interruption module 402 is configured to terminate monitoring the response signal if the response signal is not monitored within a preset duration.
Optionally, the method further comprises:
the establishing module is used for establishing a first timer with the timing duration being the preset duration;
the monitoring module 401 is specifically configured to monitor, during a timing time of the first timer, a response signal for the control instruction;
The interrupt module 402 is specifically configured to terminate monitoring for the response signal if the response signal is not monitored at the end of the timing of the first timer.
Optionally, the method further comprises:
And the closing module is used for closing the first timer if the response signal is monitored.
Optionally, the closing module is further configured to close the first timer after the listening for the answer signal is finished.
Optionally, the method further comprises:
the acquisition module is used for acquiring the working state of the functional module aimed at by the control instruction;
and the prompt signal sending module is used for sending a fault prompt signal to a user if the functional module is in a fault state.
Optionally, the method further comprises:
the determining module is used for determining the importance level of the control instruction;
and the sending module is used for sending the control instruction to the functional module again if the functional module is in a non-fault state and the importance level of the control instruction is greater than a preset level threshold.
Optionally, the establishing module is further configured to establish a second timer, and monitor, during a time duration of the second timer, a reply signal for the retransmitted control instruction.
Optionally, the timing duration of the second timer is smaller than the timing duration of the first timer.
The control device 400 of the processor in this embodiment can implement the processes of the foregoing method embodiments, and achieve substantially the same technical effects, which are not described herein.
Optionally, the embodiment of the present invention further provides an electronic device, including a processor, a memory, and a computer program stored in the memory and capable of running on the processor, where the computer program when executed by the processor implements each process of the embodiment of the control method of the processor, and the process can achieve the same technical effect, so that repetition is avoided, and details are not repeated here.
The embodiment of the invention also provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor, realizes the processes of the control method embodiment of the processor, and can achieve the same technical effects, and in order to avoid repetition, the description is omitted here. The computer readable storage medium is, for example, a Read-Only Memory (ROM), a random access Memory (Random Access Memory RAM), a magnetic disk or an optical disk.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiment of the present invention.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, comprising several instructions for causing a computer device (which may be a personal computer, a server, a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a ROM, a RAM, a magnetic disk, or an optical disk, etc.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
Claims (11)
1. A method of controlling a processor, comprising the steps of:
after the processor sends a control instruction to the functional module, monitoring a response signal aiming at the control instruction;
if the response signal is not monitored within the preset time, ending the monitoring of the response signal; and recovering the hardware load provided by monitoring the response signal, comprising: a corresponding working process and a corresponding memory load of the processor;
acquiring the working state of the functional module aimed at by the control instruction; if the functional module is in a fault state, a fault prompt signal is sent to a user;
determining the importance level of the control instruction; and if the functional module is in a non-fault state and the importance level of the control instruction is greater than a preset level threshold, the control instruction is sent to the functional module again.
2. The method for controlling a processor according to claim 1, wherein after the processor transmits the control instruction, further comprising:
establishing a first timer with the timing duration being the preset duration;
the monitoring response signals for the control instruction comprises the following steps:
monitoring a response signal aiming at the control instruction in the timing time of the first timer;
and if the answer signal is not monitored within the preset time, ending the monitoring of the answer signal, including:
And if the response signal is not monitored at the end of the timing of the first timer, ending the monitoring of the response signal.
3. The method for controlling a processor according to claim 2, wherein after the monitoring of the response signal to the control instruction, further comprising:
And if the response signal is monitored, closing the first timer.
4. The control method of a processor according to claim 2, wherein after the ending of the listening for the response signal, the method further comprises:
closing the first timer.
5. The method of controlling a processor according to claim 1, wherein the resending the control instruction to the functional module further comprises:
and establishing a second timer, and monitoring a response signal for the retransmitted control instruction within the timing duration of the second timer.
6. The method of controlling a processor according to claim 5, wherein a time duration of the second timer is smaller than a time duration of the first timer.
7. A control device for a processor, comprising:
the monitoring module is used for monitoring response signals aiming at the control instructions after the processor sends the control instructions to the functional module;
The interruption module is used for ending the monitoring of the response signal if the response signal is not monitored within the preset duration; and recovering the hardware load provided by monitoring the response signal, comprising: a corresponding working process and a corresponding memory load of the processor;
the acquisition module is used for acquiring the working state of the functional module aimed at by the control instruction;
the first sending module is used for sending a fault prompt signal to a user if the functional module is in a fault state;
the determining module is used for determining the importance level of the control instruction;
and the second sending module is used for sending the control instruction to the functional module again if the functional module is in a non-fault state and the importance level of the control instruction is greater than a preset level threshold.
8. The control device of the processor as set forth in claim 7, further comprising:
the establishing module is used for establishing a first timer with the timing duration being the preset duration;
the monitoring module is specifically configured to monitor a response signal for the control instruction in a timing time of the first timer;
The interrupt module is specifically configured to terminate monitoring of the response signal if the response signal is not monitored when the first timer is finished.
9. The control device of the processor of claim 8, further comprising a shutdown module for shutting down the first timer if the reply signal is detected.
10. An electronic device comprising a processor, a memory and a computer program stored on the memory and executable on the processor, which when executed by the processor, implements the steps of the method of controlling a processor according to any one of claims 1 to 6.
11. A computer-readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the control method of a processor according to any one of claims 1 to 6.
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