CN113097060B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN113097060B CN113097060B CN202010016189.9A CN202010016189A CN113097060B CN 113097060 B CN113097060 B CN 113097060B CN 202010016189 A CN202010016189 A CN 202010016189A CN 113097060 B CN113097060 B CN 113097060B
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
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- 229910052732 germanium Inorganic materials 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate; forming a layer to be etched on a substrate; forming a discrete core layer on the layer to be etched; forming a side wall film on the top and the side wall of the core layer and the surface of the layer to be etched; removing the side wall films on the top of the core layer and the surface of the layer to be etched, reserving the residual side wall films on the side wall of the core layer as side walls, and enclosing a plurality of first grooves by the adjacent side walls on the side wall of the adjacent core layer and the layer to be etched, wherein the first grooves extend along a first direction; forming a blocking layer in part of the first grooves, wherein the blocking layer fills the first grooves along a second direction, and the second direction is perpendicular to the first direction; after the blocking layer is formed, removing the core layer to form a second groove, wherein the second groove is isolated from the first groove by a side wall; and etching the layers to be etched at the bottoms of the first groove and the second groove by taking the side wall and the blocking layer as masks to form target patterns. The embodiment of the invention is beneficial to improving the precision of pattern transfer.
Description
Technical Field
Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the rapid growth of the semiconductor integrated circuit (INTEGRATED CIRCUIT, IC) industry, semiconductor technology continues to advance toward smaller process nodes driven by moore's law, resulting in integrated circuits that are evolving toward smaller volumes, higher circuit precision, and higher circuit complexity.
As integrated circuits develop, the geometry (i.e., the minimum device size that can be created using process steps) generally decreases as the functional density (i.e., the number of interconnect structures per chip) increases, which correspondingly increases the difficulty and complexity of integrated circuit fabrication.
Currently, with the continued scaling of technology nodes, how to increase the matching degree between the patterns formed on the wafer and the target patterns becomes a challenge.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and improves the accuracy of pattern transfer.
In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a layer to be etched on the substrate; forming a discrete core layer on the layer to be etched; forming a side wall film on the top and the side wall of the core layer and the surface of the layer to be etched; removing the side wall films positioned on the top of the core layer and the surface of the layer to be etched, reserving the residual side wall films positioned on the side wall of the core layer as side walls, and enclosing a plurality of first grooves by the adjacent side walls positioned on the side wall of the adjacent core layer and the layer to be etched, wherein the first grooves extend along a first direction; forming a blocking layer in part of the first groove, wherein the blocking layer fills the first groove along a second direction, and the second direction is perpendicular to the first direction; after the blocking layer is formed, removing the core layer to form a second groove, wherein the second groove and the first groove are isolated by the side wall; and etching the layers to be etched at the bottoms of the first groove and the second groove by taking the side wall and the blocking layer as masks to form target patterns.
Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: a substrate; the layer to be etched is positioned on the substrate; the core layer is separated on the layer to be etched; the side walls are positioned on the side walls of the layers to be etched, the adjacent side walls positioned on the side walls of the adjacent core layers and the layers to be etched enclose a plurality of first grooves, and the first grooves extend along a first direction; and the blocking layer is positioned in part of the first groove, the blocking layer fills the first groove along a second direction, the second direction is perpendicular to the first direction, and the blocking layer and the side wall are used as masks for etching the layer to be etched.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
In the method for forming the semiconductor structure, after the side wall film is formed and before the blocking layer is formed, the side wall film positioned on the top of the core layer and the surface of the layer to be etched is removed to form the side wall, so that the side wall film is not formed on the top of the core layer in the step of forming the blocking layer, the blocking layer is prevented from covering the side wall film positioned on the top of the core layer, and if the blocking layer also covers part of the core layer, the step of removing the side wall film positioned on the top of the core layer is not needed, the core layer can be exposed by over etching the blocking layer and the like, the process window for over etching (Overcut) the blocking layer is increased, and therefore, when the core layer is removed, the core layer is easy to remove, the problem of loss caused to the side wall by removing the side wall film positioned on the top of the core layer is also prevented, the process difficulty is correspondingly reduced, the process window is increased, the effect of the blocking layer and the side wall for being used as the etching layer to be etched is also prevented, and the process window is further increased, and the formed mask pattern transfer precision is further improved, and the formed mask process requirement is met.
Drawings
Fig. 1 to 6 are schematic structural views corresponding to steps in a method for forming a semiconductor structure;
Fig. 7 is a partial top view of a semiconductor structure formed using the method of forming the semiconductor structure of fig. 1-6;
FIG. 8 is a schematic diagram of another method for forming a semiconductor structure;
Fig. 9 is a schematic structural diagram corresponding to a method for forming a further semiconductor structure;
Fig. 10 to 20 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
The current method for forming the semiconductor structure has lower pattern transfer precision, and the formed actual pattern is difficult to meet the design requirement. The reason why the pattern transfer accuracy is low is now analyzed in combination with a method of forming a semiconductor structure.
Referring to fig. 1 to 6, schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure are shown.
Referring to fig. 1, a substrate 1 is provided; a metal hard mask material layer 2 is formed on the substrate 1.
With continued reference to fig. 1, a discrete core layer 3 is formed on the metal hard mask material layer 2.
Referring to fig. 2, a sidewall film 4 is formed on the top and the sidewall of the core layer 3 and the surface of the metal hard mask material layer 2, and a trench 5 is defined by the adjacent sidewall film 4 on the sidewall of the adjacent core layer 3 and the sidewall film 4 on the surface of the metal hard mask material layer 2, where the trench 5 extends along a first direction (not labeled).
Referring to fig. 3, a blocking layer 6 is formed in a portion of the trench 5, the blocking layer 6 fills the trench 5 along a second direction (not labeled), the second direction is perpendicular to the first direction, and the blocking layer 6 also covers a portion of the sidewall film 4 on top of the core layer 3 on both sides of the trench 5.
Referring to fig. 4, the sidewall film 4 on the top of the core layer 3 and the surface of the metal hard mask material layer 2 exposed by the blocking layer 6 is removed, the remaining sidewall film 4 on the sidewall of the core layer 3 is used as a sidewall 7, and the adjacent sidewall 7 on the sidewall of the adjacent core layer 3 and the metal hard mask material layer 2 enclose a first groove 8.
Referring to fig. 5, after removing the top of the core layer 3 and the sidewall film 4 on the surface of the metal hard mask material layer 2 exposed by the blocking layer 6, removing the core layer 3 to form a second groove 9, where the first groove 8 and the second groove 9 are isolated by the sidewall 7.
Referring to fig. 6, the metal hard mask material layer 2 at the bottoms of the first groove 8 and the second groove 9 is etched by taking the side wall 7 and the blocking layer 6 as masks, wherein the metal hard mask material layer 2 is etched by taking the side wall 7 as a mask to form a metal hard mask layer 10, and the blocking layer 6 is used as a mask to etch the metal hard mask material layer 2 to form a blocking mask layer 11.
In the above method, after forming the sidewall film 4, the blocking layer 6 is formed in a part of the trench 5, and the blocking layer 6 also covers a part of the sidewall film 4 on top of the core layer 3 on both sides of the trench 4, so that, in the step of removing the sidewall film 4 on top of the core layer 3 and the surface of the metal hard mask material layer 2 exposed by the blocking layer 6, a part of the sidewall film 4 on top of the core layer 3 remains under the coverage of the blocking layer 6, which easily causes the following problems:
Firstly, since the remaining sidewall film 4 also covers part of the top of the core layer 3, this easily results in an increased difficulty in removing the core layer 3, and the core layer 3 is difficult to be removed cleanly;
Secondly, when the sidewall film 4 covered by the blocking layer 6 is etched with the sidewall 7 and the blocking layer 6 as masks, the accuracy of the pattern transfer is easily affected, so that the width of the blocking mask layer 11 is too large, when the substrate 1 is etched with the metal hard mask layer 10 and the blocking mask layer 11 as masks, the dielectric spacers a (as shown in fig. 7) corresponding to the metal hard mask layer 10 are formed in the substrate 1, the blocking structures B (as shown in fig. 7) corresponding to the blocking mask layer 11 are formed in the substrate 1, the interconnection trenches for forming the metal interconnection lines M (as shown in fig. 7) are surrounded between the adjacent dielectric spacers a or the blocking structures B, the blocking structures B may occupy too much space for forming the metal interconnection lines M, resulting in a large filling difficulty of the metal interconnection lines M in the interconnection trenches, and a reduced pattern quality of the metal interconnection lines M (as shown in a dashed box of fig. 7), and even further, the blocking structures B are easily caused to break the metal interconnection lines M at the unwanted breaking positions (as shown by arrows in fig. 7).
In order to prevent the above problems, a method is currently adopted in which, in the step of removing the sidewall film on the top of the core layer and the surface of the metal hard mask material layer exposed by the blocking layer, an etching process is performed to remove the sidewall film on the top of the core layer.
But the difficulty of precisely controlling the over-etching is great. If the over etching is more, as shown in fig. 8, since the material of the sidewall film on top of the core layer 3b is the same as that of the sidewall 7b, the sidewall 7b is easily etched, and further, the height loss of the sidewall 7b is caused (as shown by the dashed line frame in fig. 8), so that it is difficult to ensure that the sidewall 7b is used as an etching mask, and the accuracy of the pattern transfer is easily reduced.
Moreover, if the over etching is more, as shown in fig. 9, the remaining thickness of the blocking layer 6a in the trench 8a may be too small (as shown by a dashed box in fig. 9), so that the blocking layer 6a may be difficult to block, for example: if the top of the remaining blocking layer 6a is lower than the top of the side wall 7a, after etching the substrate 1a by using the patterned metal hard mask material layer and the patterned metal hard mask material layer 2a as a mask, the top surface of the blocking structure formed in the substrate and corresponding to the blocking layer 6a is lower than the top surface of the dielectric layer, and a groove is formed by surrounding the top surface of the blocking structure and the dielectric layer, which easily results in that the pattern formed in the substrate 1a is difficult to meet the process requirement, as an example: when the patterned substrate 1a is used to form metal interconnect lines, adjacent metal interconnect lines are easily filled into the grooves, thereby causing adjacent metal interconnect lines to be shorted to each other (Merge), and thus causing circuit failure.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a layer to be etched on the substrate; forming a discrete core layer on the layer to be etched; forming a side wall film on the top and the side wall of the core layer and the surface of the layer to be etched; removing the side wall films positioned on the top of the core layer and the surface of the layer to be etched, reserving the residual side wall films positioned on the side wall of the core layer as side walls, and enclosing a plurality of first grooves by the adjacent side walls positioned on the side wall of the adjacent core layer and the layer to be etched, wherein the first grooves extend along a first direction; forming a blocking layer in part of the first groove, wherein the blocking layer fills the first groove along a second direction, and the second direction is perpendicular to the first direction; after the blocking layer is formed, removing the core layer to form a second groove, wherein the second groove and the first groove are isolated by the side wall; and etching the layers to be etched at the bottoms of the first groove and the second groove by taking the side wall and the blocking layer as masks to form target patterns.
In the method for forming the semiconductor structure, after the side wall film is formed and before the blocking layer is formed, the side wall film positioned on the top of the core layer and the surface of the layer to be etched is removed, so that the side wall is formed, in the step of forming the blocking layer, the side wall film is not formed on the top of the core layer, the blocking layer is prevented from covering the side wall film positioned on the top of the core layer, and if the blocking layer also covers part of the core layer, the step of removing the side wall film positioned on the top of the core layer is not needed, and the core layer can be exposed by over etching the blocking layer and the like, so that the core layer is easy to remove cleanly when the core layer is removed, the problem of loss to the side wall caused by removing the side wall film positioned on the top of the core layer is also solved, the process difficulty is correspondingly reduced, the process window is increased, the blocking layer and the side wall are also guaranteed to be used as a mask for etching the layer, the pattern transfer precision is further improved, and the formed target pattern meets the process requirement.
In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 10 to 20 are schematic structural views corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 10, a substrate is provided.
The substrate is used for providing a process platform for a subsequent process.
In this embodiment, a semiconductor device such as a transistor or a capacitor may be formed in the substrate, and a functional structure such as a resistor structure or a conductive structure may be formed in the substrate.
In this embodiment, the substrate includes an inter-metal dielectric (IMD) layer 110, and the IMD layer 110 is used to electrically isolate the interconnect lines in a Back end of line (BEOL) process.
The inter-metal dielectric layer 110 is used as a film to be patterned, and after the inter-metal dielectric layer 110 is patterned subsequently, an interconnection trench is formed, where the interconnection trench is used to provide a spatial position for forming an interconnection line.
For this reason, the material of the inter-metal dielectric layer 110 is a low-k dielectric material (low-k dielectric material refers to a dielectric material having a relative dielectric constant of 2.6 or more and 3.9 or less), an ultra-low-k dielectric material (ultra-low-k dielectric material refers to a dielectric material having a relative dielectric constant of less than 2.6), silicon oxide, silicon nitride, silicon oxynitride, or the like. In this embodiment, the material of the inter-metal dielectric layer 110 is an ultra-low k dielectric material, so as to reduce parasitic capacitance between the back-end interconnect lines, and further reduce the back-end RC delay. In particular, the ultra-low k dielectric material may be SiOCH.
With continued reference to fig. 10, a layer to be etched 120 is formed on the substrate.
The layer to be etched 120 is used as a film layer to be patterned to form a target pattern.
In this embodiment, the layer 120 to be etched is a metal hard mask material layer, and the layer 120 to be etched is located on the inter-metal dielectric layer 110.
After patterning the layer to be etched 120, the metal hard mask material layer is formed into a metal hard mask layer, which is used as an etching mask for etching the inter-metal dielectric layer 110 to form an interconnection trench.
In this embodiment, the material of the layer 120 to be etched is silicon nitride. In other embodiments, the material of the layer to be etched may be silicon oxide, silicon oxynitride, silicon carbide, titanium oxide, titanium nitride, tantalum oxide, tantalum nitride, boron nitride, copper nitride, aluminum nitride, or tungsten nitride.
With continued reference to fig. 10, a discrete core layer 130 is formed on the layer 120 to be etched.
The core layer 130 is used to provide support for the subsequent formation of the sidewall film.
Furthermore, the area between the adjacent core layers 130 is further used to define the formation area of the subsequent first grooves, and the position occupied by the core layer 130 is used to define the formation area of the subsequent second grooves.
The core layer 130 is also removed later, so the core layer 130 is a material that is easy to remove, and the process of removing the core layer 130 has less damage to other film layers.
In this embodiment, the material of the core layer 130 is amorphous silicon. In other embodiments, the material of the core layer may be amorphous germanium, silicon oxide, silicon oxynitride, carbon nitride, polysilicon, silicon carbide, silicon carbonitride, or silicon oxycarbonitride.
Referring to fig. 11, a sidewall film 135 is formed on the top and sidewall of the core layer 130 and the surface of the layer 120 to be etched.
The sidewall film 135 is used to form a sidewall. The side wall is used as a partial etching mask for patterning the layer 120 to be etched later.
In this embodiment, the material of the sidewall film 135 is titanium nitride. The titanium nitride material, amorphous silicon, silicon nitride and SiOCH have larger etching selectivity, which is beneficial to ensuring the function of the subsequent side wall as an etching mask for etching the layer to be etched 120 and reducing the loss of the side wall film 135 when the core layer 130 is removed subsequently. In other embodiments, the material of the sidewall film may be titanium oxide or silicon oxide, or other suitable materials, according to actual processes.
In this embodiment, an atomic layer deposition (Atomic deposition layer, ALD) process is used to form the sidewall film 135. The atomic layer deposition process is based on Self-limiting reaction process of atomic layer deposition process, and the film obtained by deposition can reach the thickness of single-layer atoms, because the atomic layer deposition process can accurately deposit one atomic layer in each period, the atomic layer deposition process is selected to be favorable for accurately controlling the thickness of the side wall film 135, and the step coverage performance of the atomic layer deposition process is better, so that the conformal coverage capability of the side wall film 135 on the top and the side wall of the core layer 130 and the surface of the layer 120 to be etched is favorable to be improved, and in addition, the film prepared by the atomic layer deposition process also has the characteristics of good bonding strength, consistent film thickness, good composition uniformity, good conformality and the like, and is favorable for improving the thickness uniformity and the film quality of the side wall film 135.
In other embodiments, other suitable deposition processes may be used to form the sidewall film, depending on the actual process.
Referring to fig. 12, fig. 12a in fig. 12 is a top view, fig. 12b is a cross-sectional view along a-a1 in fig. 12a, the sidewall film 135 on the top of the core layer 130 and the surface of the layer to be etched 120 is removed, the remaining sidewall film 135 on the sidewall of the core layer 130 is remained as a sidewall 140, the adjacent sidewall 140 on the sidewall of the adjacent core layer 130 and the layer to be etched 120 enclose a plurality of first grooves 20, and the first grooves 20 extend along a first direction (as shown in X direction in fig. 12 a).
The sidewall 140 is used as a partial mask for etching the layer 120 to be etched.
In this embodiment, the first grooves 20 extend along a first direction (as shown in an X direction in fig. 12 a), and the plurality of first grooves 20 are arranged along a second direction (as shown in a Y direction in fig. 12 a) perpendicular to the first direction.
The subsequent steps further comprise: a blocking layer is formed in a portion of the first recess 20.
In the method for forming a semiconductor structure provided in the embodiment of the present invention, after the formation of the sidewall film 135 and before the formation of the blocking layer, the sidewall film 135 located on the top of the core layer 130 and on the surface of the layer to be etched 120 is also removed to form the sidewall 140, so in the subsequent step of forming the blocking layer, the sidewall film 135 is not formed on the top of the core layer 130, which is favorable to preventing the problem that the blocking layer also covers the sidewall film 135 located on the top of the core layer 130, and if the blocking layer also covers part of the core layer 130, the step of removing the sidewall film 135 located on the top of the core layer 130 is not needed, and the core layer 130 can be exposed by performing an etching or other mode on the blocking layer, thereby, when the core layer 130 is removed, the core layer 130 is easy to be removed, and also favorable to preventing the problem that the sidewall film 135 located on the top of the core layer 130 is lost, accordingly reducing the process difficulty, increasing the process window, and favorable to ensuring that the blocking layer and the sidewall film 140 are used as the effect of the layer to be etched 120, and further improving the transfer pattern of the layer to be etched, thereby meeting the requirement of forming the pattern of the mask.
Specifically, by removing the sidewall film 135 on the top of the core layer 130 and on the surface of the layer 120 to be etched, it is advantageous to increase the process window for the subsequent over-etching (overcut) of the blocking layer.
In this embodiment, an anisotropic dry etching process is used to remove the sidewall film 135 on top of the core layer 130 and on the surface of the layer 120 to be etched. The anisotropic dry etching process has the characteristic of anisotropic etching, so that in the process of removing the side wall films 135 on the surfaces of the core layer 130 and the layer 120 to be etched, the lateral etching of the side wall films 135 on the side wall of the core layer 130 is less, and the side wall films 135 on the side wall of the core layer 130 can be reserved as side walls 140; moreover, by using a dry etching process, it is advantageous to increase the etching selectivity, thereby reducing damage to other film layers (e.g., the core layer 130) caused by the process of removing the sidewall film 135 on top of the core layer 130 and on the surface of the layer 120 to be etched.
In particular, the anisotropic dry etching process may be an anisotropic plasma etching process.
In this embodiment, the etching selectivity of the plasma etching process to the sidewall film 135 and the core layer 130 is greater than or equal to 5:1, thereby ensuring that the loss to the core layer 130 is small and that the sidewall film 135 on top of the core layer 130 can be stopped on top of the core layer 130 when removed.
Referring to fig. 13, fig. 13a of fig. 13 is a top view, and fig. 13b is a cross-sectional view taken along the direction a-a1 of fig. 13a, a blocking layer 145 is formed in a portion of the first groove 20, and the blocking layer 145 fills the first groove 20 along a second direction (as shown in the direction Y of fig. 13 a), which is perpendicular to the first direction.
The blocking layer 145 and the sidewall 140 together serve as a mask for patterning the layer 120 to be etched later. The blocking layer 145 fills the first groove 20 in the second direction, thereby breaking the first groove 20 in the first direction.
The material of the blocking layer 145 is a dielectric material. In this embodiment, the material of the blocking layer 145 includes silicon oxide. The silicon oxide, the silicon nitride and the amorphous silicon have higher etching selectivity, which is beneficial to reducing the influence of the subsequent process of removing the core layer 130 on the blocking layer 145, ensuring the etching mask effect of the blocking layer 145 when the layer 120 to be etched is etched subsequently, and correspondingly improving the stability of pattern transfer and the pattern transfer precision.
In other embodiments, the material of the blocking layer may be silicon nitride or other materials with higher etching selectivity than the layers to be etched and the core layer according to the materials of the layers to be etched and the core layer.
In this embodiment, in the step of forming the blocking layer 145, the blocking layer 145 also covers part of the top of the core layer 130 at two sides of the first groove 20.
In this embodiment, the step of forming the blocking layer 145 includes: forming a mask layer (not shown) filling the first recess 20 on the core layer 130 and the sidewall 140, wherein a mask opening (not shown) is formed in the mask layer, and the mask opening exposes a portion of the bottom and the sidewall of the first recess 20; filling a blocking material layer (not shown) in the first recess 20 and the mask opening exposed by the mask opening; etching back a portion of the blocking material layer, the remaining blocking material layer being used as the blocking layer 145; and removing the mask layer.
The mask layer is used for defining patterns and forming positions of the blocking material layer, and the mask opening is used for providing space positions for forming the blocking material layer.
The mask layer is made of organic materials such as photoresist, spin-coated carbon and the like. The mask layer may be formed by photolithography processes such as coating, exposure, and development, and this embodiment will not be described herein.
The blocking material layer is used for forming a blocking layer.
In this embodiment, the process of forming the blocking material layer includes a chemical vapor deposition process. In other embodiments, other suitable deposition processes may also be used to form the blocking material layer.
In this embodiment, the process of etching back the blocking material layer with a partial thickness includes a dry etching process.
Specifically, the dry etching process may be a plasma etching process. The plasma etching process has higher etching accuracy and efficiency, and is beneficial to realizing higher etching selection ratio, thereby being beneficial to reducing the probability of generating loss to the side wall 140 and the core layer 130 in the process of etching back the blocking material layer.
And removing the mask layer after etching back the blocking material layer. Specifically, the mask layer may be removed using an ashing process, a wet photoresist removing process, and the like.
The subsequent steps further comprise: the core layer 130 is removed.
Referring to fig. 14 to 16 in combination, in this embodiment, the method for forming a semiconductor structure further includes: after forming the blocking layer 145, the blocking layer 145 on top of the core layer 130 is removed before the core layer 130 is removed.
By removing the blocking layer 145 on top of the core layer 130, the top of the core layer 130 is exposed, providing for subsequent removal of the core layer 130, and preventing the blocking layer 145 on top of the core layer 130 from affecting the accuracy of the pattern transfer.
In this embodiment, the step of removing the blocking layer 145 located on top of the core layer 130 includes:
As shown in fig. 14 and 15, a blocking layer 160 is formed to fill the first recess 20 and cover the blocking layer 145, and the blocking layer 160 exposes the blocking layer 145 on top of the core layer 130.
The shielding layer 160 is used as an etching mask for etching the blocking layer 145.
In this embodiment, the shielding layer 160 is further used as an etching mask for removing the core layer 130 later.
The subsequent steps further comprise: the masking layer 160 is removed. Thus, the shielding layer 160 is a material that is easily removed.
In this embodiment, the material of the shielding layer 160 is an organic material. Specifically, the material of the shielding layer 160 may be an ODL (organic DIELECTRIC LAYER ) material. The filling property of the ODL is better, thereby improving the filling ability of the shielding layer 160 in the first groove 20. In other embodiments, the material of the shielding layer may be another material with better filling performance, such as a Spin-on carbon (SOC) material or a DUO (deep UV light absorbing oxide, deep ultraviolet light absorbing oxide layer).
In this embodiment, the step of forming the shielding layer 160 includes: as shown in fig. 14, an initial shielding layer 150 filling the first recess 20 (as shown in fig. 13) is formed, the initial shielding layer 150 also covering the blocking layer 145; forming an anti-reflection coating 151 on the initial shielding layer 150 and a pattern layer 152 on the anti-reflection coating 151; as shown in fig. 15, the anti-reflection coating 151 and the initial shielding layer 150 are etched in sequence using the pattern layer 152 as a mask, and the remaining initial shielding layer 150 is used as the shielding layer 160.
In this embodiment, the anti-reflection coating 151 is used to reduce the reflection effect during exposure, thereby improving the pattern transfer accuracy. In this embodiment, the anti-reflective coating 151 is a Si-ARC layer, which is advantageous for increasing the depth of field (DOF) of exposure during the photolithography process, improving the uniformity of exposure, and is also advantageous for increasing the hardness of the anti-reflective coating 151 due to the silicon-rich Si-ARC layer, thereby further improving the transfer accuracy of the pattern.
In other embodiments, the anti-reflective coating may also be other suitable anti-reflective materials, such as: BARC (Bottom Anti-REFLECTIVE COATING ) material.
In this embodiment, the pattern layer 152 is used as an etching mask for etching the anti-reflection coating 151 and the initial shielding layer 150. In this embodiment, the material of the pattern layer 152 is photoresist, and the pattern layer 152 may be formed by a photolithography process such as coating, exposure, and development.
In this embodiment, a dry etching process is used, and the anti-reflection coating 151 and the initial shielding layer 150 are etched sequentially using the pattern layer 152 as a mask. The dry etching process has better section control and is beneficial to improving the accuracy of pattern transfer. Specifically, the dry etching process may be a plasma etching process.
In this embodiment, the pattern layer 152 is gradually consumed in the process of etching the anti-reflection coating 151 and the initial shielding layer 150, so that the pattern layer 152 has been removed after the shielding layer 160 is formed.
As shown in fig. 16, the blocking layer 145 exposed by the shielding layer 160 is removed.
In this embodiment, a dry etching process is used to remove the shielding layer 160 to expose the shielding layer 145. Specifically, the process of removing the blocking layer 145 exposed by the shielding layer 160 includes a plasma etching process.
In the step of removing the blocking layer 145 exposed by the shielding layer 160, an etching selectivity ratio of the blocking layer 145 to the sidewall 140 is greater than or equal to 5:1. the etching selectivity of the barrier layer 145 and the side wall 140 is relatively large, so that the probability of damage of the side wall 140 is small in the process of removing the barrier layer 145 exposed by the shielding layer 160, and the etching mask effect of the side wall 140 in the subsequent patterning of the layer 120 to be etched is guaranteed.
In this embodiment, the anti-reflection coating 151 on the blocking layer 160 is gradually consumed in the process of removing the blocking layer 145 exposed by the blocking layer 160, so that the anti-reflection coating 151 is already removed after removing the blocking layer 145 exposed by the blocking layer 160.
After removing the blocking layer 145 exposed by the shielding layer 160, the method for forming a semiconductor structure further includes: the masking layer 160 is removed.
In this embodiment, the process of removing the shielding layer 160 includes an ashing process.
Referring to fig. 17, fig. 17a of fig. 17 is a top view, and fig. 17b is a cross-sectional view taken along a-a1 of fig. 17a, after the blocking layer 145 is formed, the core layer 130 is removed to form a second groove 40, and the second groove 40 and the first groove 20 are isolated by the sidewall 140.
The core layer 130 is removed, so that the layer 120 to be etched at the bottom of the core layer 130 is exposed, and preparation is made for subsequent etching of the layer 120 to be etched at the bottom of the first recess 20 and the second recess 40.
The extending direction of the second grooves 40 is also the first direction, and the plurality of second grooves 40 are arranged along the second direction.
In this embodiment, after forming the sidewall 140 on the sidewall of the core layer 130 to form the first groove 20, removing the core layer 130 to form the second groove 40, where the second groove 40 and the first groove 20 are isolated by the sidewall 140, by forming the first groove 20 and the second groove 40 in different steps, respectively, it is beneficial to reduce the difficulty of forming the first groove 20 and the second groove 40, increase the process window (for example, improve the optical proximity effect), ensure the pattern precision of the first groove 20 and the second groove 40, isolate the first groove 20 and the second groove 40 by the sidewall 140, and also beneficial to meeting the minimum design interval between the first groove 20 and the second groove 40 by controlling the thickness of the sidewall 140, and correspondingly, after forming the target pattern on the layer 120 to be etched at the bottom of the first groove 20 and the second groove 40, it is beneficial to meeting the minimum design interval between the target patterns, and the pattern precision of the target pattern is also improved.
In this embodiment, the sidewall film 135 is not formed on the top of the core layer 130, and the blocking layer 145 is not formed on the top of the core layer 130, that is, a barrier is not formed on the core layer 130 during the process of removing the core layer 130, so that the process window for removing the core layer 130 is advantageously increased, and the core layer 130 is easy to be removed cleanly.
In this embodiment, the process of removing the core layer 130 includes a plasma etching process. By selecting a plasma etching process, a larger etching selectivity ratio is advantageously achieved, so as to reduce damage to other film layers when the core layer 130 is removed, for example: the damage to the side wall 140 is small, so that the etching mask effect of the side wall 140 in the subsequent process of patterning the layer 120 to be etched is ensured.
Specifically, in the step of removing the core layer 130 in this embodiment, the etching selectivity ratio of the core layer 130 to the blocking layer 145 is greater than or equal to 5:1.
In this embodiment, after removing the blocking layer 145 exposed by the shielding layer 160, the core layer 130 is removed before removing the shielding layer 160.
By removing the core layer 130 before removing the shielding layer 160, the shielding layer 160 can be further used as a mask for removing the core layer 130, which is beneficial to improving the process integration degree and the process compatibility.
Accordingly, in this embodiment, the step of removing the core layer 130 includes: the core layer 130 is removed using the blocking layer 160 and the blocking layer 145 as masks.
Referring to fig. 18, the spacer 140 and the blocking layer 145 are used as masks to etch the layer 120 to be etched at the bottoms of the first groove 20 and the second groove 40, so as to form a target pattern.
In this embodiment, the probability of the loss of the sidewall 140 in the foregoing steps is low, and no part of the sidewall film 135 remains, so that the accuracy of pattern transfer is high in the step of etching the layer 120 to be etched at the bottom of the first groove 20 and the second groove 40.
In this embodiment, the layer 120 to be etched is a metal hard mask material layer, so the side wall 140 and the blocking layer 145 are used as masks to etch the layer 120 to be etched at the bottom of the first groove 20 and the second groove 20, thereby forming the metal hard mask layer 170.
The metal hard mask layer 170 is used as an etching mask for etching the inter-metal dielectric layer 110.
In this embodiment, after etching the layer 120 to be etched at the bottom of the first recess 20 and the second recess 40, the metal hard mask layer 170 at the bottom of the blocking layer 145 and the sidewall 140 adjacent to the blocking layer 145 is used as a metal blocking layer 170a, and the metal blocking layer 170a does not occupy a space between adjacent metal hard mask layers 170 along the second direction (as shown in the Y direction in fig. 17 a).
The inter-metal dielectric layer 110 is etched to form a blocking structure using the metal blocking layer 170a as a mask.
Referring to fig. 19 in combination, fig. 19a in fig. 19 is a top view, and fig. 19b is a cross-sectional view along aa1 in fig. 19a, in this embodiment, after forming the metal hard mask layer 170, the method for forming a semiconductor structure further includes: and etching the inter-metal dielectric layer 110 by taking the metal hard mask layer 170 as a mask, and forming a plurality of interconnection trenches 60 in the inter-metal dielectric layer 110.
The interconnect trenches 60 are used to provide spatial locations for forming interconnect lines.
In this embodiment, the interconnection trenches 60 extend along a first direction, the plurality of interconnection trenches 60 are arranged along a second direction, and the plurality of interconnection trenches 60 are isolated by the remaining inter-metal dielectric layer 110.
In this embodiment, the inter-metal dielectric layer 110 is etched by using the metal blocking layer 170a as a mask, the inter-metal dielectric layer 110 located at the bottom of the metal blocking layer 170a is used as a blocking structure 110a, and the blocking structure 110a blocks the same interconnection trench 60 along the first direction, so that the interconnection line formed in the interconnection trench 60 where the blocking structure 110a is located subsequently can be disconnected at the position of the blocking structure 110 a.
In the present embodiment, the blocking structure 110a does not occupy the space of the interconnect trench 60 in the second direction, thereby preventing an influence on the pattern of the interconnect trench 60 and the filling of the interconnect line in the interconnect trench 60.
Referring to fig. 20 in combination, fig. 20a is a top view and fig. 20b is a cross-sectional view taken along a-a1 of fig. 20a, the interconnect trench 60 (shown in fig. 19) is filled with an interconnect line 180.
In this embodiment, the interconnection 180 is a metal layer. In this embodiment, the material of the interconnect 180 is copper. In other embodiments, the material of the interconnect line may be a conductive material such as cobalt, tungsten, aluminum, etc.
In this embodiment, the interconnect lines 180 are isolated from each other by the remaining intermetal dielectric layer 110.
Wherein the interconnect line 180 located in the interconnect trench 60 where the blocking structure 110a is located is disconnected by the blocking structure 110a at the location of the blocking structure 110 a.
In this embodiment, the pattern quality of the blocking structure 110a is better, so the pattern quality of the interconnect line 180 is higher, the line edge roughness is lower, and the pattern quality of the disconnection of the interconnect line 180 at the position of the blocking structure 110a is higher, which is beneficial to improving the filling capability of the interconnect line 180 in the interconnect trench 60 and preventing the disconnection problem of the interconnect line 180 at the position where the disconnection is not required.
In summary, the embodiment of the invention is beneficial to improving the electrical connection reliability of the semiconductor structure, so that the formed interconnection pattern meets the design requirement. In particular, embodiments of the present invention are advantageous in enabling the pattern of interconnect lines to meet the requirements of a circuit design.
In this embodiment, the step of forming the interconnection line 180 includes: forming a conductive layer (not shown) on the inter-metal dielectric layer 110 to fill the interconnect trench 60; and removing the conductive layer higher than the inter-metal dielectric layer 110, and filling the remaining conductive layer in the interconnection trench 60 to serve as the interconnection line.
Correspondingly, the invention further provides a semiconductor structure. Referring to fig. 16, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate; a layer to be etched 120 located on the substrate; a core layer 130, which is separated from the layer 120 to be etched; the side walls 140 are located on the side walls of the layer 120 to be etched, and a plurality of first grooves 20 (as shown in fig. 12) are defined by the adjacent side walls 140 located on the side walls of the adjacent core layers 130 and the layer 120 to be etched, and the first grooves 20 extend along a first direction (as shown in an X direction in fig. 12 a); and the blocking layer 145 is located in a part of the first groove 20, the blocking layer 145 fills the first groove 20 along a second direction (as shown in a Y direction in fig. 13B), the second direction is perpendicular to the first direction, and the blocking layer 145 and the side wall 140 are used as masks for etching the layer 120 to be etched.
In the semiconductor structure provided by the embodiment of the invention, the side wall 140 is only positioned on the side wall of the core layer 130, and the material (such as the side wall film) of the side wall 140 is not arranged on the top of the core layer 130, so that the blocking layer 145 does not cover the side wall film positioned on the core layer 130 even if the blocking layer 145 is positioned on part of the core layer 130, and therefore, in the forming step of the blocking layer 145, the core layer 130 can be exposed by over etching the blocking layer 145, and the like, and the subsequent step further comprises removing the core layer 130, so that the core layer 130 is easy to remove cleanly, and the blocking layer 145 and the side wall 140 are favorable for being used as a mask for etching the layer 120 to be etched, thereby improving the pattern transfer precision and enabling the formed target pattern to meet the process requirement.
The substrate is used for providing a process platform for a process.
In this embodiment, a semiconductor device such as a transistor or a capacitor may be formed in the substrate, and a functional structure such as a resistor structure or a conductive structure may be formed in the substrate.
In this embodiment, the substrate includes an inter-metal dielectric layer 110, and the inter-metal dielectric layer 110 is used to realize electrical isolation between interconnection lines in a back-end-of-line process.
The inter-metal dielectric layer 110 is used as a film to be patterned, and after the inter-metal dielectric layer 110 is patterned subsequently, an interconnection trench is formed, where the interconnection trench is used to provide a spatial position for forming an interconnection line.
In this embodiment, the material of the intermetal dielectric layer 110 is an ultra-low k dielectric material. In particular, the ultra-low k dielectric material may be SiOCH.
The layer to be etched 120 is used as a film layer to be patterned to form a target pattern.
In this embodiment, the layer 120 to be etched is a metal hard mask material layer, and the layer 120 to be etched is located on the inter-metal dielectric layer 110.
After the layer to be etched 120 is patterned, the metal hard mask material layer is formed into a metal hard mask layer, and the metal hard mask layer is used as an etching mask for etching the inter-metal dielectric layer 110 to form an interconnection trench. In this embodiment, the material of the layer 120 to be etched is silicon nitride.
The core layer 130 is used to provide support for the formation of the sidewall 140.
In this embodiment, the material of the core layer 130 is amorphous silicon.
The sidewall 140 is used as a mask for patterning the layer 120 to be etched.
In this embodiment, the material of the sidewall 140 is titanium nitride.
In this embodiment, the sidewall 140 is only located on the sidewall of the core layer 130, which is beneficial to enlarging the process window for over-etching when forming the blocking layer 145.
The blocking layer 145 and the sidewall 140 together serve as a mask for patterning the layer 120 to be etched.
The blocking layer 145 fills the first groove 20 in the second direction, thereby breaking the first groove 20 in the first direction.
The blocking layer 145 is made of a dielectric material. In this embodiment, the blocking layer 145 includes silicon oxide. In other embodiments, the material of the blocking layer may be silicon nitride or other materials with higher etching selectivity than the layers to be etched and the core layer according to the materials of the layers to be etched and the core layer.
In this embodiment, the blocking layer 145 exposes the core layer 130, so as to prevent the blocking layer 145 from affecting the subsequent removal of the core layer 130, which is beneficial to reducing the removal difficulty of the subsequent removal of the core layer 130, and further facilitates the removal of the core layer 130.
The semiconductor structure further includes: and a shielding layer 160 filled in the first groove 20, wherein the shielding layer 160 covers the top of the blocking layer 145, and the side wall of the shielding layer 160 along the first direction is flush with the side wall of the blocking layer 145.
The shielding layer 160 is used as a mask for subsequently removing the core layer 130; and the blocking layer 145 exposes the core layer 130 because the blocking layer 145 on top of the core layer 130 was also removed before, the blocking layer 160 also serves as a mask for removing the blocking layer 145 on top of the core layer 130.
In this embodiment, the material of the shielding layer 160 is an organic material. Specifically, the material of the shielding layer 160 may be an ODL material. The filling performance of the ODL is better, so that the filling capability of the shielding layer 160 in the first groove 20 is improved.
The semiconductor structure may be formed by the forming method described in the foregoing embodiments, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (14)
1. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a layer to be etched on the substrate;
Forming a discrete core layer on the layer to be etched;
forming a side wall film on the top and the side wall of the core layer and the surface of the layer to be etched;
removing the side wall films positioned on the top of the core layer and the surface of the layer to be etched, reserving the residual side wall films positioned on the side wall of the core layer as side walls, and enclosing a plurality of first grooves by the adjacent side walls positioned on the side wall of the adjacent core layer and the layer to be etched, wherein the first grooves extend along a first direction; forming a blocking layer in part of the first groove, wherein the blocking layer fills the first groove along a second direction, the second direction is perpendicular to the first direction, and in the step of forming the blocking layer, the blocking layer also covers part of the top of the core layer at two sides of the first groove;
after the blocking layer is formed, removing the core layer to form a second groove, wherein the second groove and the first groove are isolated by the side wall; the method for forming the semiconductor structure further comprises the following steps: removing the blocking layer positioned on the top of the core layer before removing the core layer after forming the blocking layer;
And etching the layers to be etched at the bottoms of the first groove and the second groove by taking the side wall and the blocking layer as masks to form target patterns.
2. The method of claim 1, wherein an anisotropic dry etching process is used to remove sidewall films on top of the core layer and on the surface of the layer to be etched.
3. The method of forming a semiconductor structure of claim 1, wherein removing the blocking layer on top of the core layer comprises: forming a shielding layer filling the first groove and covering the blocking layer, wherein the shielding layer exposes the blocking layer positioned on the top of the core layer;
Removing the blocking layer exposed by the shielding layer;
after removing the blocking layer exposed by the shielding layer, the method for forming the semiconductor structure further comprises the following steps: and removing the shielding layer.
4. The method of claim 3, wherein removing the blocking layer exposed by the masking layer comprises a plasma etching process.
5. The method of forming a semiconductor structure as claimed in claim 3, wherein in the step of removing the blocking layer exposed by the shielding layer, an etching selectivity ratio of the blocking layer to the sidewall is greater than or equal to 5:1.
6. The method of forming a semiconductor structure of claim 4, wherein the core layer is removed after removing the blocking layer exposed by the blocking layer and before removing the blocking layer;
the step of removing the core layer includes: and removing the core layer by taking the shielding layer and the blocking layer as masks.
7. The method of forming a semiconductor structure of claim 3, wherein the process of removing the masking layer comprises an ashing process.
8. The method of forming a semiconductor structure of claim 1, wherein the step of forming the blocking layer comprises: forming a mask layer filling the first groove on the core layer and the side wall, wherein a mask opening is formed in the mask layer, and the mask opening exposes part of the bottom and the side wall of the first groove;
filling a blocking material layer in the first groove exposed by the mask opening and the mask opening;
etching back part of the blocking material layer with the thickness, wherein the rest blocking material layer is used as the blocking layer;
and removing the mask layer.
9. The method of forming a semiconductor structure of claim 8, wherein the process of forming the blocking material layer comprises a chemical vapor deposition process.
10. The method of forming a semiconductor structure of claim 8, wherein the process of etching back a portion of the thickness of the blocking material layer comprises a dry etching process.
11. The method of forming a semiconductor structure of claim 1, wherein the process of removing the core layer comprises a plasma etch process.
12. The method of forming a semiconductor structure of claim 1, wherein in the step of removing the core layer, an etch selectivity of the core layer and the blocking layer is greater than or equal to 5:1.
13. The method of forming a semiconductor structure of claim 1, wherein the material of the blocking layer comprises silicon oxide or silicon nitride.
14. The method of forming a semiconductor structure of claim 1, wherein the substrate comprises an inter-metal dielectric layer;
the layer to be etched is a metal hard mask material layer and is positioned on the inter-metal dielectric layer;
etching the layers to be etched at the bottoms of the first groove and the second groove by taking the side wall and the blocking layer as masks to form a metal hard mask layer;
After the metal hard mask layer is formed, the method for forming the semiconductor structure further comprises the following steps: and etching the inter-metal dielectric layer by taking the metal hard mask layer as a mask, and forming a plurality of interconnection grooves in the inter-metal dielectric layer.
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| CN103839769A (en) * | 2012-11-20 | 2014-06-04 | 华邦电子股份有限公司 | pattern forming method |
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