CN113094206A - High-speed data access method and device based on error correction - Google Patents
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Abstract
The invention discloses a high-speed data access method and a device based on error correction, wherein the method comprises the following steps: when writing data: grouping all original data according to the size of a storage unit, acquiring a first preset number of groups of original data as a section, extracting one bit from each group of original data to form a group of data to be encoded, and generating a group of error correction encoded data based on the group of data to be encoded until all bits of each group of original data are subjected to an error correction encoding process; and writing a group of data to be encoded and a corresponding group of error correction encoded data into a third number of logic units bit by bit, wherein each logic unit is written with one bit of data. The invention realizes that the abnormal errors of a single storage unit are corrected by utilizing the storage array coding while ensuring the data throughput, avoids the data errors caused by the abnormal single storage unit and improves the system reliability.
Description
Technical Field
The invention relates to the technical field of data storage, in particular to a high-speed data access method and device based on error correction.
Background
With the development of solid-state storage technology, various high-speed solid-state flash memories are applied to various instruments and devices as storage media of data, and most of the solid-state storage devices are NAND FLASH, so that a part of storage units can not be used normally, namely bad blocks can be generated in the production and use processes of the solid-state storage devices due to problems of production processes and the like. Bad blocks generated after solid-state storage leaves a factory can be removed from unusable parts generally through modes of initialization scanning, storage space mapping and the like, but the bad blocks generated in the using process need to carry out error check on the memory through modes of ECC (error correction code) checking and the like, the checked bad blocks are listed in storage space mapping management, the storage space is remapped, and the work of the part is generally managed by a file system. In some embedded high-speed application scenarios, the general file system is already unavailable due to the ultra-high data throughput (GByte/s).
Existing data access is generally divided into two types, namely a file system and a non-file system:
1. the method with the file system generally uses an embedded core processor with an operating system (linux system) to manage a peripheral solid-state storage device, and the method has the advantages of convenient operation and high reliability, but cannot support the use scene with the requirement of ultrahigh-speed read-write bandwidth due to the limitation of parallel processing capacity and the like.
2. The method without the file system can adopt a scheme of taking the FPGA as a core processing unit to directly drive the plug-in memory device, has high concurrent processing capacity and the advantage of ultrahigh-speed read-write bandwidth, but the problem of the stored bad blocks needs to be processed by a more complex scheme of initialization, dynamic bad block inspection, memory space mapping and the like, and the management complexity is increased along with the increase of the number of the mounted memory units.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a high-speed data access method and a high-speed data access device based on error correction, which can ensure data reliability while ensuring that data throughput meets the requirement of ultrahigh-speed read-write bandwidth, and the technical scheme is as follows:
in a first aspect, a high-speed data access method based on error correction is provided, which is applied to read-write control of a flash solid-state memory device, and includes:
when writing data: grouping all original data according to the size of a storage unit, acquiring a first preset number of groups of original data as a section, extracting one bit (bit) from each group to form a group of data to be encoded for the section of original data, and generating a group of error correction encoded data based on the group of data to be encoded until all bits of each group of original data are subjected to an error correction encoding process;
writing a set of data to be encoded and a corresponding set of error correction encoded data bit by bit into a third number of Logical Units (LUNs), each logical unit writing a bit of data;
when reading data, reading data from each logic unit, and obtaining original data through decoding and error correction.
In a possible implementation manner, after performing error detection and error correction on the read data, the method further includes:
adding an abnormal storage record for a storage unit with error data bits in the logic unit;
monitoring whether the abnormal storage recording times of the same storage unit are greater than a preset threshold value or not;
if so, generating an updating request for a mapping table of the physical address and the logical address of the data storage space;
and updating the mapping table based on the updating request in an idle state.
In a possible implementation manner, one of the Logic Units (LUN) corresponds to one chip select enable signal input terminal to implement individual control of the read-write process of each logic unit.
In a possible implementation manner, when the group of data to be encoded and the corresponding group of error correction coded data are written into a third number of Logical Units (LUNs) bit by bit and data are read, the data reading and writing speed is improved by controlling the third number of Logical Units (LUNs) to be simultaneously enabled.
In one possible implementation, the error correction coding process employs a hamming code coding algorithm.
In one possible implementation, the logic unit is located in a FLASH granule of a FLASH solid-state storage device, the FLASH solid-state storage device includes 8 FLASH granules, and one FLASH granule includes 4 logic units.
In a second aspect, there is provided an error correction based high speed data access apparatus comprising:
the original data unit error correction coding unit is used for grouping all original data according to the size of a storage unit, acquiring a first preset number of groups of original data as a section, extracting one bit (bit) from each group of original data to form a group of data to be coded, and generating a group of error correction coded data based on the group of data to be coded until all bits of each group of original data are subjected to an error correction coding process;
original data and coded data writing unit, writing a group of data to be coded and a corresponding group of error correction coded data into a third number of Logic Units (LUNs) bit by bit, each logic unit writing one bit of data;
and the read data unit is used for reading data from each logic unit and obtaining original data through decoding and error correction.
In a possible implementation manner, the error correction based high-speed data access apparatus further includes: the abnormal storage unit management unit is used for adding an abnormal storage record to the storage unit with the error data bit in the logic unit; and when the abnormal storage recording times of the same storage unit are larger than a preset threshold value, generating an updating request for the mapping table of the physical address and the logical address of the data storage space, and updating the mapping table based on the updating request in an idle state.
In a third aspect, the application of the high-speed data access method in a high-speed camera based on an FPGA is provided, where the FPGA controls a solid-state storage array composed of a plurality of FLASH particles to read and write high-speed image data.
The high-speed data access method and device based on error correction have the following beneficial effects: the invention realizes that abnormal errors occurring in a single storage unit are corrected by utilizing storage array coding while ensuring data throughput through the combination setting of a plurality of storage units, the setting of a selection method of the original data bits participating in a coding process when the original data is subjected to error correction coding and the setting of a method of writing the generated error correction coding into the storage units, thereby avoiding the data errors caused by the abnormality of the single storage unit and improving the reliability of the system.
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FIG. 1 is a flow chart of an error correction encoding and writing process for a piece of original data according to an embodiment of the present invention;
FIG. 2 is a flow chart of reading data in an embodiment of the present invention;
FIG. 3 is a schematic diagram of a writing process for a set of data to be encoded in the present invention;
FIG. 4 is a schematic diagram of read/write control of the flash solid-state memory device by the FPGA in the high-speed camera according to the present invention;
FIG. 5 is a block diagram of the high speed data access device based on error correction according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail with reference to the accompanying drawings, the described embodiments should not be construed as limiting the present invention, and all other embodiments obtained by a person of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.
The embodiment of the invention discloses an error correction-based high-speed data access method, which is applied to read-write control of an FPGA (field programmable gate array) to a FLASH solid-state storage device in an FPGA-based high-speed camera, wherein the FPGA realizes the read-write of high-speed image data by controlling a solid-state storage array consisting of a plurality of FLASH particles, and the access process of the high-speed image data specifically comprises the following steps: each high-speed image data is collected by a high-speed image collecting sensor and transmitted to the FPGA, and the FPGA controls a solid-state storage array consisting of 8 FLASH particles. The high-speed image sensor transmits the acquired image data to the FPGA, and the FPGA encodes the data after receiving the original image data. The encoded data is written to the solid-state storage array. And after the data acquisition is finished, reading out the image data according to the data reading space given by the upper computer, and decoding the read-out image data and outputting the original image data to the upper computer. Wherein, the FPGA is used for controlling the solid-state storage array composed of 8 FLASH particles,
when writing data:
grouping all original data according to the size of a storage unit, and acquiring a first preset number of groups of original data as a section;
the encoding and writing process for a piece of original data comprises:
(1) extracting one bit (bit) from each group to form a group of data to be encoded, and performing an error correction encoding process on the basis of the group of data to be encoded to generate a group of error correction encoded data;
(2) repeating the step (1) until all bits of each group of original data are subjected to an error correction coding process;
(3) writing a group of data to be encoded and a corresponding group of error correction encoded data into a third number of Logical Units (LUNs) bit by bit, each logical unit writing one bit of data, that is, each logical unit enabling one storage unit to store one bit of data;
(4) and (4) repeating the step (3) until a section of original data and the corresponding error correction coding data finish the writing process.
When reading data, reading data from each logic unit, and obtaining original data through decoding and error correction.
In the writing process, one bit (bit) is extracted from each group of the first preset number of groups of original data to form a group of data to be encoded, namely the number of bits of the group of data to be encoded is a first preset number, the number of bits of the obtained group of data to be encoded can be determined based on the first preset number of bits of the data to be encoded and a preset error correction coding algorithm, and the number of bits of the group of data to be encoded is recorded as a second number;
in this embodiment, for example that the first preset number is 11, and one storage unit of all logic units stores 8-bit data, the size of a group of original data is 8 bits, and the size of a segment of original data is 11 × 8 bits, that is, 11 bytes, and the error correction coding and writing processes for the 11 bytes are as follows:
numbering the 1 st group, the 2 nd group,. 11 th group of each group of original data, and numbering the 1 st bit, the 2 nd bit,. 8 th bit of each group of data;
extracting the 1 st bit from each group of the 1 st to 11 th groups of original data to form a 1 st group of data to be encoded, and encoding the 1 st group of data to be encoded by taking a Hamming code encoding algorithm as an example to generate 5-bit error correction encoded data;
extracting 2 nd bits from each group of 1 st to 11 th original data to form 2 nd group data to be encoded to form corresponding 5-bit error correction encoded data;
similarly, extracting the jth bit and jth group of data to be encoded (j is less than or equal to 8) from each group of 1 st to 11 th groups of original data to form corresponding 5-bit error correction encoded data;
writing 11 bits of the 1 st group of data to be encoded and corresponding 5-bit error correction encoded data into 16 logic units, numbering each bit of storage space in the logic units according to bits, wherein the 1 st bit and the 2 nd bit are coded.8 th bit, and the 16-bit data are sequentially written into the 1 st bit of each logic unit;
sequentially writing 11 bits of the 2 nd group of data to be encoded and corresponding 5-bit error correction encoded data into the 2 nd bit of each logic unit;
similarly, the 11 bits of the jth group of data to be encoded and the corresponding 5-bit error correction encoded data are written into the jth bit of each logic unit in turn.
Correspondingly, the process of decoding and correcting errors when reading data can be as follows:
and reading the j-th data of the 1 st to 16 th logic units one by one, and decoding and correcting errors of the read data to obtain original data.
In the embodiment of the present invention, a second number of values are obtained by setting a first preset number of values and selectively setting an error correction coding scheme, and a third number, which is the number of logic units required for a segment of original data and a storage process of error correction coded data corresponding to the segment of original data, is further obtained, for example, 16 logic units are required for accessing the segment of original data.
The embodiment of the invention sets the selection method of the original data bit participating in the primary coding process when the original data is subjected to error correction coding through the combination of a plurality of storage units, and sets the method of writing the generated error correction coding into the storage units:
on the first hand, the error correction processing of the read data is realized, the data error caused by the damage of a single unit is avoided, and the influence of the failure of a certain storage unit on the whole system is eliminated by encoding the original data.
In a second aspect, in this embodiment, a single control of the read-write process of each logic unit is implemented by corresponding one Logic Unit (LUN) to one chip select enable signal input end, and when a group of data to be encoded and a corresponding group of error correction encoded data are written into a third number of Logic Units (LUNs) and read data bit by bit, the data read-write speed is increased by controlling the third number of Logic Units (LUNs) and simultaneously enabling the data read-write speed, that is, the data processing bandwidth is increased by controlling the storage unit array in parallel. The accuracy of data storage of the solid-state storage device is improved while high-speed access is guaranteed, the correctness of data reading can be guaranteed when a small number of storage units fail due to the service life problem, and the service life of the storage system is prolonged.
In the third aspect, compared with the design of improving data reliability by setting a redundant disk array of a RAID in the prior art, the embodiment of the present invention refines the size of a unit storage unit by adding physical storage units that can be operated simultaneously, simplifies the control operation method, and improves the real-time processing capability by relating the control operation method to the stored data blocks.
On the basis of ensuring the data throughput and the data reliability, the embodiment further includes managing normal and abnormal memory cells in the entire flash solid-state memory device after performing error detection and error correction on the read data, and specifically includes:
adding an abnormal storage record for a storage unit with error data bits in the logic unit;
monitoring whether the abnormal storage recording times of the same storage unit are greater than a preset threshold value or not;
if so, generating an updating request for a mapping table of the physical address and the logical address of the data storage space;
and updating the mapping table based on the updating request in an idle state.
In the embodiment of the invention, the position information of an abnormal storage unit is counted in the decoding process of reading data each time, and based on the reading and writing operations on the flash solid-state memory device for many times and the position information counting result of the abnormal storage unit for many times, when the abnormal storage recording times of the same storage unit is more than a preset threshold value, the storage unit at the position is judged to be an abnormal physical storage unit, the mapping table of the physical address and the logical address is dynamically updated, and the abnormal physical storage unit is removed from the mapping table.
The embodiment of the invention also provides a high-speed data access device based on error correction, which comprises:
the original data unit error correction coding unit is used for grouping all original data according to the size of a storage unit, acquiring a first preset number of groups of original data as a section, extracting one bit (bit) from each group of original data to form a group of data to be coded, and generating a group of error correction coded data based on the group of data to be coded until all bits of each group of original data are subjected to an error correction coding process;
original data and coded data writing unit, writing a group of data to be coded and a corresponding group of error correction coded data into a third number of Logic Units (LUNs) bit by bit, each logic unit writing one bit of data;
the read data unit is used for reading data from each logic unit and obtaining original data through decoding and error correction;
the abnormal storage unit management unit is used for adding an abnormal storage record to the storage unit with the error data bit in the logic unit; and when the abnormal storage recording times of the same storage unit are larger than a preset threshold value, generating an updating request for the mapping table of the physical address and the logical address of the data storage space, and updating the mapping table based on the updating request in an idle state.
For the specific definition of the high-speed data access apparatus based on error correction in this embodiment, refer to the above definition of a high-speed data access method based on error correction, and are not described herein again. The units can be realized in a software form, and the corresponding operation of the units is called and executed based on the FPGA.
The present invention is not limited to the above-described embodiments, and those skilled in the art will be able to make various modifications without creative efforts from the above-described conception, and fall within the scope of the present invention.
Claims (9)
1. A high-speed data access method based on error correction is applied to read-write control of a flash solid-state storage device and is characterized by comprising the following steps:
when writing data:
grouping all original data according to the size of a storage unit, acquiring a first preset number of groups of original data as a section, extracting one bit (bit) from each group to form a group of data to be encoded for the section of original data, and generating a group of error correction encoded data based on the group of data to be encoded until all bits of each group of original data are subjected to an error correction encoding process;
writing a set of data to be encoded and a corresponding set of error correction encoded data bit by bit into a third number of Logical Units (LUNs), each logical unit writing a bit of data;
when reading data, reading data from each logic unit, and obtaining original data through decoding and error correction.
2. An error correction based high speed data access method according to claim 1, comprising: after the error detection and correction are performed on the read data, the method further includes:
adding an abnormal storage record for a storage unit with error data bits in the logic unit;
monitoring whether the abnormal storage recording times of the same storage unit are greater than a preset threshold value or not;
if so, generating an updating request for a mapping table of the physical address and the logical address of the data storage space;
and updating the mapping table based on the updating request in an idle state.
3. A high-speed data access method based on error correction according to claim 1, characterized in that a single control of the read/write process of each logical unit is implemented by one of said Logical Units (LUN) corresponding to one of the chip select enable signal inputs.
4. A high-speed data access method based on error correction according to claim 3, characterized in that, when writing a group of data to be encoded and a corresponding group of data to be encoded into a third number of Logical Units (LUN) bit by bit and reading data, the data read-write speed is increased by controlling the simultaneous enablement of the third number of Logical Units (LUN).
5. An error correction based high speed data access method according to claim 1, comprising: the logic unit is located in a FLASH granule of a FLASH solid-state storage device, the FLASH solid-state storage device comprises 8 FLASH granules, and one FLASH granule comprises 4 logic units.
6. An error correction based high speed data access method according to claim 1, comprising: the error correction coding process adopts a Hamming code coding algorithm.
7. An error correction based high speed data access apparatus, comprising:
the original data unit error correction coding unit is used for grouping all original data according to the size of a storage unit, acquiring a first preset number of groups of original data as a section, extracting one bit (bit) from each group of original data to form a group of data to be coded, and generating a group of error correction coded data based on the group of data to be coded until all bits of each group of original data are subjected to an error correction coding process;
original data and coded data writing unit, writing a group of data to be coded and a corresponding group of error correction coded data into a third number of Logic Units (LUNs) bit by bit, each logic unit writing one bit of data;
and the read data unit is used for reading data from each logic unit and obtaining original data through decoding and error correction.
8. The high speed data access device based on error correction according to claim 1, further comprising: the abnormal storage unit management unit is used for adding an abnormal storage record to the storage unit with the error data bit in the logic unit; and when the abnormal storage recording times of the same storage unit are larger than a preset threshold value, generating an updating request for the mapping table of the physical address and the logical address of the data storage space, and updating the mapping table based on the updating request in an idle state.
9. Use of the high speed data access method of any of claims 1-6 in an FPGA-based high speed camera, wherein: the FPGA realizes the reading and writing of high-speed image data by controlling a solid-state storage array consisting of a plurality of FLASH particles.
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