CN113078431A

CN113078431A - Broadband high-flatness terahertz chip-to-chip interconnection structure

Info

Publication number: CN113078431A
Application number: CN202110324624.9A
Authority: CN
Inventors: 王政; 马熙辰; 谢倩
Original assignee: University of Electronic Science and Technology of China
Current assignee: University of Electronic Science and Technology of China
Priority date: 2021-03-26
Filing date: 2021-03-26
Publication date: 2021-07-06
Anticipated expiration: 2041-03-26
Also published as: CN113078431B

Abstract

The invention belongs to the field of terahertz chips, and particularly provides a broadband high-flatness terahertz chip-to-chip interconnection structure which comprises two chip-to-chip coupling structures, wherein dielectric waveguides are arranged in axial symmetry with respect to the dielectric waveguides, the chip-to-chip coupling structure based on coplanar waveguides is designed, and the dielectric waveguides are connected to the chip-to-chip coupling structures in a covering mode, so that chip signals can be coupled to the dielectric waveguides from the chip through the chip-to-chip coupling structures and transmitted to another chip through the chip-to-chip coupling structures after being transmitted through the dielectric waveguides, and chip-to-chip interconnection is realized. The on-chip coupling structure based on the coplanar waveguide is based on the principle characteristics of the transmission line, such as smooth transition, no additional structures such as balun and mode converter, and the like, so that the inter-chip interconnection structure realizes the terahertz signal transmission with broadband, high flatness and low loss, has a simple structure, small occupied area, easy processing and low cost, and effectively solves the problems of high loss and large in-band fluctuation of the traditional terahertz interconnection structure.

Description

Broadband high-flatness terahertz chip-to-chip interconnection structure

Technical Field

The invention belongs to the field of terahertz chips, and particularly relates to a broadband high-flatness terahertz chip-to-chip interconnection structure.

Background

Due to the characteristic that the working frequency of the terahertz chip is very high, the traditional metal connecting wire is used as an inter-chip interconnection wire to bring great limitation to a terahertz system, and the terahertz inter-chip interconnection structure is used as an important component of the terahertz system, has the function of transmitting data between chips at high speed and with low loss, and has good anti-interference capability. At present, an inter-chip interconnection structure mostly adopts photoelectric/electro-optical conversion, dielectric waveguide and the like; the dielectric waveguide has the characteristics of low production cost, simple structure and easiness in integration. The on-chip coupling structure is used as an excitation source of the dielectric waveguide, so that energy can be transmitted between chips more efficiently, and the overall efficiency of the system is improved.

At present, the common efficiency of the reported on-chip coupling structures is not satisfactory, and the in-band fluctuation is large, so that the signal intensity is not stable enough, and some dielectric waveguides with complicated production flows need to be used, so that the production cost and the structural complexity of the dielectric waveguides are improved, and the terahertz chip interconnection based on the dielectric waveguides is still limited greatly.

Disclosure of Invention

The invention aims to provide a broadband high-flatness terahertz chip-to-chip interconnection structure aiming at the problem that the existing terahertz chip-to-chip interconnection based on dielectric waveguide is still greatly limited, so that the efficiency of the interconnection structure is improved, and in-band fluctuation is inhibited.

In order to achieve the purpose, the technical scheme adopted by the invention is as follows:

a broadband high-flatness terahertz chip-to-chip interconnection structure comprises: a dielectric waveguide and two on-chip coupling structures 2 arranged axisymmetrically with respect to the dielectric waveguide; it is characterized in that the preparation method is characterized in that,

the on-chip coupling structure 2 comprises: the device comprises a silicon substrate 2-1, an oxide layer 2-2, a passivation layer 2-3, a signal line 2-4 and a metal ground, wherein the metal comprises: the device comprises a bottom layer metal ground 2-5 and an upper layer metal ground 2-6, wherein the bottom layer metal ground 2-5 is arranged on a silicon substrate 2-1, an oxidation layer 2-2 is arranged on the bottom layer metal ground 2-5, a signal line 2-4 and the upper layer metal ground 2-6 are both embedded into the upper surface of the oxidation layer 2-2, and a passivation layer 2-3 covers the oxidation layer 2-2;

the dielectric waveguide 1 is a rectangular dielectric waveguide, the dielectric waveguide is connected to the passivation layer 2-3, the dielectric waveguide completely covers the signal line 2-4, and the signal line 2-4 is located right below the dielectric waveguide.

Further, the upper-layer metal ground 2-6 is formed by two side metal grounds, the signal line 2-4 is formed by connecting two periodic structure units and is positioned in the middle of the two side metal grounds, the length of each unit is lambda, and the center of each unit is symmetrically provided with a branch joint in the orthogonal direction.

Further, the dielectric waveguide and the on-chip coupling structure are connected through a connection adhesive 3.

Furthermore, the distance between the two side metal grounds is 1/2 lambda, and the coverage area of the bottom metal ground is larger than that of the upper metal ground.

Further, the length of the branch node is less than 1/4 lambda, and the branch node is not in contact with the side metal ground.

Compared with the prior art, the invention has the beneficial effects that:

the invention provides a broadband high-flatness terahertz chip-to-chip interconnection structure which comprises a dielectric waveguide and two chip-to-chip coupling structures which are arranged in axial symmetry with respect to the dielectric waveguide, wherein the dielectric waveguide is covered and connected on the chip-to-chip coupling structures based on the coplanar waveguide by adopting the design of the chip-to-chip coupling structures based on the coplanar waveguide, so that chip signals can be coupled into the dielectric waveguide from the chip through the chip-to-chip coupling structures, and then transmitted to another chip through the chip-to-chip coupling structures after being transmitted through the dielectric waveguide, and chip-to-chip interconnection is realized. The on-chip coupling structure based on the coplanar waveguide is based on the principle characteristics of the transmission line, such as smooth transition, no additional structures such as balun and mode converter, and the like, so that the inter-chip interconnection structure realizes the terahertz signal transmission with broadband, high flatness and low loss, has a simple structure, small occupied area, easy processing and low cost, and effectively solves the problems of high loss and large in-band fluctuation of the traditional terahertz interconnection structure.

Drawings

Fig. 1 is a schematic diagram of an interconnection structure between broadband high-flatness thz plates according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of an interconnection structure between broadband high-flatness terahertz plates in an embodiment of the invention.

Fig. 3 is a schematic diagram of an on-chip coupling structure based on coplanar waveguides in an embodiment of the present invention.

Fig. 4 is a graph showing the insertion loss and return loss results of the broadband high-flatness terahertz chip-to-chip interconnection structure in the embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples.

The embodiment provides a broadband high-flatness terahertz inter-wafer interconnection structure, an overall structure of which is shown in fig. 1, and specifically includes: the dielectric waveguide on-chip coupling structure comprises two on-chip coupling structures 2 and a dielectric waveguide 1, wherein the two on-chip coupling structures 2 and the dielectric waveguide 1 are arranged in axial symmetry and are based on coplanar waveguides, and the dielectric waveguide 1 is covered and connected on the on-chip coupling structures 2 based on the coplanar waveguides through a connecting glue 3; signals from the chip firstly enter the on-chip coupling structure based on the coplanar waveguide at one end, then are coupled into the dielectric waveguide by the on-chip coupling structure based on the coplanar waveguide, are transmitted to the on-chip coupling structure based on the coplanar waveguide at the other end through the dielectric waveguide, and finally enter another chip.

More specifically:

in this embodiment, the dielectric waveguide 1 is made of high-impedance silicon, and has a width of 500um, a height of 250um, and a length of 6500 um;

the structure of the coplanar waveguide-based on-chip coupling structure 2 is shown in fig. 2, and comprises: the device comprises a silicon substrate 2-1, an oxide layer 2-2, a passivation layer 2-3, a signal line 2-4 and a metal ground, wherein the metal comprises a bottom metal ground 2-5 and an upper metal ground 2-6, the bottom metal ground 2-5 is arranged on the silicon substrate 2-1, the oxide layer 2-2 is arranged on the bottom metal ground 2-5, the signal line 2-4 and the upper metal ground 2-6 are embedded into the upper surface of the oxide layer 2-2, and the passivation layer 2-3 covers the signal line 2-4, the upper metal ground 2-6 and the oxide layer 2-2; the upper layer metal ground is formed by two side metal grounds, and the distance between the two side metal grounds is 1/2 lambda; the signal line 2-4 is formed by connecting two periodic structure units and is positioned in the middle of metal grounds 2-6 at two sides, the length of each unit is lambda, a branch node in the orthogonal direction is symmetrically arranged at the center of each unit, the length of the branch node is less than 1/4 lambda so as to ensure that the branch node is not contacted with a side metal ground, the signal line is connected with a chip through an impedance transformation structure, and the length of the impedance transformation structure is 1/4 lambda, as shown in fig. 3; λ is the operating wavelength;

the dielectric waveguide 1 is connected to a passivation layer 2-3 of the on-chip coupling structure 2 based on the coplanar waveguide through a connecting glue 3, the dielectric waveguide 1 completely covers the signal line 2-4, and the signal line 2-4 is located right below the dielectric waveguide.

When the interconnection structure is adopted to realize the interconnection of terahertz chips, in the on-chip coupling structure 2 based on the coplanar waveguide, the silicon substrate 2-1 corresponds to the silicon substrate of the chip, the bottom metal ground 2-5 corresponds to the bottom metal of the chip, the signal line 2-4 and the upper metal ground 2-6 correspond to the top thick metal of the chip, and the signal line is connected with the chip through the impedance transformation structure.

Based on the broadband high-flatness terahertz chip-to-chip interconnection structure provided by the embodiment, lower transmission loss and smaller in-band signal fluctuation can be realized; as shown in fig. 4, the insertion loss and the return loss of the interconnection structure between the broadband high-flatness terahertz chips in this embodiment are shown, where the abscissa is frequency and the unit is GHz, the ordinate is S-parameter amplitude value and the unit is dB, as can be seen from the figure, the minimum insertion loss in the band is-4.2 dB, and the 3dB bandwidth is about 33 GHz.

While the invention has been described with reference to specific embodiments, any feature disclosed in this specification may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise; all of the disclosed features, or all of the method or process steps, may be combined in any combination, except mutually exclusive features and/or steps.

Claims

1. A broadband high-flatness terahertz inter-chip interconnect structure, comprising: a dielectric waveguide and two on-chip coupling structures (2) arranged axially symmetrically about the dielectric waveguide; it is characterized in that,

The on-chip coupling structure (2) includes: a silicon substrate (2-1), an oxide layer (2-2), a passivation layer (2-3), a signal line (2-4) and a metal ground, wherein the The metal ground includes: a bottom metal ground (2-5) and an upper metal ground (2-6), the bottom metal ground (2-5) is disposed on the silicon substrate (2-1), and the oxide layer ( 2-2) is arranged on the bottom metal ground (2-5), the signal line (2-4) and the upper metal ground (2-6) are embedded in the upper surface of the oxide layer (2-2), and the passivation The layer (2-3) covers the oxide layer (2-2);

The dielectric waveguide (1) is a rectangular dielectric waveguide, the dielectric waveguide is connected to the passivation layer (2-3), the dielectric waveguide completely covers the signal line (2-4), and the signal line (2-4) is located on the side of the dielectric waveguide. Directly below.

2. The broadband high-flatness terahertz inter-chip interconnect structure according to claim 1, wherein the upper metal ground (2-6) is composed of two side metal grounds, and the signal line (2-6) is composed of two side metal grounds. 4) It is composed of two periodic structural units connected and located in the middle of the metal ground on both sides, the length of each unit is λ, and the center of each unit is symmetrically arranged with a branch in an orthogonal direction.

3. The broadband high-flatness terahertz inter-chip interconnect structure according to claim 1, wherein the dielectric waveguide and the on-chip coupling structure are connected by a connecting glue (3).

4. The broadband high-flatness terahertz inter-chip interconnect structure according to claim 2, wherein the spacing between the two side metal grounds is 1/2λ, and the coverage area of the underlying metal ground should be greater than The coverage area of the upper metal ground.

5. The broadband high-flatness terahertz inter-chip interconnect structure according to claim 2, wherein the length of the branch is less than 1/4λ, and the branch is not in contact with the side metal ground.