CN113053816B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN113053816B CN113053816B CN201911378954.5A CN201911378954A CN113053816B CN 113053816 B CN113053816 B CN 113053816B CN 201911378954 A CN201911378954 A CN 201911378954A CN 113053816 B CN113053816 B CN 113053816B
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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Abstract
The application provides a semiconductor structure and a forming method thereof, wherein the semiconductor structure is embedded into a semiconductor substrate in most of a gate oxide layer of a high-voltage device area, so that the high-voltage device area and a non-high-voltage device area have nearly horizontal surfaces after the gate oxide layer is formed. The forming method of the semiconductor structure comprises the following steps: providing a semiconductor substrate, wherein a plurality of isolation structures are formed in the semiconductor substrate, a liner oxide layer and a mask layer are sequentially formed on the surface of the semiconductor substrate, the mask layer is provided with first openings, and the first openings correspond to the semiconductor substrate and part of the isolation structures among the isolation structures; removing the liner oxide layer exposed by the first opening; etching the semiconductor substrate to enable the semiconductor substrate between the isolation structures to form a recessed part similar to a sigma shape; and growing a gate oxide layer in the concave part.
Description
Technical Field
The present application relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
Various devices such as high voltage devices and low voltage devices are commonly included in integrated circuits, and high voltage devices typically use a thicker gate oxide to maintain a higher operating voltage, such as a gate-driven high voltage device for a Thin Film Transistor (TFT), which typically can reach 1100 angstroms.
Before a gate oxide layer of a high-voltage device is manufactured, a sacrificial oxide layer needs to be formed on a semiconductor substrate and then removed, so that the height difference between a high-voltage device area and a low-voltage device area or a medium-voltage device area is reduced, and the height difference is caused by the thick gate oxide layer of the high-voltage device area. However, the presence of the sacrificial oxide layer may affect the stress of the trench isolation structure in the semiconductor substrate, which in turn affects the performance of the low voltage device or the medium voltage device. In the subsequent process of removing the sacrificial oxide layer, a large recess may be formed at the interface between the trench isolation structure and the semiconductor substrate, the recess surrounds the active region of the high-voltage device, the performance of the semiconductor structure is affected, and residue of the metal gate may be caused in the subsequent process of manufacturing the metal gate of the high-voltage device.
Therefore, in order to solve the above technical problems, it is necessary to provide a new semiconductor structure and a method for fabricating the same.
Disclosure of Invention
The application provides a semiconductor structure and a forming method thereof, wherein the semiconductor structure is embedded into a semiconductor substrate in most of a gate oxide layer of a high-voltage device area, so that the high-voltage device area and a non-high-voltage device area have nearly horizontal surfaces after the gate oxide layer is formed.
One aspect of the present application provides a method for forming a semiconductor structure, including: providing a semiconductor substrate, wherein a plurality of isolation structures are formed in the semiconductor substrate, a liner oxide layer and a mask layer are sequentially formed on the surface of the semiconductor substrate, the mask layer is provided with first openings, and the first openings correspond to the semiconductor substrate and part of the isolation structures among the isolation structures; removing the liner oxide layer exposed by the first opening; etching the semiconductor substrate to form a sigma-like recessed part on the semiconductor substrate between the isolation structures; and growing a gate oxide layer in the concave part.
Optionally, the method further includes, after forming the Σ -like shaped recess: and removing part of the isolation structure at the joint of the concave part and the isolation structure, and exposing the top end of the concave part.
Optionally, after growing the gate oxide layer in the recess, the method further includes: and removing the mask layer.
Optionally, after removing the mask layer, the method further includes: and thinning the liner oxide layer.
Optionally, the semiconductor substrate includes a high-voltage device region and a non-high-voltage device region, and the gate oxide layer is formed in the high-voltage device region.
Optionally, the semiconductor substrate is etched by a dry etching process or a wet etching process, so that the semiconductor substrate between the isolation structures forms a recessed portion similar to a sigma shape.
Optionally, in the wet etching process, the etching solution includes TMAH.
Optionally, the etching gas in the dry etching process includes CF 4 。
Optionally, a gate oxide layer is grown in the recess by a thermal oxidation process.
Another aspect of the present application also provides a semiconductor structure, comprising: a semiconductor substrate; an isolation structure in the semiconductor substrate; a pad oxide layer on the surface of the semiconductor substrate; and the gate oxide layer is positioned between the isolation structures and in the semiconductor substrate which is not covered by the liner oxide layer.
Optionally, the semiconductor substrate includes a high-voltage device region and a non-high-voltage device region, and the gate oxide layer is located in the high-voltage device region.
Optionally, the gate oxide layer is formed by thermally oxidizing the sigma-like shaped recess in the semiconductor substrate.
Optionally, the surface of the gate oxide layer is substantially even with the surface of the pad oxide layer.
According to the semiconductor structure and the forming method thereof, the semiconductor structure is embedded into the semiconductor substrate in most of the gate oxide layer of the high-voltage device area, so that the high-voltage device area and the non-high-voltage device area have horizontal surfaces after the gate oxide layer is formed.
Drawings
The following drawings describe in detail exemplary embodiments disclosed in the present application. Wherein like reference numerals refer to similar structures throughout the several views of the drawings. Those of ordinary skill in the art will understand that the present embodiments are non-limiting, exemplary embodiments and that the accompanying drawings are for illustrative and descriptive purposes only and are not intended to limit the scope of the present disclosure, as other embodiments may equally fulfill the inventive intent of the present application. It should be understood that the drawings are not to scale. Wherein:
FIG. 1 is a schematic diagram of a semiconductor structure for a high voltage device region;
FIG. 2 is a schematic structural diagram of a semiconductor substrate including a high voltage device region and a non-high voltage device region;
fig. 3 to 9 are schematic structural diagrams of steps of a semiconductor structure forming method according to an embodiment of the present disclosure.
Detailed Description
The following description is presented to enable any person skilled in the art to make and use the present disclosure, and is provided in the context of a particular application and its requirements. Various local modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present disclosure. Thus, the present disclosure is not to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.
The technical solution of the present invention will be described in detail below with reference to the embodiments and the accompanying drawings.
Referring to fig. 1, a schematic structural diagram of a semiconductor structure of a high voltage device region is shown, where a first Well 101 and a second Well 102(Well) are formed in a semiconductor substrate 100, and the first Well 101 and the second Well 102 are formed by lightly doping the semiconductor substrate 100, where the first Well 101 and the second Well 102 may be doped N-type or P-type, for example, the first Well 101 is doped P-type, the second Well 102 is doped N-type, and more than one Drift region (Drift) may also be formed in both the first Well 101 and the second Well 102, for example, the first Drift region 111 and the second Drift region 112, optionally, the doping types of the first Drift region 111 and the second Drift region 112 are opposite to the doping type of the Well corresponding to the position, for example, the first Drift region 111 is doped N-type, and the second Drift region 112 is doped P-type. A first isolation structure 151 for isolating the first and second transition regions 111 and 112 is also formed in the semiconductor substrate. In the semiconductor substrate, a plurality of second isolation structures 161 are further formed, and the second isolation structures 161 are used for lengthening the length of a migration region of an active device which is formed in the semiconductor substrate later.
A Pad Oxide layer (Pad Oxide)131 is also formed on the surface of the semiconductor substrate and used as a protective layer on the surface of the semiconductor substrate. In the active region between the second wells 102, a gate oxide layer 141 is to be formed on the semiconductor substrate, and since a high voltage device requires a higher operating voltage, the thickness of the gate oxide layer 141 is much higher than that of a non-high voltage device region, especially a low voltage device region. The thickness d of the gate oxide layer 141 can be up to 1100 angstroms, for example. In the subsequent process of forming an interlayer dielectric layer (ILD), since the thickness of the gate oxide layer 141 is much greater than that of the non-high voltage device region, the gate layer of the high voltage device region is also much greater than that of other device regions, and when the interlayer dielectric layer grinding process is performed, a part, even most, of the gate layer of the high voltage device region is ground, thereby causing the loss of the gate layer of the high voltage device region.
Based on this, the present application provides a method for forming a semiconductor structure, comprising:
step S1, providing a semiconductor substrate, wherein a plurality of isolation structures are formed in the semiconductor substrate, a pad oxide layer and a mask layer are sequentially formed on the surfaces of the semiconductor substrate and the isolation structures, the mask layer is provided with a first opening, and the first opening corresponds to the semiconductor substrate and part of the isolation structures between the isolation structures;
step S2, removing the pad oxide layer exposed by the first opening;
step S3, etching the semiconductor substrate to form a sigma-like concave part on the semiconductor substrate between the isolation structures; and growing a gate oxide layer in the concave part.
Referring to fig. 2, a semiconductor substrate 200 is provided, wherein the semiconductor substrate 200 includes a high voltage device region 200B and a non-high voltage device region 200A, and the high voltage device region 200B and the non-high voltage device region 200A are not drawn to scale and are only schematically shown in the drawing. For clarity and convenience of illustration, fig. 3 to 9 of the present embodiment only schematically illustrate a local position (schematically indicated by a dashed box) in the high-voltage device region 200B.
The semiconductor substrate 200 may be at least one of the following materials: si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, or other III/V compound semiconductors, and further includes a multilayer structure composed of the material layers or silicon-on-insulator (SOI), stacked-on-insulator (SSOI), or the like. In this embodiment, the constituent material of the semiconductor substrate 200 is single crystal silicon or silicon on insulator.
Referring to fig. 3, a well region 201 is formed in the semiconductor substrate 200 through a doping process, a doping ion type of the well region 201 may be an N type or a P type, and a migration region is further formed in the well region 201 according to a process requirement, which is not shown in fig. 3 to 9 for clarity of the drawings. The doped ion type of the migration region is opposite to that of the well region.
A plurality of isolation structures are also formed in the semiconductor substrate for lengthening the length of the migration region. The isolation structure may include a linear oxide layer 202 and an insulating dielectric layer 203, where the linear oxide layer 202 may be made of, for example, a silicon oxide layer, and may be formed by a thermal oxidation process, and the insulating dielectric layer 203 may be made of, for example, silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the insulating dielectric layer 203 is made of silicon oxide, and a process for forming the insulating dielectric layer 203 may be a chemical vapor deposition process or a physical vapor deposition process, and the chemical vapor deposition process may be a High Aspect Ratio (HARP) deposition process. Of course, the isolation structure may also be any other known trench isolation structure, and the formation method of the isolation structure may also be any manufacturing method of a trench isolation structure, which is not limited in this application.
A pad oxide layer 204 is further formed on the surface of the semiconductor substrate 200 as a protection layer of the semiconductor substrate 200. The pad oxide layer 204 may be formed before the plurality of isolation structures are formed, or may be formed after the plurality of isolation structures are formed. In this embodiment, the material of the pad oxide layer 204 is silicon oxide, and the process for forming the pad oxide layer 204 may be a thermal oxidation process, a chemical vapor deposition process, an atomic layer deposition process, a physical vapor deposition process, or the like.
Referring to fig. 4, the surface of the pad oxide layer 204 further includes a mask layer 205. The mask layer 205 serves as a mask for a subsequent etching process and a protective layer for the semiconductor substrate 200 and the pad oxide layer 204. In this embodiment, the mask layer 205 is made of silicon nitride (SiN), and a process of forming the mask layer 205 is a Chemical Vapor Deposition (CVD) process. The thickness of the mask layer 205 is, for example, 200 to 700 angstroms, and optionally, 400 to 500 angstroms, for example.
Because the stress of the mask layer 205 is relatively large, when the mask layer 205 is formed on the semiconductor substrate 200, dislocation is easily caused on the surface of the semiconductor substrate 200, and the pad oxide layer 204 is also used as a buffer for forming the mask layer 205, so that the problem of dislocation generated when the mask layer 205 is directly formed on the semiconductor substrate 200 is avoided; in addition, the pad oxide layer 204 may also serve as a stop layer in the subsequent step of removing the mask layer 205.
The mask layer 205 has a first opening 206, and the first opening 206 corresponds to the semiconductor substrate between the isolation structures and a portion of the isolation structures. The region corresponding to the first opening 206 is also the channel region of the high voltage device. The first opening is formed in order to expose the active region between the isolation structures and a small part of the isolation structure close to the active region in a subsequent etching process. And the purpose of exposing the active region between the isolation structures is to form a concave part in the semiconductor substrate subsequently, and the purpose of exposing the small part of the isolation structure close to the active region is to etch and remove the small part of the exposed isolation structure so as to completely expose the top of the concave part.
Referring to fig. 5, the liner oxide layer 204 exposed by the first opening 206 is removed. The process of removing the pad oxide layer 204 is, for example, a wet etching process. In some embodiments of the present application, the liner oxide layer 204 exposed by the first opening 206 may be removed using an HF acid solution. Optionally, the wet etching process may be performed after HF with a concentration of 49% and deionized water are diluted in a ratio of 1: 150-300 (HF is 1). In the process of removing the pad oxide layer 204, since the material of the pad oxide layer 204 is the same as that of the insulating dielectric layer in the isolation structure, the insulating dielectric layer in the isolation structure exposed by the first opening 206 may also be etched to the same extent. After the pad oxide layer 204 exposed by the first opening 206 is removed, the exposed surface of the semiconductor substrate 200 is the (100) surface of the polysilicon lattice.
Referring to fig. 6, the semiconductor substrate 200 is etched, so that the semiconductor substrate 200 between the isolation structures forms a recessed portion 207 with a sigma-like shape; the etching starts from the (100) surface of the semiconductor substrate 200. Due to the shielding effect of the isolation structure or the different etching rates of the etching solution in different directions, a sigma-like shaped recess 207 is formed in the semiconductor substrate 200.
In some embodiments of the present application, the semiconductor substrate 200 is etched by a dry etching process, and the semiconductor substrate will form the Σ -like shaped recess 207 due to the shielding effect of the isolation structure. In the embodiment of the present application, the dry etching is, for example, plasma etching, and the etching gas includes CF 4 。
In other embodiments of the present application, a wet etching process is used to etch the semiconductor substrate 200, and the semiconductor substrate will also form the Σ -like shaped recess 207 due to different etching rates of the etching solution in different directions. The wet etching is performed by using an etching solution containing TMAH (tetramethylammonium hydroxide), for example, wherein the mass percentage concentration of TMAH in the etching solution is 1% to 3%, for example, 2.38%.
In the process of etching the semiconductor substrate 200 to form the Σ -like shaped recess 207 by using a wet etching process, 180 to 220 angstroms of semiconductor substrate portions, for example, 190 angstroms, 200 angstroms, 210 angstroms, etc., are etched and removed. The etching reaction can be performed at normal temperature, for example, 15 to 35 degrees celsius, and optionally, 23 to 25 degrees celsius.
The reaction mechanism of etching with the etching solution containing the TMAH is as follows:
Si+4OH→Si(OH) 4 +4e -
4e - +4H 2 O→4OH - +2H 2 ↓ (oxygen-free atmosphere)
4e - +2H 2 O+O 2 →4OH - (aerobic atmosphere)
Wherein, the etching rate is greatly influenced by the existence of oxygen, and the etching rate can be controlled by controlling the flow of the oxygen. In this embodiment, an alternative etch rate range is 30 angstroms per minute to 70 angstroms per minute, such as 50 angstroms per minute.
The following table 1 shows the etching rate of the polysilicon on different crystal planes and the etching rate ratio of the polysilicon to the polysilicon on the basis of the etching solution at the temperature of 79.8 ℃ and the mass percent of the TMAH in the etching solution of 20%. The large difference in the etch rate and the etch rate ratio causes the formation of the Σ -like shaped recess 207.
TABLE 1
Referring to fig. 7, after forming the recess 207 having a Σ -like shape, the method further includes: and removing part of the isolation structure at the junction of the recess 207 and the isolation structure to expose the top end 207a of the recess 207. The process can be realized by selecting a large etching solution for silicon oxide and silicon etching, for example, an HF acid solution is used to pre-clean the interface between the isolation structure and the recess 207, so that a portion of the insulating dielectric layer 203 at the interface between the isolation structure and the recess 207 can be removed to expose the top 207a of the recess 207, and thus, in the subsequent process of thermally oxidizing the recess 207 to form the gate oxide layer 208, the top 207a of the recess 207 can also be completely oxidized.
Referring to fig. 8, a gate oxide layer 208 is grown within the recess 207. Optionally, a gate oxide layer is grown in the recess by using a thermal oxidation process. The thermal oxidation process may be performed in a furnace tube. The formed gate oxide layer 208 is positioned in the semiconductor substrate 200, and by controlling the process conditions, the upper surface of the gate oxide layer 208 should be horizontal to the upper surface of the gate oxide layer formed in the non-high voltage device area. In the subsequent process for forming the interlayer dielectric layer, the process for grinding the interlayer dielectric layer cannot firstly grind the gate of the high-voltage device area, so that the high-voltage device area is not affected.
Referring to fig. 9, the mask layer 205 is removed. The process for removing the mask layer 205 is, for example, a wet etching process, and a solution adopted by the wet etching process is, for example, a phosphoric acid solution.
After removing the mask layer, optionally, the method may further thin the pad oxide layer 204. The process for thinning the pad oxide layer 204 is, for example, a wet etching process.
An embodiment of the present application further provides a semiconductor structure, which is shown in fig. 9 and includes: a semiconductor substrate 200; the isolation structure is positioned in the semiconductor substrate 200 and can comprise a linear oxidation layer 201 and an insulating medium layer 203; a pad oxide layer 204 on the surface of the semiconductor substrate 200; a gate oxide layer 208 located in the semiconductor substrate 200 between the isolation structures and not covered by the pad oxide layer 204.
The semiconductor substrate comprises a high-voltage device area and a non-high-voltage device area, and the gate oxide layer is located in the high-voltage device area. In an embodiment of the present application, the gate oxide layer 208 is formed by thermally oxidizing the sigma-like shaped recess 207 in the semiconductor substrate 200 (the recess 207 refers to fig. 6 and 7).
In the embodiment of the present application, the gate oxide layer 208 is embedded in the semiconductor substrate, and the surface of the gate oxide layer 208 is close to the surface of the pad oxide layer 204 and is horizontal to the upper surface of the gate oxide layer formed in the non-high voltage device region.
In conclusion, upon reading the present detailed disclosure, those skilled in the art will appreciate that the foregoing detailed disclosure can be presented by way of example only, and not limitation. Those skilled in the art will appreciate that the present application is intended to cover various reasonable variations, adaptations, and modifications of the embodiments described herein, although not explicitly described herein. Such alterations, improvements, and modifications are intended to be suggested by this disclosure, and are within the spirit and scope of the exemplary embodiments of this disclosure.
It is to be understood that the term "and/or" as used herein includes any and all combinations of one or more of the associated listed items. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present.
Similarly, it will be understood that when an element such as a layer, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term "directly" means that there are no intervening elements. It will be further understood that the terms "comprises," "comprising," "includes" and/or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be further understood that, although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be termed a second element in other embodiments without departing from the teachings of the present invention. The same reference numerals or the same reference identifiers denote the same elements throughout the specification.
Further, exemplary embodiments are described by referring to cross-sectional illustrations and/or plan illustrations that are idealized exemplary illustrations. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Thus, example embodiments should not be construed as limited to the shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of exemplary embodiments.
Claims (12)
1. A method of forming a semiconductor structure, comprising:
providing a semiconductor substrate, wherein a plurality of isolation structures are formed in the semiconductor substrate, a liner oxide layer and a mask layer are sequentially formed on the surface of the semiconductor substrate, the mask layer is provided with first openings, and the first openings correspond to the semiconductor substrate and part of the isolation structures among the isolation structures;
removing the liner oxide layer exposed by the first opening;
etching the semiconductor substrate to form a sigma-like recessed part on the semiconductor substrate between the isolation structures;
and growing a gate oxide layer in the concave part.
2. The method of forming a semiconductor structure of claim 1, wherein after forming the Σ -like shaped recess, the method further comprises: and removing part of the isolation structure at the joint of the concave part and the isolation structure, and exposing the top end of the concave part.
3. The method of forming a semiconductor structure of claim 1, further comprising: and removing the mask layer.
4. The method of forming a semiconductor structure of claim 3, wherein after removing the mask layer, the method further comprises: and thinning the liner oxide layer.
5. The method of forming a semiconductor structure of claim 1, wherein said semiconductor substrate comprises a high voltage device region and a non-high voltage device region, said gate oxide layer being formed in the high voltage device region.
6. The method for forming a semiconductor structure according to claim 1, wherein the semiconductor substrate is etched by a dry etching process or a wet etching process, so that the semiconductor substrate between the isolation structures forms a sigma-like shaped recess.
7. The method for forming a semiconductor structure according to claim 6, wherein the etching liquid in the wet etching process comprises TMAH.
8. The method of forming a semiconductor structure of claim 6, wherein the etching gas in the dry etching process comprises CF 4 。
9. The method of forming a semiconductor structure of claim 1, wherein a thermal oxidation process is used to grow a gate oxide layer within said recess.
10. A semiconductor structure, comprising:
a semiconductor substrate;
an isolation structure in the semiconductor substrate;
a pad oxide layer on the surface of the semiconductor substrate;
and the gate oxide layer is positioned between the isolation structures and in the semiconductor substrate which is not covered by the liner oxide layer, wherein the gate oxide layer is formed by thermally oxidizing the sigma-like-shaped concave part positioned in the semiconductor substrate.
11. The semiconductor structure of claim 10, wherein said semiconductor substrate includes a high voltage device region and a non-high voltage device region, said gate oxide layer being located in the high voltage device region.
12. The semiconductor structure of claim 10, wherein a surface of said gate oxide layer is substantially planar with a surface of said liner oxide layer.
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