CN112992245B - Efuse cell structure, double-row structure of efuse cell and application circuit of efuse cell structure - Google Patents
Efuse cell structure, double-row structure of efuse cell and application circuit of efuse cell structure Download PDFInfo
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- CN112992245B CN112992245B CN202011562191.2A CN202011562191A CN112992245B CN 112992245 B CN112992245 B CN 112992245B CN 202011562191 A CN202011562191 A CN 202011562191A CN 112992245 B CN112992245 B CN 112992245B
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Abstract
The invention provides an efuse unit structure, a double-row structure of the efuse unit and an application circuit of the efuse unit structure, wherein the efuse unit structure comprises a programming fuse and a reference fuse; the first NMOS tube and the second NMOS tube; one end of the reference fuse is a SAref port of the efuse unit structure, and the other end of the reference fuse is connected with the drain electrode of the second NMOS tube; one end of the programming fuse is a bit line port of the efuse unit structure, and the other end of the programming fuse is connected with the drain electrode of the first NMOS tube; the gates of the first NMOS tube and the second NMOS tube are connected to form a word line port of the efuse unit structure; the source electrodes of the first NMOS tube and the second NMOS tube are connected to form a grounding port of the efuse unit structure. The efuse unit structure adopts non-fusing programming operation to the fuse, reduces the requirement on required programming current, can work under lower programming voltage, and greatly reduces the power consumption of the system. And meanwhile, the small difference between the programming fuse and the reference fuse can be reliably compared, and a non-fusing mechanism is adopted, so that the required programming current is smaller, and the whole area of the efuse is reduced.
Description
Technical Field
The present invention relates to the field of integrated circuit design, and more particularly, to an efuse cell structure, a double-row structure of an efuse cell, and an application circuit of the efuse cell structure.
Background
EFuses belong to one-time programmable memories (OTPs) and implement programming functions by blowing fuses based on the Electromigration (EM) principle. The internal reading module of the efuse converts the resistance value of the fuse into a corresponding logic value, and the working principle is that the comparison circuit is used for comparing the fuse resistance before and after the fusing with a reference resistance to generate different levels. To ensure reliability of the comparison result, conventional efuse designs all want fuse blowing during programming operation to obtain a larger resistance. Thus, conventional efuse cells all contain a control tube of a larger W/L size to enable the passage of a larger fuse current, which directly results in a larger efuse area and greater overall power consumption.
Conventional efuse cells implement programming operations by blowing fuses based on electromigration principles. Because of the large fuse current required for programming, conventional efuses require a high programming voltage; while in read operation, the system uses lower voltages to reduce power consumption. Therefore, the conventional efuse adopts a dual power supply (VDD, VDDQ) structure, as shown in fig. 1, fig. 1 shows a circuit schematic diagram of the conventional efuse structure, and when the system is in a programming operation, a programming current flows from VDDQ, through P1, link and N1 pipes to ground, so as to realize programming of the efuse. During a read operation of the system, a read current is converted from VDD, SA, through link and N1 pipe to ground, and a current value related to the resistance value of an efuse fuse (link) is converted into a logic output DO at SA (Sensor Amplifier).
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide an efuse cell structure, a double-row structure of the efuse cell and an application circuit of the efuse cell structure for solving the problems of large efuse area and large overall power consumption in the prior art.
To achieve the above and other related objects, the present invention provides an efuse cell structure including at least:
a fuse pair consisting of a programming fuse and a reference fuse; the first NMOS tube and the second NMOS tube; wherein one end of the reference fuse is SAref ports of the efuse unit structure; the other end of the reference fuse is connected with the drain electrode of the second NMOS tube; one end of the programming fuse is a bit line port of the efuse unit structure; the other end of the programming fuse is connected with the drain electrode of the first NMOS tube; the grid electrodes of the first NMOS tube and the second NMOS tube are connected with each other to form a word line port of the efuse unit structure; and the sources of the first NMOS tube and the second NMOS tube are connected with each other to form a grounding port of the efuse unit structure.
The invention also provides a double-row structure of the efuse unit, which at least comprises:
N efuse cell structures; the efuse cell structure includes: a fuse pair consisting of a programming fuse and a reference fuse; the first NMOS tube and the second NMOS tube; wherein one end of the reference fuse is SAref ports of the efuse unit structure; the other end of the reference fuse is connected with the drain electrode of the second NMOS tube; one end of the programming fuse is a bit line port of the efuse unit structure; the other end of the programming fuse is connected with the drain electrode of the first NMOS tube; the grid electrodes of the first NMOS tube and the second NMOS tube are connected with each other to form a word line port of the efuse unit structure; the sources of the first NMOS tube and the second NMOS tube are connected with each other to form a grounding port of the efuse unit structure;
A sense amplifier module SA; the sense amplifier module SA includes: the first differential input terminal BL, the second differential input terminal Ref and the logic output terminal;
The N efuse unit structures are sequentially arranged into first to N efuse unit structures; the bit line ports of the first to nth efuse unit structures are connected with each other and connected to a first differential input terminal BL of the sense amplifier module SA; the SAref ports of the first through N-th efuse cell structures are connected to each other and to a second differential input Ref of the sense amplifier module SA.
The invention also provides an application circuit of the efuse unit structure, which at least comprises:
An efuse cell structure; the efuse cell structure includes: a fuse pair consisting of a programming fuse and a reference fuse; the first NMOS tube and the second NMOS tube; wherein one end of the reference fuse is SAref ports of the efuse unit structure; the other end of the reference fuse is connected with the drain electrode of the second NMOS tube; one end of the programming fuse is a bit line port of the efuse unit structure; the other end of the programming fuse is connected with the drain electrode of the first NMOS tube; the grid electrodes of the first NMOS tube and the second NMOS tube are connected with each other to form a word line port of the efuse unit structure; the sources of the first NMOS tube and the second NMOS tube are connected with each other to form a grounding port of the efuse unit structure;
A sense amplifier module SA; the sense amplifier module SA includes: the first differential input terminal BL, the second differential input terminal Ref, the logic output terminal and the power supply terminal VDD;
a PMOS programming control tube;
the bit line port of the efuse unit structure is connected with the first differential input end BL of the sensitive amplifier module SA and the drain electrode of the PMOS programming control tube; the SAref port of the efuse unit structure is connected to the second differential input Ref of the sense amplifier module SA.
Preferably, the source of the PMOS programming control tube is connected to the voltage VDD1.
Preferably, the gate of the PMOS programming control tube is connected to a control signal Prog.
As described above, the efuse cell structure of the present invention has the following beneficial effects: the efuse unit structure of the invention reduces the requirement on the required programming current due to adopting non-fusing programming operation on the fuse, thus being capable of working under lower programming voltage and greatly reducing the power consumption of the system. Meanwhile, as the efuse unit structure adopts a fuse pair mode, the tiny difference between the programming fuse and the reference fuse can be reliably compared, and the programming current required by adopting a non-fusing mechanism is smaller, so that the fuse and the control tube of the efuse unit can be made smaller, and the whole area of the efuse is reduced.
Drawings
FIG. 1 shows a schematic circuit diagram of a conventional efuse structure;
FIG. 2 is a schematic diagram of an efuse cell structure of the present invention;
FIG. 3 shows a circuit schematic of a double row structure of an efuse cell of the present invention;
Fig. 4 shows a schematic diagram of an application circuit of the efuse cell structure of the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1 to 4. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
The invention provides an efuse unit structure, which at least comprises:
a fuse pair consisting of a programming fuse and a reference fuse; the first NMOS tube and the second NMOS tube; wherein one end of the reference fuse is SAref ports of the efuse unit structure; the other end of the reference fuse is connected with the drain electrode of the second NMOS tube; one end of the programming fuse is a bit line port of the efuse unit structure; the other end of the programming fuse is connected with the drain electrode of the first NMOS tube; the grid electrodes of the first NMOS tube and the second NMOS tube are connected with each other to form a word line port of the efuse unit structure; and the sources of the first NMOS tube and the second NMOS tube are connected with each other to form a grounding port of the efuse unit structure.
As shown in fig. 2, fig. 2 is a schematic diagram of an efuse cell structure of the present invention; the efuse unit structure of the embodiment is a fuse pair consisting of a programming fuse (Link 1) and a reference fuse (Link 2); the first NMOS tube N1 and the second NMOS tube N2; one end of the reference fuse Link2 is SAref ports (reference resistor output ends) of the efuse unit structure; the other end of the reference fuse Link2 is connected with the drain electrode of the second NMOS tube N2; one end of the programming fuse Link1 is a bit line port BL of the efuse unit structure; the other end of the programming fuse Link1 is connected with the drain electrode of the first NMOS tube N1; the grid electrodes of the first NMOS tube and the second NMOS tube are connected with each other to form a word line port WL of the efuse unit structure; the sources of the first NMOS tube and the second NMOS tube are connected with each other to form a ground port GND of the efuse unit structure.
The efuse cell structure of the present invention employs a new programming mechanism, namely, a non-blowing mode of programming operation for the fuse. This mechanism requires control over the process of electromigration of the fuse such that the resistance of the fuse changes rather than causing the fuse to blow. Because electromigration occurs under different current and time phases, the resistance value of the fuse wire can change in a larger range, and the efuse unit structure of the invention uses a fuse wire which does not undergo electromigration as a comparison reference object, and the difference of the resistance values between the programmed fuse wire and the reference fuse wire is directly compared through a differential structure in the sensitive amplifier module SA, so that the correct logic output value is obtained through conversion.
The invention also provides a double-row structure of the efuse unit, which at least comprises:
N efuse cell structures; the efuse cell structure includes: a fuse pair consisting of a programming fuse and a reference fuse; the first NMOS tube and the second NMOS tube; wherein one end of the reference fuse is SAref ports of the efuse unit structure; the other end of the reference fuse is connected with the drain electrode of the second NMOS tube; one end of the programming fuse is a bit line port of the efuse unit structure; the other end of the programming fuse is connected with the drain electrode of the first NMOS tube; the grid electrodes of the first NMOS tube and the second NMOS tube are connected with each other to form a word line port of the efuse unit structure; the sources of the first NMOS tube and the second NMOS tube are connected with each other to form a grounding port of the efuse unit structure;
A sense amplifier module SA; the sense amplifier module SA includes: the first differential input terminal BL, the second differential input terminal Ref and the logic output terminal;
The N efuse unit structures are sequentially arranged into first to N efuse unit structures; the bit line ports of the first to nth efuse unit structures are connected with each other and connected to a first differential input terminal BL of the sense amplifier module SA; the SAref ports of the first through N-th efuse cell structures are connected to each other and to a second differential input Ref of the sense amplifier module SA.
As shown in fig. 3, fig. 3 shows a circuit schematic of a double-row structure of an efuse cell of the present invention, which in this embodiment includes: n efuse cell structures; wherein each of said efuse cell structures comprises: a fuse pair consisting of a programming fuse and a reference fuse; the first NMOS tube and the second NMOS tube; wherein one end of the reference fuse is SAref ports of the efuse unit structure; the other end of the reference fuse is connected with the drain electrode of the second NMOS tube; one end of the programming fuse is a bit line port of the efuse unit structure; the other end of the programming fuse is connected with the drain electrode of the first NMOS tube; the grid electrodes of the first NMOS tube and the second NMOS tube are connected with each other to form a word line port of the efuse unit structure; the sources of the first NMOS tube and the second NMOS tube are connected with each other to form a grounding port of the efuse unit structure;
A sense amplifier module SA; the sense amplifier module SA includes: the first differential input terminal BL, the second differential input terminal Ref and the logic output terminal DO;
the N efuse unit structures are sequentially arranged into first to N efuse unit structures; the bit line ports BL of the first to N-th efuse cell structures are connected to each other and connected to a first differential input BL of the sense amplifier module SA; the SAref ports of the first through N-th efuse cell structures are connected to each other and to a second differential input Ref of the sense amplifier module SA.
The word line ports corresponding to the first to N efuse unit structures are first to N word line ports WL1 to WLn;
The invention adopts a non-fusing mechanism to perform programming operation, and though the resistance change of a fuse wire which generates electromigration is smaller, the small change of the resistance value of the fuse wire is converted into logic change through SA by arranging a fuse wire pair of a programming fuse wire and a reference fuse wire in an efuse unit and utilizing the deviation of the resistance values of the programming fuse wire and the reference fuse wire. As shown in fig. 3, the reference array and the memory array formed by the fuse pairs in the cells on the same column have the same physical characteristics and change states because the same structure and the same region are co-located, and thus the effects of process variations can be offset from each other.
The invention also provides an application circuit of the efuse unit structure, as shown in fig. 4, fig. 4 shows a schematic diagram of the application circuit of the efuse unit structure of the invention, at least including:
An efuse cell structure; the efuse cell structure includes: a fuse pair consisting of a programming fuse and a reference fuse; the first NMOS tube and the second NMOS tube; wherein one end of the reference fuse is SAref ports of the efuse unit structure; the other end of the reference fuse is connected with the drain electrode of the second NMOS tube; one end of the programming fuse is a bit line port of the efuse unit structure; the other end of the programming fuse is connected with the drain electrode of the first NMOS tube; the grid electrodes of the first NMOS tube and the second NMOS tube are connected with each other to form a word line port of the efuse unit structure; the sources of the first NMOS tube and the second NMOS tube are connected with each other to form a grounding port of the efuse unit structure;
The application circuit of the efuse unit structure further comprises: a sense amplifier module SA; the sense amplifier module SA includes: the first differential input terminal BL, the second differential input terminal Ref, the logic output terminal and the power supply terminal VDD;
The application circuit of the efuse unit structure further comprises: PMOS programming control tube P1;
the bit line port BL of the efuse unit structure is connected with the first differential input end BL of the sensitive amplifier module SA and the drain electrode of the PMOS programming control tube P1; the SAref port of the efuse unit structure is connected to the second differential input Ref of the sense amplifier module SA.
The source of the PMOS programming control tube of the present embodiment is further connected to the voltage VDD1. Still further, the gate of the PMOS programming control tube of the present embodiment is connected to the control signal Prog. The efuse structure of the present invention shown in FIG. 4 switches SAref of the reference fuses in the fuse pair in the efuse cell to SA, ensuring that an accurate comparison reference is provided for the programmed fuse resistance on BL during a read operation.
Because the efuse adopts non-fusing programming operation to the fuse, the invention reduces the requirement to the required programming current, thus the efuse can work under lower programming voltage and greatly reduces the power consumption of the system. Meanwhile, as the efuse unit adopts a fuse pair mode, the tiny difference between the programming fuse and the reference fuse can be reliably compared, and the programming current required by adopting a non-fusing mechanism is smaller, so that the fuse and a control tube of the efuse unit can be made smaller, and the whole area of the efuse is reduced.
The basic application structure of the efuse cell of the present invention is shown in FIG. 4. It can be seen that the WL signal on the WL port of the efuse cell controls the gate ends of the N1 and N2 tubes as in the conventional efuse of FIG. 1. The BL terminal of the efuse unit is connected to the SA module and the drain terminal of the PMOS programming control tube P1 respectively. In a programming operation, the Prog signal controls the programming current from VDD1, P1 pipe, programming fuse and N1 to ground. The reference current of the SA module is passed through the reference fuse and the N2 pipe to the ground, which provides an accurate comparison reference for the programmed fuse resistance on BL during read operation, and outputs the comparison result from DO of the SA module. In contrast, conventional efuses do not rely on an external reference fuse to make a comparison resistor, but rather utilize a reference resistor internal to the SA module.
In summary, the efuse unit structure, the double-row structure of the efuse unit and the application circuit of the efuse unit structure of the invention reduce the requirement on the required programming current due to the non-fusing programming operation on the fuse, thus the invention can work under lower programming voltage and greatly reduce the power consumption of the system. Meanwhile, as the efuse unit structure adopts a fuse pair mode, the tiny difference between the programming fuse and the reference fuse can be reliably compared, and the programming current required by adopting a non-fusing mechanism is smaller, so that the fuse and the control tube of the efuse unit can be made smaller, and the whole area of the efuse is reduced. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (5)
1. An efuse cell structure comprising at least:
A fuse pair consisting of a programming fuse and a reference fuse; the first NMOS tube and the second NMOS tube; wherein one end of the reference fuse is SAref ports of the efuse unit structure; the other end of the reference fuse is connected with the drain electrode of the second NMOS tube; one end of the programming fuse is a bit line port of the efuse unit structure; the other end of the programming fuse is connected with the drain electrode of the first NMOS tube; the grid electrodes of the first NMOS tube and the second NMOS tube are connected with each other to form a word line port of the efuse unit structure; and the sources of the first NMOS tube and the second NMOS tube are connected with each other to form a grounding port of the efuse unit structure.
2. A double-row structure of an efuse cell comprising at least:
N efuse cell structures; the efuse cell structure includes: a fuse pair consisting of a programming fuse and a reference fuse; the first NMOS tube and the second NMOS tube; wherein one end of the reference fuse is SAref ports of the efuse unit structure; the other end of the reference fuse is connected with the drain electrode of the second NMOS tube; one end of the programming fuse is a bit line port of the efuse unit structure; the other end of the programming fuse is connected with the drain electrode of the first NMOS tube; the grid electrodes of the first NMOS tube and the second NMOS tube are connected with each other to form a word line port of the efuse unit structure; the sources of the first NMOS tube and the second NMOS tube are connected with each other to form a grounding port of the efuse unit structure;
A sense amplifier module SA; the sense amplifier module SA includes: the first differential input terminal BL, the second differential input terminal Ref and the logic output terminal;
The N efuse unit structures are sequentially arranged into first to N efuse unit structures; the bit line ports of the first to nth efuse unit structures are connected with each other and connected to a first differential input terminal BL of the sense amplifier module SA; the SAref ports of the first through N-th efuse cell structures are connected to each other and to a second differential input Ref of the sense amplifier module SA.
3. An application circuit of an efuse cell structure, comprising at least:
An efuse cell structure; the efuse cell structure includes: a fuse pair consisting of a programming fuse and a reference fuse; the first NMOS tube and the second NMOS tube; wherein one end of the reference fuse is SAref ports of the efuse unit structure; the other end of the reference fuse is connected with the drain electrode of the second NMOS tube; one end of the programming fuse is a bit line port of the efuse unit structure; the other end of the programming fuse is connected with the drain electrode of the first NMOS tube; the grid electrodes of the first NMOS tube and the second NMOS tube are connected with each other to form a word line port of the efuse unit structure; the sources of the first NMOS tube and the second NMOS tube are connected with each other to form a grounding port of the efuse unit structure;
A sense amplifier module SA; the sense amplifier module SA includes: the first differential input terminal BL, the second differential input terminal Ref, the logic output terminal and the power supply terminal VDD;
a PMOS programming control tube;
The bit line port of the efuse unit structure is connected with the first differential input end BL of the sensitive amplifier module SA and the drain electrode of the PMOS programming control tube; the SAref port of the efuse unit structure is connected to the second differential input Ref of the sense amplifier module SA.
4. An application circuit for an efuse cell structure in accordance with claim 3, wherein: the source of the PMOS programming control tube is connected with the voltage VDD1.
5. The application circuit of the efuse cell structure of claim 4, wherein: the grid electrode of the PMOS programming control tube is connected with a control signal Prog.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011562191.2A CN112992245B (en) | 2020-12-25 | Efuse cell structure, double-row structure of efuse cell and application circuit of efuse cell structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011562191.2A CN112992245B (en) | 2020-12-25 | Efuse cell structure, double-row structure of efuse cell and application circuit of efuse cell structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112992245A CN112992245A (en) | 2021-06-18 |
| CN112992245B true CN112992245B (en) | 2024-11-19 |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101253573A (en) * | 2005-08-31 | 2008-08-27 | 国际商业机器公司 | Random access electrically programmable-E-FUSE ROM |
| CN103745750A (en) * | 2013-12-25 | 2014-04-23 | 苏州宽温电子科技有限公司 | Improved difference framework OTP (one time programmable) storage unit based on fuse characteristic |
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101253573A (en) * | 2005-08-31 | 2008-08-27 | 国际商业机器公司 | Random access electrically programmable-E-FUSE ROM |
| CN103745750A (en) * | 2013-12-25 | 2014-04-23 | 苏州宽温电子科技有限公司 | Improved difference framework OTP (one time programmable) storage unit based on fuse characteristic |
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