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CN112953242B - Instantaneous overpower control method and circuit - Google Patents

Instantaneous overpower control method and circuit Download PDF

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Publication number
CN112953242B
CN112953242B CN202110319420.6A CN202110319420A CN112953242B CN 112953242 B CN112953242 B CN 112953242B CN 202110319420 A CN202110319420 A CN 202110319420A CN 112953242 B CN112953242 B CN 112953242B
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output
pem
signal
voltage
controller
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CN112953242A (en
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赵志伟
曾正球
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Shenzhen Nanyun Microelectronics Co ltd
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Shenzhen Nanyun Microelectronics Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
    • H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
    • H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
    • H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
    • H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/04—Measuring peak values or amplitude or envelope of ac or of pulses

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention provides an instantaneous overpower control method and a circuit, when a CS pin of a controller detects that a source voltage when a power tube is conducted is larger than a maximum peak current limiting threshold value in a normal mode in the controller within a plurality of continuous periods, the controller is judged to be in an instantaneous overpower state at the moment, so that the peak current of the CS pin of the controller is raised, the working frequency of the controller is improved, the controller works in an overpower working mode, and in the maintenance time of the instantaneous overpower state, if the output state is recovered to be normal or the timing of the maintenance time is finished, the instantaneous overpower state can be quitted under the two conditions, so that the controller is recovered to the normal working mode. The invention can distinguish the normal large dynamic state from the instantaneous overpower state, namely the normal large dynamic state can not be triggered by mistake to enter the instantaneous overpower state, so as to avoid the increase of the switching loss caused by overhigh working frequency and the influence on the working efficiency of the system.

Description

Instantaneous overpower control method and circuit
Technical Field
The invention relates to the technical field of power semiconductors, in particular to an instantaneous overpower control method and an instantaneous overpower control circuit, which are suitable for a power management integrated circuit system in a power converter, and particularly suitable for the power management integrated circuit system in a flyback isolation converter.
Background
Currently, flyback converters (Flyback converters) have been widely used as power conversion devices for various electronic products because of their advantages of high efficiency, low power consumption, small size and light weight.
Flyback converters are frequently used in a variety of portable devices (e.g., mobile phones, digital cameras, tablet computers, digital music players, media players, portable hard drives, handheld game consoles, and other handheld consumer electronic devices) that are powered from a limited internal battery, such as a lithium battery. Therefore, flyback converters are commonly used to provide voltage regulation functionality.
As technology advances, portable devices become more functional, requiring more power from the power converter. In some applications there may be a demand for higher current for a short period (short-term transient overpower boost demand). The application may be a printer, a motor, or for CPU power boost functions. The instantaneous overpower can be 2 times or even 3 to 4 times of the maximum power required for normal operation. Known converters cannot deliver large amounts of instantaneous overpower at no cost (e.g., using larger transformers to avoid magnetic saturation conditions).
It is therefore desirable to provide a technique for maintaining normal operation of a module during transient overpower, avoiding saturation of the magnetic core, and minimizing the increase in size and cost of the module to meet the transient overpower conditions.
Disclosure of Invention
In view of the defects and limitations of the prior art, the technical problem to be solved by the present invention is to provide an instantaneous overpower control method and circuit, wherein the peak current when the primary side power tube is turned on is detected to judge that the converter is in overpower, so as to improve the working frequency of the controller, raise the threshold of the peak current, improve the loading capacity of the converter, and keep the output voltage stable; meanwhile, the invention designs that the maintaining time for entering the instantaneous overpower state is programmable, thereby meeting the requirements of different applications on the instantaneous overpower; the invention simultaneously detects the maximum peak current threshold and the output feedback voltage, and distinguishes the output normal dynamic load from the instantaneous overpower state, thereby avoiding the phenomenon that the output large dynamic load is mistakenly in the instantaneous overpower state when jumping, and influencing the working efficiency of the system.
In order to solve the technical problem, the technical scheme of the instantaneous overpower control method provided by the invention is as follows:
a transient overpower control method is applied to a power converter, the power converter comprises a power tube and a controller, and the control method is characterized by comprising the following steps:
a peak current sampling step, namely detecting through a CS pin of a controller to generate a voltage signal VCS changing along with the source voltage when a power tube is conducted;
a PWM input gain and output state judgment step, namely detecting through an FB pin of a controller to generate a voltage signal VFB _ PFM, a voltage signal VFB _ PEM and a voltage signal VFB _ PWM which change along with the output voltage of the power converter, and an output state signal Vout _ ok _ H reflecting the over-power condition output by the power converter;
the peak current sampling step is to select to compare the obtained voltage signal VCS with a voltage signal VFB _ PEM or a voltage signal VFB _ PWM to generate a duty ratio control signal PWM _ L; and also selectively comparing the obtained voltage signal VCS with a first threshold Vref _ Lim1 or a second threshold Vref _ Lim2 to generate a maximum duty ratio control signal PWM _ Lim _ L;
an instantaneous overpower judging step, namely generating an instantaneous overpower state signal PEM _ EN _ L according to the maximum duty ratio control signal PWM _ Lim _ L;
a maintaining time programmable step, generating the maintaining time of the overpower state according to the instantaneous overpower state signal PEM _ EN _ L; generating an exit instantaneous overpower state signal PEM _ out _ ok _ L according to the instantaneous overpower state signal PEM _ EN _ L and the output state signal Vout _ ok _ H;
a frequency and duty ratio control step, wherein a driving signal GATE, a low-voltage driving signal Drive _ H inside a controller and a current signal IFB _ PEM changing with the output voltage of a power converter are generated according to an instantaneous overpower state signal PEM _ EN _ L, a maximum duty ratio control signal PWM _ Lim _ L, a duty ratio control signal PWM _ L and a voltage signal VFB _ PFM; meanwhile, a first working frequency of the controller working in a normal working mode or a second working frequency of the controller working in an instantaneous overpower mode is selected according to an instantaneous overpower state signal PEM _ EN _ L and a voltage signal VFB _ PFM;
the Vref _ Lim1 is less than Vref _ Lim2, the first working frequency is less than the second working frequency, and the second working frequency changes along with the change of the voltage signal VFB _ PFM;
each step also comprises the following steps of realizing the switching of the working mode of the controller according to the following control logic;
when the VCS is less than or equal to Vref _ Lim1 or the VCS is more than the Vref _ Lim1 but the lasting time is less than N periods, the maximum duty ratio control signal PWM _ Lim _ L and the instantaneous overpower state signal PEM _ EN _ L are both high level, the controller works in a normal working mode, the selection voltage signal VCS is compared with a first threshold Vref _ Lim1, and the controller works at a first working frequency;
when the duration time of VCS & gt Vref _ Lim1 is more than or equal to N periods, the maximum duty ratio control signal PWM _ Lim _ L and the instantaneous overpower state signal PEM _ EN _ L are both low levels, the controller works in an overpower working mode, the voltage selection signal VCS is compared with a second threshold Vref _ Lim2, and the controller works at a second working frequency;
when the instantaneous overpower state signal PEM _ EN _ L is at a low level, if the output state of the power converter is recovered to be normal, the output state signal Vout _ ok _ H is at a high level; when the maintaining time is over or the output state signal Vout _ ok _ H is at a high level, the exiting instantaneous overpower state signal PEM _ out _ ok _ L is at a low level, and the controller is recovered to a normal working mode;
wherein N is a positive integer of a given value.
Further, the higher the overpower multiple output by the power converter, the higher the second operating frequency.
Further, the duration is set by the PEM pin of the controller, and the higher the overpower multiple output by the power converter, the shorter the duration.
Correspondingly, the technical scheme of the instantaneous overpower control circuit provided by the invention is as follows:
a transient overpower control circuit for a power converter, the power converter comprising a power transistor and a controller, the transient overpower control circuit comprising: the device comprises a peak current sampling unit, an instantaneous overpower judging unit, a maintaining time programmable unit, a PWM input gain and output state judging unit and a frequency and duty ratio control unit;
the peak current sampling unit is used for generating a voltage signal VCS changing along with the source voltage when the power tube is conducted through the detection of a CS pin of the controller;
the PWM input gain and output state judgment unit is used for generating a voltage signal VFB _ PFM, a voltage signal VFB _ PEM and a voltage signal VFB _ PWM which change along with the output voltage of the power converter and an output state signal Vout _ ok _ H reflecting the over-power condition output by the power converter through the detection of an FB pin of the controller;
the peak current sampling unit also selectively compares the obtained voltage signal VCS with a voltage signal VFB _ PEM or a voltage signal VFB _ PWM to generate a duty ratio control signal PWM _ L; and also selectively comparing the obtained voltage signal VCS with a first threshold value Vref _ Lim1 or a second threshold value Vref _ Lim2 to generate a maximum duty ratio control signal PWM _ Lim _ L;
the instantaneous overpower judging unit generates an instantaneous overpower state signal PEM _ EN _ L according to the maximum duty ratio control signal PWM _ Lim _ L;
the maintaining time programmable unit generates maintaining time of the overpower state according to the instantaneous overpower state signal PEM _ EN _ L; generating an exit instantaneous overpower state signal PEM _ out _ ok _ L according to the instantaneous overpower state signal PEM _ EN _ L and the output state signal Vout _ ok _ H;
the frequency and duty ratio control unit generates a driving signal GATE, a low-voltage driving signal Drive _ H in the controller and a current signal IFB _ PEM changing along with the output voltage of the power converter according to an instantaneous overpower state signal PEM _ EN _ L, a maximum duty ratio control signal PWM _ Lim _ L, a duty ratio control signal PWM _ L and a voltage signal VFB _ PFM; meanwhile, a first working frequency of the controller working in a normal working mode or a second working frequency of the controller working in an instantaneous overpower mode is selected according to an instantaneous overpower state signal PEM _ EN _ L and a voltage signal VFB _ PFM;
the Vref _ Lim1 is less than Vref _ Lim2, the first working frequency is less than the second working frequency, and the second working frequency changes along with the change of the voltage signal VFB _ PFM;
each circuit unit also realizes the switching of the working mode of the controller according to the following control logic;
when VCS is less than or equal to Vref _ Lim1 or the VCS is more than Vref _ Lim1 but the lasting time is less than N periods, the maximum duty ratio control signal PWM _ Lim _ L and the instantaneous overpower state signal PEM _ EN _ L are both high level, the controller works in a normal working mode, the peak current sampling unit selection voltage signal VCS is compared with a first threshold Vref _ Lim1, and the frequency and duty ratio control unit selects the controller to work at a first working frequency;
when the duration time of VCS & gt Vref _ Lim1 is more than or equal to N periods, the maximum duty ratio control signal PWM _ Lim _ L and the instantaneous overpower state signal PEM _ EN _ L are both low levels, the controller works in an overpower working mode, the peak current sampling unit selects the voltage signal VCS to be compared with a second threshold value Vref _ Lim2, and the frequency and duty ratio control unit selects the controller to work at a second working frequency;
when the instantaneous overpower state signal PEM _ EN _ L is at a low level, if the output state of the power converter is recovered to be normal, the output state signal Vout _ ok _ H is at a high level, when the maintaining time is over or the output state signal Vout _ ok _ H is at a high level, the instantaneous overpower state signal PEM _ out _ ok _ L is exited to be at a low level, and then the controller is recovered to be in a normal working mode;
wherein N is a set positive integer.
Further, the higher the overpower multiple output by the power converter, the higher the second operating frequency.
Further, the duration is set by the PEM pin of the controller, and the higher the overpower multiple output by the power converter, the shorter the duration.
A specific embodiment of the peak current sampling unit is characterized by comprising: an alternative data selector MUX1, an alternative data selector MUX2, a comparator CMP1, a comparator CMP2; the negative phase input end of the comparator CMP1 is used for connecting a CS pin of the controller and is connected with the negative phase input end of the comparator CMP2, the positive phase input end of the comparator CMP1 is connected with the output end of the alternative data selector MUX1, and the output end of the comparator CMP1 outputs a duty ratio control signal PWM _ L; a voltage signal VFB _ PWM is input to a first input end of the alternative data selector MUX1, a voltage signal VFB _ PEM is input to a second input end of the alternative data selector MUX1, and an instantaneous overpower state signal PEM _ EN _ L is input to a third input end of the alternative data selector MUX2 after the third input end of the alternative data selector is connected with the third input end of the alternative data selector MUX 2; a first threshold value Vref _ Lim1 is input to a first input end of the alternative data selector MUX2, a second threshold value Vref _ Lim2 is input to a second input end, and an output end of the alternative data selector MUX2 is connected with a positive phase input end of a comparator CMP2; the output terminal of the comparator CMP2 outputs the maximum duty ratio control signal PWM _ Lim _ L.
As a specific implementation manner of the alternative data selector MUX1, the alternative data selector MUX1 includes: the NMOS transistor NM1, the NMOS transistor NM2 and the NOT, wherein the drain electrode of the NMOS transistor NM1 is used as a first input end of the alternative data selector MUX1, the source electrode of the NMOS transistor NM1 is connected with the source electrode of the NMOS transistor NM2, and the junction of the connection is used as the output end of the alternative data selector MUX 1; the input ends of the grid NAND gates not of the NMOS tube NM1 are connected, and the junction of the connection is used as a third input end of the alternative data selector MUX 1; the output end of the NOT is connected with the grid electrode of the NMOS tube NM2, and the drain electrode of the NMOS tube NM2 is used as the second input end of the alternative data selector MUX 1.
Another specific implementation of the alternative data selector MUX1 is characterized by comprising: the input end of the transmission gate Transgate1 is used as the first input end of the alternative data selector, the output end of the transmission gate Transgate1 is connected with the output end of the transmission gate Transgate2, and the connection intersection is used as the output end of the alternative data selector MUX 1; the input ends of the positive control ends and the non-gate of the transmission gate Transgate1 are connected, and the junction of the connection is used as a third input end of the alternative data selector MUX 1; the output end of the not gate not is connected with the forward control end of the transmission gate Transgate2, and the input end of the transmission gate Transgate2 is used as the second input end of the either-or data selector MUX 1.
One specific implementation way of the instant overpower judgment unit is characterized by comprising the following steps: a judgment delay unit, an RS latch and a NOT _1; the judging delay unit generates a judging signal PEM _ IN _ H entering an instantaneous overpower state according to a maximum duty ratio control signal PWM _ Lim _ L input by a first input end, a low-voltage driving signal Drive _ H input by a second input end and a driving signal GATE input by a third input end, the judging signal PEM _ IN _ H is output to an S end of the RS latch, an R end of the RS latch inputs and exits the instantaneous overpower state signal PEM _ out _ ok _ L, an output end Q of the RS latch is connected with an input end of a NAND GATE _1, and an output end of a NOT _1 outputs an instantaneous overpower state signal PEM _ EN _ L.
As a specific implementation manner of the aforementioned unit for determining a delay time, the unit is characterized by including: the circuit comprises an RS latch RS1, an RS latch RS2, a D trigger DFF, a NOT1, a NOT2, a NOT3, an AND gate and, a leading edge blanking LEB and a counter; the output end Q of the D flip-flop DFF is simultaneously connected with the output end of the AND GATE and the R end of the RS latch RS2, the first input end of the AND GATE and the second input end of the counter are connected, the input end of the NOT2 is connected with the output end of the leading edge blanking LEB, the input end of the leading edge blanking LEB inputs the driving signal GATE, the third input end of the D flip-flop DFF Clr _ L is used for inputting the low-voltage initialization signal ENP _ lv inside the controller, the output end Q of the D flip-flop DFF is connected with the second input end of the counter and the R end of the RS latch RS2, the first input end of the GATE and the second input end of the GATE are used for inputting the instantaneous over-power state signal ClL, the output end of the GATE and the counter is connected with the second input end of the counter, the output end of the counter is connected with the output end of the NOT3 of the NOT GATE and the output end of the counter, the output end of the NOT2 of the counter is connected with the output end of the NOT2, and the output end of the NOT2 is connected with the output end of the NOT2 of the counter.
One specific embodiment of the hold time programmable unit is characterized by comprising: current source IB 1 A current source IB 2 The circuit comprises a capacitor C1, an NMOS tube NM1_1, a comparator CMP, a NAND gate nand, a latch LATH, a D trigger DFF1, a NOT4, a NOT5, a NOT6, a Delay and an AND gate and1;
current source IB 1 The input end of the voltage source is used for connecting a low-voltage power supply VCC, the output end of the voltage source is used for connecting a PEM pin of a controller, and the current source IB 1 The output terminal of the comparator is also connected with the positive phase input terminal of the comparator CMP; current source IB 2 The input terminal is used for connecting a low-voltage power supply VCC 、 The current signal IFB _ PEM and the current source IB are input into the output end 2 The output end of the comparator is also simultaneously connected with one end of the capacitor C1, the drain electrode of the NMOS tube NM1_1 and the inverting input end of the comparator CMP; the other end of the capacitor C1 is simultaneously connected with the source electrode of the NMOS tube NM1_1 and the ground of the controller; the grid of the NMOS tube NM1_1 is connected with the output end of the NAND gate nand, the first input end of the NAND gate nand is simultaneously connected with the output end of the latch LATH and the second input end CP of the D flip-flop DFF1, the second input end of the NAND gate nand is connected with the third input end Clr _ lv of the D flip-flop DFF1 for inputting the low voltage in the controllerInitializing a signal ENP _ lv; the input of the latch is connected to the output of the comparator CMP; a first input end D of the D trigger DFF1 is connected with a second output end Q of the D trigger, a first output end Q of the D trigger DFF1 is connected with an input end of a NAND gate not4, an output end of the NOT4 is connected with a first input end CP _ L of a counter1, a second input end Clr _ L of the counter1 is connected with an output end of a NAND gate not5, and an input end of the NOT5 inputs an instantaneous overpower state signal PEM _ EN _ L; the output end of the counter1 is connected with the input end of the NAND gate not6, the output end of the NOT6 is connected with the second input end of the AND gate and1, the first input end of the AND gate and1 is connected with the output end of the Delay, and the input end of the Delay inputs and outputs a state signal Vout _ ok _ H.
One of the PWM input gain and output state judging units comprises a PWM input gain, an alternative data selector MUX3, a comparator CMP3 and a NOT7; the first input end of the PWM input gain is used for being connected with an FB pin of the controller, the second input end of the PWM input gain is connected with the third input end of the alternative data selector MUX3 and then inputs an instantaneous overpower state signal PEM _ EN _ L, the first output end of the PWM input gain is connected with the positive input end of the comparator CMP3, and the second output end, the third output end and the fourth output end of the PWM input gain respectively output a voltage signal VFB _ PFM, a voltage signal VFB _ PEM and a voltage signal VFB _ PWM; a first input end of the alternative data selector MUX3 is used for connecting a first reference voltage signal Vref1 inside the input controller, a second input end of the alternative data selector MUX3 is used for connecting a second reference voltage signal Vref2 inside the input controller, an output end of the alternative data selector MUX3 is connected with a negative phase input end of the comparator CMP3, an output end of the comparator CMP3 is connected with an input end of the nand gate not7, and an output end of the not gate not7 outputs an output state signal Vout _ ok _ H.
As a specific embodiment of the PWM input gain, the PWM input gain control apparatus includes: the device comprises a switched capacitor Filter, an NMOS (N-channel metal oxide semiconductor) tube NM3, a resistor R1, a resistor R2, a resistor R3 and a resistor R4; the input end of the switched capacitor Filter is used for being connected with an FB pin of the controller, the first output end of the switched capacitor Filter is connected with the grid electrode of the NMOS tube NM3, and the second output end of the switched capacitor Filter outputs a voltage signal VFB _ PFM; the drain electrode of the NMOS tube NM3 is used for being connected with a low-voltage power supply VCC, the source electrode of the NMOS tube NM3 is connected with one end of a resistor R1, the other end of the resistor R1 is connected with one end of a resistor R2, and the connection intersection is connected with the positive phase input end of a comparator CMP 3; the other end of the resistor R2 is connected with one end of the resistor R3, and a voltage signal VFB _ PEM is output at the junction of the connection; the other end of the resistor R3 is connected with one end of the resistor R4, the voltage signal VFB _ PWM is output at the junction of the connection, and the other end of the resistor R4 is connected with the ground of the controller.
As a specific implementation manner of the frequency and duty ratio control unit, the method is characterized by comprising the following steps: the voltage-controlled oscillator VCO, the AND gate and2, the RS latch RS3 and the drive Driver; the first input end of the voltage-controlled oscillator VCO inputs an instantaneous overpower state signal PEM _ EN _ L, the second input end of the voltage-controlled oscillator VCO inputs a voltage signal VFB _ PFM, the first output end of the voltage-controlled oscillator VCO outputs a current signal IFB _ PEM, the second output end of the voltage-controlled oscillator VCO is connected with the S end of an RS latch RS3, the R end of the RS latch is connected with the output end of an AND GATE and2, the first input end of the AND GATE and2 inputs a duty ratio control signal PWM _ L, the second input end of the AND GATE and inputs a maximum duty ratio control signal PWM _ Lim _ L, the output end Q of the RS latch RS3 is connected with the input end of a Driver, the connection point outputs a low-voltage driving signal Driver _ H inside the controller, and the output end of the Driver outputs a driving signal GATE.
The brief working principle of the invention is as follows:
when a CS pin of the controller detects that the source voltage when the power tube is conducted is larger than the maximum peak current limiting threshold value in a normal mode in the controller within a plurality of continuous periods, the controller is judged to be in an instantaneous overpower state, and then a larger maximum peak current limiting threshold value is selected through an instantaneous overpower state signal to raise the peak current; meanwhile, the instantaneous overpower state signal controls the voltage-controlled oscillator to be switched to a higher working frequency, so that a GATE pin of the controller outputs the higher working frequency to meet the overpower requirement, further, the voltage and the current which are changed along with the FB voltage of the controller pin are generated through a PWM input gain part, and the voltage which is changed along with the FB voltage controls the voltage-controlled oscillator to generate the changed maximum working frequency so as to adapt to the requirements of different overpower multiples on the maximum working frequency; the current changing along with the FB voltage changes the maintaining time along with the magnitude of the overpower multiple under the control of the instantaneous overpower state signal, and meanwhile, different sampling resistors are externally connected through a PEM pin of the controller, so that different maintaining times are generated, and the requirements of different overpower states on the maintaining time are met. Further, in the maintenance time of the instantaneous overpower state, the output state is judged through the voltage of the FB pin of the controller, and if the output state is recovered to be normal or the timing of the maintenance time is ended, the instantaneous overpower state can be quitted under the two conditions, so that the controller is recovered to be in a normal working mode.
In order to avoid deviation or obstacle in understanding, the above technical solution is described as follows:
1. detecting a CS pin and generating a related signal in a peak current sampling step, and detecting an FB pin and generating a related signal in a PWM input gain and output state judging step, wherein the two steps are carried out simultaneously;
2. the first threshold value Vref _ Lim1, the second threshold value Vref _ Lim2, the first reference voltage signal Vref1, the second reference voltage signal Vref2 and the low voltage initialization signal ENP _ lv inside the controller are all preset according to the practical application requirement of the controller.
The specific principles of operation and related analyses of the present invention are described in detail in the detailed description section below. The beneficial effects of the present invention are summarized as follows:
1. the invention can distinguish the normal large dynamic state from the instantaneous overpower state, namely the normal large dynamic state can not be triggered by mistake to enter the instantaneous overpower state, so as to avoid the increase of the switching loss caused by overhigh working frequency and the influence on the working efficiency of the system.
2. The invention can lead the maximum working frequency of the controller to pass the loop self-adapting instantaneous overpower multiple state, namely the maximum working frequency of the controller working in the instantaneous overpower mode self-adapting instantaneous overpower multiple, and the higher the instantaneous overpower multiple is, the higher the maximum working frequency of the controller working is.
3. The invention can program the maintenance time of the over-power state and meet the requirements of different applications on instantaneous over-power.
4. The invention can self-adapt the instantaneous overpower multiple state through the loop circuit while programmable maintaining time, namely the higher the instantaneous overpower multiple is, the shorter the maintaining time is.
Drawings
Fig. 1 is a schematic diagram of an exemplary circuit for a flyback converter incorporating a controller 10 of the present invention with an instantaneous overpower control circuit 100;
FIG. 2 is a schematic block diagram of an embodiment of the transient overpower control circuit 100 of the present invention;
FIG. 3 is a schematic circuit diagram of an embodiment of a peak current sampling unit 101 according to the present invention;
FIG. 4 is a schematic circuit diagram of an embodiment of an alternative data selector MUX1011 in the peak current sampling unit 101 of FIG. 3;
FIG. 5 is a schematic circuit diagram of an embodiment of the instant overpower judgment unit 102 according to the present invention;
FIG. 6 is a schematic circuit diagram of an embodiment of the determining delay unit 1021 in the instantaneous overpower determining unit 102 in FIG. 5;
FIG. 7 is a schematic circuit diagram of an embodiment of the programmable time keeping unit 103 according to the present invention;
FIG. 8 is a schematic circuit diagram of an embodiment of the PWM input gain and output state determination unit 104 according to the present invention;
FIG. 9 is a schematic circuit diagram of an embodiment of the PWM input gain 1041 in the PWM input gain and output state determining unit 104 of FIG. 8;
FIG. 10 is a schematic circuit diagram of an embodiment of the frequency and duty cycle control unit 105 of the present invention;
fig. 11 is a schematic diagram of waveforms of signals related to a large dynamic load and an instantaneous over-power state of a flyback converter to which the instantaneous over-power control circuit 100 of the present invention is applied;
fig. 12 is a waveform diagram of simulation-related signals of a large dynamic load and an instantaneous overpower state system of a flyback converter to which the instantaneous overpower control circuit 100 of the present invention is applied;
fig. 13 is a schematic circuit diagram of another alternative embodiment of the alternative data selector MUX2011 in the peak current sampling unit 201 of fig. 3.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and do not limit the invention.
First embodiment
Fig. 1 is a schematic diagram of a typical circuit of a flyback converter including a controller 10 with an instantaneous overpower control circuit 100 according to the present invention. As shown in FIG. 1, the circuit comprises a controller 10, an optical coupler OP1, a coupling transformer T1, an input voltage VIN, a power tube M1, and a resistor R CS 、R PEM 、R1、R2、R3、R4、R O Capacitance C O C1, three-terminal regulator TL431 and diode D1.
The controller 10 includes the following pins, and the other pins are not related to the present invention and will not be described:
a CS pin: the current sampling input port is used for sampling the peak voltage of the source electrode at the moment when the power tube is switched on;
PEM pin: an instantaneous overpower time programmable pin for programming a hold time of an instantaneous overpower state;
FB Pin: the optical coupler feedback pin is used for feeding back an output voltage change signal of the power converter;
GATE pin: the control end is used for being connected to a power tube in the power converter and providing a driving signal for the power tube in the power converter;
GND pin: and the primary side ground is used for connecting the flyback converter.
In fig. 1, the FB pin of the controller 10 is connected to pin 3 of the optocoupler OP1, pin 4 of the optocoupler OP1 is connected to the original ground, and the PEM pin of the controller 10 is connected to the resistor R PEM Is connected to a resistor R PEM The other end of the first switch is connected with a GND pin of the controller and a primary side ground, a GATE pin of the controller is connected with a grid electrode of the power tube M1, and a CS pin of the controllerIs connected with the source electrode of the power tube M1 and is simultaneously connected with the sampling resistor R CS Is connected to a sampling resistor R CS The other end of the power tube M1 is connected with a primary side ground, the drain electrode of the power tube M1 is connected with the dotted terminal of the primary side coil of the coupling transformer T1, the synonym terminal of the primary side coil of the coupling transformer T1 is connected with the input voltage VIN, the dotted terminal of the secondary side coil of the coupling transformer T1 is connected with the anode of a diode D1, and the cathode of the diode D1 is simultaneously connected with an output filter capacitor C O One end of (2), an output load resistance R O One end of resistor R1, one end of resistor R2 and output voltage V O Is connected with the positive terminal of the coupling transformer T1, and the different name terminal of the secondary side coil of the coupling transformer T1 is simultaneously connected with the output capacitor C O Another terminal of (1), a resistor R O Another end of (b), an output voltage V O And the negative terminal-and the secondary side are connected; the other end of the resistor R1 is connected with a pin 1 of the optical coupler OP1, a pin 2 of the optical coupler OP1 is simultaneously connected with one end of the resistor R4 and the cathode of the three-terminal voltage regulator TL431, the other end of the resistor R4 is connected with one end of the capacitor C1, and the other end of the capacitor C1 is simultaneously connected with one end of the resistor R3, the other end of the resistor R2 and the reference input end of the three-terminal voltage regulator TL 431; the anode of three-terminal regulator TL431 and the other end of resistor R3 are connected to the secondary side ground.
Fig. 2 is a schematic block diagram of the transient overpower control circuit 100 of the present invention. The instantaneous overpower control circuit 100 of the present invention is integrated inside the controller 10 of fig. 1, and the controller 10 includes other circuits, such as a low-voltage power VCC generating circuit, a reference voltage generating circuit, and a low-voltage initialization signal generating circuit, in addition to the instantaneous overpower control circuit 100 of the present invention. In the invention, a low-voltage power supply VCC can be obtained by reducing the voltage of an input voltage VIN of a converter and is used for supplying power to each submodule in the controller 10, wherein the low-voltage power supply VCC =5V is selected in the embodiment of the invention; the reference voltage generating circuit can be obtained by a known band-gap reference circuit and is used for inputting a stable voltage reference signal to a module in the controller, and two reference voltage signals, namely a first reference voltage signal Vref1 and a second reference voltage signal Vref2, need to be generated; the low voltage initialization signal generating circuit can be obtained by delaying a known starting circuit, and the generated low voltage initialization signal ENP _ lv is usually established with a time delay after the internal power supply voltage of the controller is generated, and is used for initializing corresponding logic units in the controller, such as an RS latch, a D flip-flop, a counter and the like, and enabling the logic units to be at an effective potential before the logic functions.
The instantaneous overpower control circuit 100 of the present invention further includes many sub-circuits inside each unit circuit, such as the voltage controlled oscillator VCO, the switched capacitor Filter, the Driver, the counter, the Delay, the leading edge blanking LEB, and the bias current source IBIAS described in the following embodiments of each unit circuit.
As shown in fig. 2, the instantaneous overpower control circuit 100 of the present embodiment includes a peak current sampling unit 101, an instantaneous overpower judging unit 102, a hold time programmable unit 103, a PWM input gain and output state judging unit 104, and a frequency and duty ratio control unit 105.
The CS pin is connected to a first input terminal of the peak current sampling unit 101, and a first output terminal of the peak current sampling unit 101 outputs a maximum duty ratio control signal PWM _ Lim _ L to a first input terminal of the instantaneous overpower judgment unit 102 and a first input terminal of the frequency and duty ratio control unit 105; a second output terminal of the peak current sampling unit 101 outputs a duty ratio control signal PWM _ L to a second input terminal of the frequency and duty ratio control unit 105; the output end of the instantaneous overpower judgment unit 102 outputs an instantaneous overpower state signal PEM _ EN _ L to the first input end of the hold time programmable unit 103, the second input end of the peak current sampling unit 101, the first input end of the PWM input gain and output state judgment unit 104, and the third input end of the frequency and duty ratio control unit 105; a second input end of the maintenance time programmable unit 103 is connected with a PEM pin of the controller, a third input end of the maintenance time programmable unit 103 is connected with a first output end of the PWM input gain and output state judgment unit 104, and an output end of the maintenance time programmable unit 103 outputs a quit instantaneous overpower state signal PEM _ out _ ok _ L to a second input end of the instantaneous overpower judgment unit 102; the FB pin is connected to the second input terminal of the PWM input gain and output state determining unit 104, the second output terminal of the PWM input gain and output state determining unit 104 outputs the voltage signal VFB _ PFM varying with the output voltage of the power converter to the fourth input terminal of the frequency and duty ratio control unit 105, the third output terminal of the PWM input gain and output state determining unit 104 outputs the voltage signal VFB _ PEM varying with the output voltage of the power converter to the third input terminal of the peak current sampling unit 101, and the fourth output terminal of the PWM input gain and output state determining unit 104 outputs the voltage signal VFB _ PWM varying with the output voltage of the power converter to the fourth input terminal of the peak current sampling unit 101; a GATE pin of the controller is connected to a first output terminal of the frequency and duty cycle control unit 105, the first output terminal of the frequency and duty cycle control unit 105 outputs a driving signal GATE, a second output terminal of the frequency and duty cycle control unit 105 outputs a low voltage driving _ H signal inside the controller to a third input terminal of the instantaneous overpower judgment unit 102, and the third output terminal of the frequency and duty cycle control unit 105 outputs a current signal IFB _ PEM varying with the output voltage of the power converter to a fourth input terminal of the hold time programmable unit 103.
The present invention relates to a large number of signals, and the following signals are collectively described:
voltage signal VCS: a voltage signal which changes with the source voltage when the power tube is conducted;
voltage signal VFB _ PFM: the voltage signal which changes along with the output voltage of the power converter is used for controlling the working frequency of the controller to change;
voltage signal VFB _ PEM: the voltage signal which changes along with the output voltage of the power converter is used for controlling the change of the duty ratio of the output driving signal of the controller in the instantaneous overpower mode;
voltage signal VFB _ PWM: the voltage signal which changes along with the output voltage of the power converter is used for controlling the change of the duty ratio of the output driving signal of the controller in the normal working mode;
output status signal Vout _ ok _ H: a voltage signal reflecting an over-power condition output by the power converter;
duty control signal PWM _ L: is used for representing the duty ratio condition of the controller in the normal operation mode;
maximum duty control signal PWM _ Lim _ L: for indicating the duty cycle condition of the controller in the transient over-power condition;
first threshold value Vref _ Lim1: the maximum peak current of the controller in the normal operation mode defines a threshold value;
second threshold value Vref _ Lim2: the maximum peak current of the controller in the over-power operating mode defines a threshold;
instantaneous overpower state signal PEM _ EN _ L: for indicating that the controller is operating in a transient over-power state;
exit instantaneous overpower state signal PEM _ out _ ok _ L: for indicating that the controller has exited the transient overpower state;
drive signal GATE: controlling the signal of switching on and switching off a power tube in the power converter;
low voltage driving signal Drive _ H inside the controller: a driving module in the controller generates the driving signal GATE according to the signal;
current signal IFB _ PEM: a current signal that varies with the output voltage of the power converter.
The operation of the transient overpower control circuit 100 is described as follows with reference to fig. 1 and 2:
sampling resistor R when peak current sampling unit 101 detects that power tube M1 is conducted through CS pin CS If the voltage is greater than the maximum peak current limiting threshold value in the normal working mode in the controller, the maximum duty ratio control signal PWM _ Lim _ L is output to be at a low level and is sent to the instantaneous overpower judgment unit 102, and if the maximum duty ratio control signal PWM _ Lim _ L is always at a low level for a plurality of periods, the controller is judged to be in an instantaneous overpower state at the moment, so that the instantaneous overpower judgment unit 102 outputs an instantaneous overpower state signal PEM _ EN _ L to be at a low level, and the instantaneous overpower state signal PEM _ EN _ L is sent to the peak current sampling unit 101 to select a larger maximum peak current limiting threshold value so as to raise the primary peak current of the controller; instantaneous overpower at the same timeThe status signal PEM _ EN _ L is input to the frequency and duty cycle control unit 105, and controls the internal voltage-controlled oscillator to switch to a higher working frequency, so that the GATE pin of the controller outputs the higher working frequency to meet the over-power requirement.
Further, the instantaneous overpower state signal PEM _ EN _ L is also sent to the PWM input gain and output state judgment unit 104, and the voltage signal VFB _ PFM that varies with the voltage of the pin FB is generated by the PWM input gain circuit inside the PWM input gain unit and sent to the frequency and duty ratio control unit 105, so as to control the voltage-controlled oscillator inside the frequency and duty ratio control unit to generate the varying maximum operating frequency, thereby adapting to the requirements of different overpower multiples on the maximum operating frequency.
Further, the frequency and duty ratio control unit 105 outputs a current signal IFB _ PEM varying with the FB voltage to the hold time programmable unit 103, so that the hold time varies with the magnitude of the overpower multiple under the control of the instantaneous overpower state signal PEM _ EN _ L.
Furthermore, the retention time programmable unit 103 is externally connected with different sampling resistors R through PEM pins of the controller PEM (i.e., the sampling resistor R PEM The resistance value can be selected according to actual conditions), and different holding times are generated under the control of the instantaneous overpower state signal PEM _ EN _ L so as to meet the requirements of different overpower states on the holding time.
Further, the instantaneous overpower state signal PEM _ EN _ L is sent to the PWM input gain and output state determination unit 104, and during the holding time of the instantaneous overpower state, the output state is determined by the FB pin voltage of the controller, and an output state signal Vout _ ok _ H is generated and sent to the holding time programming unit 103, and if the output state is recovered to be normal, the output state signal Vout _ ok _ H is at a high level; or the timing of the hold time is over, in both cases the instantaneous overpower state can be exited, so that the hold time programmable unit 103 generates an exit instantaneous overpower state signal PEM _ out _ ok _ L to low level, so that the controller is restored to the normal operation mode.
Fig. 3 is a schematic circuit diagram of an embodiment of the peak current sampling unit 101 according to the present invention. The peak current sampling unit 101 includes alternative data selectors MUX1 and MUX2 and comparators CMP1 and CMP2.
The CS pin is simultaneously connected with the negative phase input end of the comparator CMP1 and the negative phase input end of the comparator CMP2; the positive phase input end of the comparator CMP1 is connected with the output end of the alternative data selector MUX1, the first input end of the alternative data selector MUX1 is the fourth input end of the peak current sampling unit 101, the voltage signal VFB _ PWM is input, the second input end of the alternative data selector MUX1 is the third input end of the peak current sampling unit 101, the voltage signal VFB _ PEM is input, the third input end of the alternative data selector MUX1 is the second input end of the peak current sampling unit 101, the instantaneous overpower state signal PEM _ EN _ L is input, the output end of the comparator CMP1 is the second output end of the peak current sampling unit 101, and the duty ratio control signal PWM _ L is output; a first input end of the either-or data selector MUX2 is used for inputting a first threshold Vref _ Lim1, a second input end of the either-or data selector MUX2 is used for inputting a second threshold Vref _ Lim2, vref _ Lim2 > Vref _ Lim1, a third input end of the either-or data selector MUX2 is connected with a second input end of the peak current sampling unit 101, an instantaneous overpower state signal PEM _ EN _ L is input, an output end of the instantaneous overpower state signal PEM _ EN _ L is connected with a positive phase input end of the comparator CMP2, an output end of the comparator CMP2 is a first output end of the peak current sampling unit 101, and a maximum duty ratio control signal PWM _ Lim _ L is output.
Fig. 4 is a schematic circuit diagram of an embodiment of the alternative data selector MUX1011 of the peak current sampling unit 101 of fig. 3 according to the present invention. The alternative data selector MUX1011 includes NMOS transistors NM1, NM2 and a not gate, the drain of the NMOS transistor NM1 is used as the first input terminal Vin1 of the alternative data selector 1011, the source of the NMOS transistor NM1 is connected with the source of the NMOS transistor NM2, and the junction of the connections is used as the output terminal Vout of the alternative data selector 1011; the input end of the gate nand gate not of the NMOS transistor NM1 is connected, and the junction of the two is used as the third input end Vin3 of the one-out-of-two data selector 1011; the output terminal of the not gate is connected to the gate of the NMOS transistor NM2, and the drain of the NMOS transistor NM2 is used as the second input terminal Vin2 of the one-of-two data selector 1011.
The operation principle of the peak current sampling unit 101 of the present invention is described below with reference to fig. 1, fig. 3 and fig. 4:
the comparator CMP1 is used for detecting the voltage of the CS pin of the controller, and comparing the detected voltage with an output voltage signal fed back by the FB pin through the optical coupler OP1, that is, comparing the detected voltage with a voltage signal VFB _ PWM and a voltage signal VFB _ PEM generated by the PWM input gain and output state judgment unit 104 and varying with the FB voltage, when the instantaneous overpower state signal PEM _ EN _ L is at a low level, comparing the selected voltage signal VFB _ PEM with the voltage signal VCS of the CS pin to generate a duty ratio control signal PWM _ L in the overpower operation mode, and if the instantaneous overpower state signal PEM _ EN _ L is at a high level, comparing the selected voltage signal VFB _ PWM with the voltage signal VCS of the CS pin to generate the duty ratio control signal PWM _ L in the normal operation mode; the comparator CMP2 is used to limit the maximum voltage of the CS pin, that is, the maximum peak current flowing through the primary power tube M1, specifically: if the instantaneous overpower state signal PEM _ EN _ L is at a low level, selecting a higher reference voltage Vref _ Lim2 to be compared with a CS pin voltage signal VCS to generate a maximum duty ratio control signal PWM _ Lim _ L in an overpower working mode, and if the PEM _ EN _ L is at a high level, selecting a maximum peak current limiting threshold Vref _ Lim1 in a normal mode to be compared with the CS pin voltage signal VCS to generate the maximum duty ratio control signal PWM _ Lim _ L in the normal working mode.
Namely, the peak current sampling unit 101 can limit the maximum peak current of the primary side power tube M1 in the normal operating mode, and can also limit the maximum peak current of the primary side power tube M1 in the overpower operating mode; the duty ratio control signal PWM _ L in the normal working mode can be generated, and the duty ratio control signal PWM _ L in the overpower working mode can also be generated.
The peak current sampling unit 101 can distinguish between peak current mode control in the normal operation mode and peak current mode control in the over-power operation mode.
Fig. 5 is a schematic circuit diagram of an embodiment of the transient overpower determination unit 102 according to the present invention. The instantaneous overpower determination unit 102 includes a determination delay unit 1021, an RS latch RS, and a not gate _1. A first input end of the determination delay unit 1021 is a first input end of the instantaneous overpower determination unit 102, the maximum duty ratio control signal PWM _ Lim _ L is input, a second input end thereof is a third input end of the instantaneous overpower determination unit 102, a low voltage driving signal Drive _ H inside the controller is input, a third input end thereof is a fourth input end of the instantaneous overpower determination unit 102, the driving signal GATE is input, an output end thereof outputs the determination signal PEM _ IN _ H entering the instantaneous overpower state to an S end of the RS latch, an R end of the RS latch is a second input end of the instantaneous overpower determination unit 102, the input exits the instantaneous overpower state signal PEM _ out _ ok _ L, an output end Q nand GATE _1 thereof is connected with an input end thereof, and an output end of the not GATE _1 is an output end of the instantaneous overpower determination unit 102, and the instantaneous overpower state signal PEM _ EN _ L is output.
Fig. 6 is a schematic circuit diagram of an embodiment of the determining delay unit 1021 in the instantaneous excessive power determining unit 102 in fig. 5. The determining delay unit 1021 includes RS latches RS1 and RS2, a D flip-flop DFF, not gates not1, not2, and not3, and gates, a leading edge blanking LEB, and a counter. The input end of the not gate1 is connected with the first input end CP _ L of the counter as the second input end of the determining delay unit 1021, and the low-voltage driving signal Drive _ H in the controller is input; the output end of the comparator is connected to the output end of the RS latch RS1, the output end of the comparator is connected to the output end of the GATE comparator RS2, the output end of the comparator DFF is connected to the output end of the frequency and duty control unit 105, the output end of the comparator DFF is connected to the output end of the GATE comparator RS2, the output end of the comparator DFF is connected to the output end of the frequency and duty control unit PEM 3, the output end of the comparator DFF is connected to the output end of the GATE comparator RS2, the output end of the comparator DFF is connected to the output end of the frequency and duty control unit 105, the output end of the comparator DFF is connected to the output end of the comparator DFF 3, the output end of the comparator DFF is connected to the output end of the comparator PEM 3, and the output end of the comparator DFF is connected to the output end of the comparator DFF 3.
Fig. 7 is a schematic circuit diagram of an embodiment of the programmable sustain time unit 103 according to the present invention. The hold time programmable unit 103 comprises a current source IB 1 、IB 2 The circuit comprises a capacitor C1, an NMOS tube NM1_1, a comparator CMP, a NAND gate nand, a latch LATH, a D flip-flop DFF1, NOT4, NOT5 and NOT6, a Delay Delay, a counter1 and an AND gate and1.
Current source IB 1 Is used for inputting a low-voltage power supply VCC and a current source IB 1 Is simultaneously connected to the second input terminal of the hold time programmable unit 103 and the non-inverting input terminal of the comparator CMP; current source IB 2 The input terminal of (B) is used for inputting a low-voltage power supply VCC and a current source IB 2 The output terminal of the comparator is simultaneously connected with the fourth input terminal of the hold time programmable unit 103, one terminal of the capacitor C1, the drain of the NMOS transistor NM1_1 and the inverting input terminal of the comparator CMP; the other end of the capacitor C1 is simultaneously connected with the source electrode of the NMOS tube NM1_1 and the ground; the grid of the NMOS tube NM1_1 is connected with the output end of the NAND gate nand, the first input end of the NAND gate nand is simultaneously connected with the output end of the latch LATH and the second input end CP _ L of the D flip-flop DFF1, and the second input end of the NAND gate nand and the third input end Clr _ L of the D flip-flop DFF1 are connected together and used for inputting a low-voltage initialization signal ENP _ lv inside the controller; the input of the latch is connected to the output of the comparator CMP; a first input end D of the D flip-flop DFF1 is connected with a second output end thereof, a first output end Q of the D flip-flop DFF is connected with an input end of a nand gate not4, an output end of a not gate not4 is connected with a first input end CP _ L of a counter1, an output end of a Clr _ L nand gate not5 of the counter1 is connected, an input end of the not gate not5 is connected with an output end of the instantaneous overpower judging unit 102, and the connection is used as a third input end of the maintaining time programmable unit 103 to input an instantaneous overpower state signal PEM _ EN _ L;the output terminal of the counter1 is connected to the input terminal of the nand gate not6, the output terminal of the not gate not6 outputs the instantaneous overpower-along-with-sustain-time completion status signal PEM _ out _ Tkeep _ ok _ L to the second input terminal of the and gate and1, the first input terminal of the and gate and1 is connected to the output terminal of the Delay, the input instantaneous overpower and the output state judgment completion state signal PEM _ out _ Vout _ ok _ L, the input end of the Delay is connected with the first output end of the PWM input gain and output state judgment unit 104, and this connection is used as the third input end of the hold time programmable unit, and the output state signal Vout _ ok _ H is input.
With reference to fig. 5, fig. 6 and fig. 7, the operation principle of the embodiment of the instant overpower judgment unit 102 and the embodiment of the hold time programmable unit 103 of the present invention is briefly described as follows:
if the maximum duty ratio control signal PWM _ Lim _ L is always at a low level for several cycles, determining that the controller is in an instantaneous overpower state at the moment, so that the instantaneous overpower determination unit 102 outputs an instantaneous overpower state signal PEM _ EN _ L at a low level, the instantaneous overpower state signal PEM _ EN _ L is sent to the PWM input gain and output state determination unit 104, within the maintenance time of the instantaneous overpower state, the output state is determined by the FB pin voltage of the controller, an output state signal Vout _ ok _ H is generated, the signal Vout _ ok _ H is sent to the maintenance time programmable unit 103, and if the output state is recovered to be normal, the output state signal Vout _ ok _ H is at a high level; or the timing of the hold time is over, in both cases, the instantaneous overpower state can be exited, so that the hold time programmable unit 103 generates an exit instantaneous overpower state signal PEM _ out _ ok _ L as low level, and the controller is restored to the normal operation mode.
Further, the retention time programmable unit 103 is externally connected with different sampling resistors R through a PEM pin of the controller PEM Under the control of the instantaneous overpower state signal PEM _ EN _ L, different holding times are generated to meet the requirements of different overpower states for the holding times.
Further, the frequency and duty ratio control unit 105 outputs a current signal IFB _ PEM varying with the FB voltage to the hold time programmable unit 103, so that the hold time varies with the magnitude of the over-power multiple under the control of the instantaneous over-power state signal PEM _ EN _ L.
Fig. 8 is a schematic circuit diagram of an embodiment of the PWM input gain and output state determination unit 104 according to the present invention. The PWM input gain and output state decision unit 104 includes a PWM input gain 1041, an alternative data selector MUX3, a comparator CMP3, and a not gate 7.
A first input terminal of the PWM input gain 1041 is connected to the FB pin of the controller, and this connection is used as a second input terminal of the PWM input gain and output state determination unit 104; a second input end of the PWM input gain 1041 is a first input end of the PWM input gain and output state judgment unit 104, inputs the PEM _ EN _ L signal, and is connected to an output end of the instantaneous overpower judgment unit 102 and a third input end of the alternative data selector MUX; a first output terminal of the PWM input gain 1041 outputs a VFB _ OLP signal, which is connected to a non-inverting input terminal of the comparator CMP3, and a second output terminal, a third output terminal, and a fourth output terminal of the PWM input gain 1041 are respectively used as a second output terminal, a third output terminal, and a fourth output terminal of the PWM input gain and output state determination unit 104, which respectively output a VFB _ PFM signal, a VFB _ PEM signal, and a VFB _ PWM signal; a first input end of the one-of-two data selector MUX3 is used for inputting a reference voltage signal Vref1 inside the controller, a second input end of the one-of-two data selector MUX3 is used for inputting a reference voltage signal Vref2 inside the controller, an output end of the one-of-two data selector MUX is connected with a negative phase input end of the comparator CMP, an output end of the comparator CMP3 is connected with an input end of the nand gate not7, and an output end of the not gate not7 is used as a first output end of the PWM input gain and output state judgment unit 104 to output a Vout _ ok _ H signal.
Fig. 9 is a schematic circuit diagram of an embodiment of the PWM input gain 1041 in the PWM input gain and output state determination unit 104 of fig. 8. The PWM input gain 1041 includes a switched capacitor Filter, an NMOS transistor NM3, and resistors R1, R2, R3, and R4.
The input end of the switched capacitor Filter is connected with an FB pin of the controller, the first output end of the switched capacitor Filter is connected with the grid electrode of the NMOS tube NM3, and the second output end of the switched capacitor Filter is used as the second output end of the PWM input gain 1041 to output a VFB _ PFM signal; the drain electrode of the NMOS transistor NM3 is used for connecting a low-voltage power supply VCC, the source electrode of the NMOS transistor NM3 is connected with one end of the resistor R1, the other end of the resistor R1 is connected with one end of the resistor R2, and a junction of the connection is used as a first output end of the PWM input gain 1041 to output a VFB _ OLP signal; the other end of the resistor R2 is connected to one end of the resistor R3, and the junction of the connection is used as a third output end of the PWM input gain 1041 to output a VFB _ PEM signal; the other end of the resistor R3 is connected to one end of the resistor R4, and the junction of the connection serves as a fourth output end of the PWM input gain 1041, which outputs the VFB _ PWM signal, and the other end of the resistor R4 is connected to the ground of the controller.
Fig. 10 is a schematic circuit diagram of an embodiment of the frequency and duty cycle control unit 105 according to the present invention. The frequency and duty cycle control unit 105 includes a voltage controlled oscillator VCO, and GATE2, RS latch RS3, GATE pin driving Driver and controller.
The first input terminal of the voltage-controlled oscillator VCO is the third input terminal of the frequency and duty cycle control unit 105, the PEM _ EN _ L signal is input, the output terminal of the instantaneous overpower judgment unit 102 is connected, the second input terminal of the voltage-controlled oscillator VCO is the fourth input terminal of the frequency and duty cycle control unit 105, the VFB _ PFM signal is input, the second output terminal of the PWM input gain and output state judgment unit 104 is connected, the first output terminal of the voltage-controlled oscillator VCO outputs the IFB _ PEM signal, the IFB _ PEM signal is connected to the fourth input terminal of the hold time programmable unit 103, the third output terminal IFB _ PEM is used as the frequency and duty cycle control unit, the second output terminal CLK of the voltage-controlled oscillator VCO is connected to the S terminal of the RS latch, the R terminal of the RS latch RS3 is connected to the output terminal of the and GATE and2, the first input terminal of the and GATE2 is the second input terminal of the frequency and duty ratio control unit 105, the PWM _ L signal is input and connected to the second output terminal of the peak current sampling unit 101, the second input terminal of the and GATE2 is the first input terminal of the frequency and duty ratio control unit 105, the PWM _ Lim _ L signal is input and connected to the first output terminal of the peak current sampling unit 101, the output terminal of the RS latch RS3 outputs the Drive _ H signal and is connected to the input terminal of the Drive, which is connected as the second output terminal of the frequency and duty ratio control unit 105, and the output terminal of the Drive is connected to the GATE pin of the controller as the first output terminal of the frequency and duty ratio control unit 105.
It should be noted that the structure of the voltage controlled oscillator is common knowledge of those skilled in the art, and a common structure is a voltage input differential pair, which controls the transconductance amplifier to generate a varying current, and the current charges and discharges a capacitor in combination with a voltage comparator to generate a varying frequency. The voltage-controlled oscillator in the embodiment of the invention has the function of generating the maximum working frequency which is changed along with the voltage signal VFB _ PFM when the instantaneous overpower state signal PEM _ EN _ L is effective so as to adapt to the requirements of different overpower multiples on the maximum working frequency.
With reference to fig. 8, 9 and 10, the operation principle of the PWM input gain and output state determining unit 104 and the frequency and duty ratio control unit 105 according to the present invention is described as follows:
the FB pin of the controller generates voltage signals VFB _ PFM, VFB _ OLP, VFB _ PEM and VFB _ PWM varying with the FB voltage through the switched capacitor Filter and the voltage dividing resistors R1 to R4. The voltage signal VFB _ PFM is sent to the frequency and duty cycle control unit 105 to generate a current signal IFB _ PEM varying with the FB voltage, and control the voltage controlled oscillator VCO therein to generate a varying maximum operating frequency, so as to meet the requirements of different overpower multiples on the maximum operating frequency. Comparing the voltage signal VFB _ OLP with a reference voltage inside the controller (Vref 1 or Vref2 is selected depending on the PEM _ EN _ L signal, vref1 is selected when the PEM _ EN _ L signal is high, vref2 is selected when the PEM _ EN _ L signal is low; vref1> Vref 2) to generate an output status signal Vout _ ok _ H; the voltage signals VFB _ PEM and VFB _ PWM are provided to the peak current sampling unit 101 for generating the duty cycle control signal PWM _ L in the normal mode.
Further, the frequency and duty ratio control unit 105 outputs a current IFB _ PEM varying with the FB voltage to the hold time programmable unit 103, and the hold time varies with the magnitude of the overpower multiple under the control of the instantaneous overpower state signal PEM _ EN _ L.
Further, the instantaneous overpower state signal PEM _ EN _ L is sent to the PWM input gain and output state judgment unit 104, the output state is judged by the FB pin voltage of the controller during the maintenance time of the instantaneous overpower state, an output state signal Vout _ ok _ H is generated, and the signal Vout _ ok _ H is sent to the maintenance time programmable unit 103, if the output state is recovered to normal, vout _ ok _ H is at high level; or the timing of the hold time is over, in both cases, the instant overpower state can be exited, so that the signal PEM _ out _ ok _ L for exiting the instant overpower state generated by the hold time programmable unit 103 is at a low level, and the controller is restored to the normal operation mode.
Fig. 11 is a schematic diagram showing waveforms of signals related to a large dynamic load and an instantaneous overpower state of a flyback converter to which the instantaneous overpower control circuit 100 of the present invention is applied. With reference to fig. 1, the analysis is as follows:
iout is the output load current, 10% Io represents the load of 10%; 100% Io represents 100% load, which we generally refer to as full load; 400% Io represents 4 times full load, i.e. 4 times overpower. VFB represents the voltage of the FB pin of the controller; VCS represents the voltage at the CS pin of the controller; PEM _ EN _ L is the output signal of the instantaneous overpower judgment unit 102; GATE is an output signal of the frequency and duty ratio control unit 105.
As can be seen in FIG. 11, in the case of normal large dynamic load jump 10-100% Io-10%, the VCS voltage is lower than the maximum peak current limit threshold Vref _ Lim1 in the normal mode, and the instantaneous overpower state is not triggered, i.e., the instantaneous overpower state signal PEM _ EN _ L is high; in the event of a jump between normal load and instantaneous overpower, i.e., 10-400 Io-10 Io, the VCS voltage would be higher than the maximum peak current limiting threshold Vref _ Lim1 in the normal mode, and the instantaneous overpower state would normally be entered, i.e., the instantaneous overpower state signal PEM _ EN _ L would be low.
Further, comparing before and after the instantaneous overpower state, it can be found that both the operating frequency and the peak current of the controller are increased when the PEM _ EN _ L is at an active low level (the increase of the operating frequency of the controller is reflected in that the interval time of the GATE signal appearing at a high level is shortened, and the increase of the peak current is reflected in that the VCS voltage is increased), so as to meet the demand of the instantaneous overpower. In the event PEM _ EN _ L is high, the instantaneous over-power state may be exited and the normal operating mode restored, with the operating frequency and peak current of the controller restored to normal.
Fig. 12 is a diagram showing simulation-related signal waveforms of a large dynamic load and an instantaneous overpower state system of a flyback converter to which the instantaneous overpower control circuit 100 of the present invention is applied. With reference to fig. 1, the following was analyzed:
vout is output voltage of the flyback converter, iout is output load current of the flyback converter, and VFB is voltage of an FB pin of the controller; VCS is the voltage of CS pin of controller; PEM _ EN _ L is the output signal of the instantaneous overpower judgment unit 102; GATE is an output signal of the frequency and duty ratio control unit 105.
As can be seen from fig. 12, when the normal load is switched to the instantaneous overpower state, the transient response of the system is fast due to the fast increase of the peak current and the operating frequency, and further the power loss of the output voltage Vout of the system is less than 10%; under the normal large dynamic load jump condition, the system can not enter an instantaneous overpower state, and the over-and-under rush of the system is very small; meanwhile, after the instantaneous overpower load is recovered to the normal load, the system normally jumps out of the instantaneous overpower state, the output voltage Vout overshoot of the system is small, and the system index requirement is met.
Fig. 13 is a schematic circuit diagram of an alternative embodiment of the alternative data selector MUX1011 of the peak current sampling unit 101 of fig. 3. The difference from fig. 3 is that NMOS transistors NM1 and NM2 are replaced by transfer gates Transgate1 and Transgate2, and the specific connection relationship is as follows:
the input end of the transmission gate Transgate1 is used as the first input end Vin1 of the alternative data selector 1011, the output end of the transmission gate Transgate1 is connected with the output end of the transmission gate Transgate2, and the junction of the connection is used as the output end Vout of the alternative data selector 1011; the positive control end of the transmission gate Transgate1 is simultaneously connected with the negative control end of the transmission gate Transgate2 and the output end of the NOT 8; the inverting control terminal of the transmission gate Transgate1 is connected with the non-inverting control terminal of the transmission gate Transgate2 and the input terminal of the not gate not8 at the same time, and the junction of the connection is used as the third input terminal Vin3 of the one-out-of-two data selector 1011; an input terminal of the transmission gate Transgate2 serves as a second input terminal Vin2 of the one-out-of-two data selector 2011.
Since the alternative data selector can make the NMOS transistors NM1 and NM2 operate in a linear region when the low voltage VCC =5V is selected, but if the low voltage VCC =3V is selected, the NMOS transistors cannot be used under a relatively high level value of Vin1 and Vin2, because the NMOS transistors operate in a saturation region, the input voltage Vin1 or Vin2 is not normally transferred to the output Vout, which affects the transmission effect. In the embodiment of the alternative data selector, the NMOS transistors NM1 and NM2 in fig. 4 are replaced by the transmission gates Transgate1 (a PMOS transistor and an NMOS transistor are used as a conventional structure, the gates of the transistors are respectively connected to two control signals with opposite potentials, and the drains and sources of the transistors are respectively connected in parallel) and the transmission gates Transgate2, so that even if the low voltage VCC =3V is selected, the PMOS transistor in the transmission gate can operate in a linear region, so that the input voltage Vin1 or Vin2 can be normally transmitted to the output Vout at a relatively high level, thereby ensuring the reliability and effectiveness of transmission.
The foregoing is merely a preferred embodiment of this invention, it being noted that the above-mentioned preferred embodiment should not be considered as limiting of this invention, and it being recognized that this invention is applicable in other broader contexts. According to the present invention, it is possible to make various modifications, substitutions and alterations without departing from the basic technical idea of the invention, and it is within the scope of the appended claims.

Claims (15)

1. A transient overpower control method is applied to a power converter, the power converter comprises a power tube and a controller, and the control method is characterized by comprising the following steps:
a peak current sampling step, namely detecting through a CS pin of a controller to generate a voltage signal VCS changing along with the source voltage when a power tube is conducted;
a PWM input gain and output state judgment step, namely detecting through an FB pin of a controller to generate a voltage signal VFB _ PFM, a voltage signal VFB _ PEM and a voltage signal VFB _ PWM which change along with the output voltage of the power converter, and an output state signal Vout _ ok _ H reflecting the over-power condition output by the power converter;
in the peak current sampling step, the obtained voltage signal VCS is selected to be compared with a voltage signal VFB _ PEM or a voltage signal VFB _ PWM to generate a duty ratio control signal PWM _ L; and also selectively comparing the obtained voltage signal VCS with a first threshold Vref _ Lim1 or a second threshold Vref _ Lim2 to generate a maximum duty ratio control signal PWM _ Lim _ L;
an instantaneous overpower judging step, namely generating an instantaneous overpower state signal PEM _ EN _ L according to the maximum duty ratio control signal PWM _ Lim _ L;
a maintaining time programmable step, generating the maintaining time of the overpower state according to the instantaneous overpower state signal PEM _ EN _ L; generating an exit instantaneous overpower state signal PEM _ out _ ok _ L according to the instantaneous overpower state signal PEM _ EN _ L and the output state signal Vout _ ok _ H;
a frequency and duty ratio control step, wherein a driving signal GATE, a low-voltage driving signal Drive _ H inside a controller and a current signal IFB _ PEM changing along with the output voltage of a power converter are generated according to an instantaneous overpower state signal PEM _ EN _ L, a maximum duty ratio control signal PWM _ Lim _ L, a duty ratio control signal PWM _ L and a voltage signal VFB _ PFM; meanwhile, a first working frequency of the controller working in a normal working mode or a second working frequency of the controller working in an instantaneous overpower mode is selected according to an instantaneous overpower state signal PEM _ EN _ L and a voltage signal VFB _ PFM;
the Vref _ Lim1 is less than Vref _ Lim2, the first working frequency is less than the second working frequency, and the second working frequency changes along with the change of the voltage signal VFB _ PFM;
the steps also include realizing the switch of the working mode of the controller according to the following control logic;
when the VCS is less than or equal to Vref _ Lim1 or the VCS is more than the Vref _ Lim1 but the lasting time is less than N periods, the maximum duty ratio control signal PWM _ Lim _ L and the instantaneous overpower state signal PEM _ EN _ L are both high level, the controller works in a normal working mode, the selection voltage signal VCS is compared with a first threshold Vref _ Lim1, and the controller works at a first working frequency;
when the duration time of VCS & gt Vref _ Lim1 is more than or equal to N periods, the maximum duty ratio control signal PWM _ Lim _ L and the instantaneous overpower state signal PEM _ EN _ L are both low levels, the controller works in an instantaneous overpower working mode, the voltage selection signal VCS is compared with a second threshold Vref _ Lim2, and the controller works at a second working frequency;
when the instantaneous overpower state signal PEM _ EN _ L is at a low level, if the output state of the power converter is recovered to normal, the output state signal Vout _ ok _ H is at a high level; when the maintaining time is over or the output state signal Vout _ ok _ H is at a high level, the exiting instantaneous overpower state signal PEM _ out _ ok _ L is at a low level, and the controller is recovered to a normal working mode;
wherein N is a positive integer of a given value.
2. The control method according to claim 1, characterized in that: the higher the overpower multiple output by the power converter is, the higher the second working frequency is.
3. The control method according to claim 1, characterized in that: the duration is set by the PEM pin of the controller, and the higher the overpower multiple output by the power converter, the shorter the duration.
4. A transient overpower control circuit for a power converter, the power converter comprising a power transistor and a controller, the transient overpower control circuit comprising: the device comprises a peak current sampling unit, an instantaneous overpower judging unit, a maintaining time programmable unit, a PWM input gain and output state judging unit and a frequency and duty ratio control unit;
the peak current sampling unit is used for generating a voltage signal VCS changing along with the source voltage when the power tube is conducted through the detection of a CS pin of the controller;
the PWM input gain and output state judgment unit is used for generating a voltage signal VFB _ PFM, a voltage signal VFB _ PEM and a voltage signal VFB _ PWM which change along with the output voltage of the power converter and an output state signal Vout _ ok _ H reflecting the over-power condition output by the power converter through the detection of an FB pin of the controller;
the peak current sampling unit also selects to compare the obtained voltage signal VCS with the voltage signal VFB _ PEM or the voltage signal VFB _ PWM to generate a duty ratio control signal PWM _ L; and also selectively comparing the obtained voltage signal VCS with a first threshold value Vref _ Lim1 or a second threshold value Vref _ Lim2 to generate a maximum duty ratio control signal PWM _ Lim _ L;
the instantaneous overpower judging unit generates an instantaneous overpower state signal PEM _ EN _ L according to the maximum duty ratio control signal PWM _ Lim _ L;
the maintaining time programmable unit generates maintaining time of the overpower state according to the instantaneous overpower state signal PEM _ EN _ L; generating an exit instantaneous overpower state signal PEM _ out _ ok _ L according to the instantaneous overpower state signal PEM _ EN _ L and the output state signal Vout _ ok _ H;
the frequency and duty ratio control unit generates a driving signal GATE, a low-voltage driving signal Drive _ H in the controller and a current signal IFB _ PEM changing along with the output voltage of the power converter according to an instantaneous overpower state signal PEM _ EN _ L, a maximum duty ratio control signal PWM _ Lim _ L, a duty ratio control signal PWM _ L and a voltage signal VFB _ PFM; meanwhile, a first working frequency of the controller working in a normal working mode or a second working frequency of the controller working in an instantaneous overpower mode is selected according to an instantaneous overpower state signal PEM _ EN _ L and a voltage signal VFB _ PFM;
the Vref _ Lim1 is less than Vref _ Lim2, the first working frequency is less than a second working frequency, and the second working frequency changes along with the change of a voltage signal VFB _ PFM;
each circuit unit also realizes the switching of the working mode of the controller according to the following control logic;
when VCS is less than or equal to Vref _ Lim1 or the VCS is more than Vref _ Lim1 but the lasting time is less than N periods, the maximum duty ratio control signal PWM _ Lim _ L and the instantaneous overpower state signal PEM _ EN _ L are both high level, the controller works in a normal working mode, the peak current sampling unit selection voltage signal VCS is compared with a first threshold Vref _ Lim1, and the frequency and duty ratio control unit selects the controller to work at a first working frequency;
when the duration time of VCS & gt Vref _ Lim1 is more than or equal to N periods, the maximum duty ratio control signal PWM _ Lim _ L and the instantaneous overpower state signal PEM _ EN _ L are both low level, the controller works in an instantaneous overpower working mode, the peak current sampling unit selects the voltage signal VCS to be compared with a second threshold value Vref _ Lim2, and the frequency and duty ratio control unit selects the controller to work at a second working frequency;
when the instantaneous overpower state signal PEM _ EN _ L is at a low level, if the output state of the power converter is recovered to be normal, the output state signal Vout _ ok _ H is at a high level, when the maintaining time is over or the output state signal Vout _ ok _ H is at a high level, the instantaneous overpower state signal PEM _ out _ ok _ L is exited to be at a low level, and then the controller is recovered to be in a normal working mode;
wherein N is a set positive integer.
5. The control circuit of claim 4, wherein: the higher the overpower multiple output by the power converter is, the higher the second working frequency is.
6. The control circuit of claim 4, wherein: the duration is set by the PEM pin of the controller, and the higher the overpower multiple output by the power converter, the shorter the duration.
7. The control circuit of claim 4, wherein: the peak current sampling unit comprises an alternative data selector MUX1, an alternative data selector MUX2, a comparator CMP1 and a comparator CMP2; the negative phase input end of the comparator CMP1 is used for being connected with a CS pin of the controller and is connected with the negative phase input end of the comparator CMP2, the positive phase input end of the comparator CMP1 is connected with the output end of the alternative data selector MUX1, and the output end of the comparator CMP outputs a duty ratio control signal PWM _ L; a first input end of the alternative data selector MUX1 inputs a voltage signal VFB _ PWM, a second input end inputs a voltage signal VFB _ PEM, and a third input end of the alternative data selector MUX2 is connected with a third input end of the alternative data selector to input an instantaneous overpower state signal PEM _ EN _ L; a first threshold value Vref _ Lim1 is input to a first input end of the alternative data selector MUX2, a second threshold value Vref _ Lim2 is input to a second input end, and an output end of the alternative data selector MUX2 is connected with a positive phase input end of a comparator CMP2; the output terminal of the comparator CMP2 outputs the maximum duty ratio control signal PWM _ Lim _ L.
8. The transient overpower control circuit of claim 7, wherein: the alternative data selector MUX1 comprises an NMOS tube NM1, an NMOS tube NM2 and a NOT, wherein the drain electrode of the NMOS tube NM1 is used as a first input end of the alternative data selector MUX1, the source electrode of the NMOS tube NM1 is connected with the source electrode of the NMOS tube NM2, and the junction of the connection is used as the output end of the alternative data selector MUX 1; the input ends of the grid NAND gates not of the NMOS tube NM1 are connected, and the connection intersection is used as a third input end of the alternative data selector MUX 1; the output end of the NOT is connected with the grid electrode of the NMOS tube NM2, and the drain electrode of the NMOS tube NM2 is used as the second input end of the alternative data selector.
9. The transient overpower control circuit of claim 7, wherein: the two-out data selector MUX1 comprises a transmission gate Transgate1, a transmission gate Transgate2 and a NOT, wherein the input end of the transmission gate Transgate1 is used as the first input end of the two-out data selector MUX1, the output end of the transmission gate Transgate1 is connected with the output end of the transmission gate Transgate2, and the connection intersection is used as the output end of the two-out data selector MUX 1; the input ends of the positive control ends and the non-gate of the transmission gate Transgate1 are connected, and the junction of the connection is used as a third input end of the alternative data selector MUX 1; the output end of the NOT gate is connected with the forward control end of the transmission gate Transgate2, and the input end of the transmission gate Transgate2 is used as the second input end of the alternative data selector.
10. The transient overpower control circuit of claim 4, wherein: the instantaneous overpower judging unit comprises a judging delay unit, an RS latch and a NOT _1; the judgment delay unit generates a judgment signal PEM _ IN _ H entering an instantaneous overpower state according to a maximum duty ratio control signal PWM _ Lim _ L input from a first input end, a low-voltage driving signal Drive _ H input from a second input end and a driving signal GATE input from a third input end, the judgment signal PEM _ IN _ H is output to an S end of the RS latch, an R end of the RS latch inputs and exits the instantaneous overpower state signal PEM _ out _ ok _ L, an output end Q of the RS latch is connected with an input end of a NAND GATE not _1, and an output end of a NOT _1 outputs an instantaneous overpower state signal PEM _ EN _ L.
11. The transient overpower control circuit of claim 10, wherein: the judging delay unit comprises an RS latch RS1, an RS latch RS2, a D trigger DFF, a NOT1, a NOT2, a NOT3, an AND gate and, a leading edge blanking LEB and a counter; the output end Q of the D flip-flop DFF is simultaneously connected with the output end of the AND GATE and the R end of the RS latch RS2, the first input end of the AND GATE and the GATE is connected with the first input end of the counter and the second input end of the GATE is connected with an instantaneous over-power state signal EN _ L, the second input end of the AND GATE is used for inputting a low-voltage initialization signal ENP _ lv IN the controller, the output end Q of the D flip-flop DFF is connected with the second input end of the counter and the GATE is connected with the second input end of the counter PEM _ L, the second input end of the GATE is connected with the output end of the NOT GATE of the counter PEM 3, the output end Q of the D flip-flop is connected with the output end of the NOT GATE of the counter, the output end Q of the NOT GATE is connected with the output end of the NOT GATE of the counter 2, and the output end Q of the NOT GATE is connected with the output end of the NOT GATE.
12. The transient of claim 4An overpower control circuit, characterized by: the programmable unit comprises a current source IB 1 A current source IB 2 The circuit comprises a capacitor C1, an NMOS tube NM1_1, a comparator CMP, a NAND gate nand, a latch LATH, a D trigger DFF1, a NOT4, a NOT5, a NOT6, a Delay and an AND gate and1;
current source IB 1 The input end of the voltage source is used for connecting a low-voltage power supply VCC, the output end of the voltage source is used for connecting a PEM pin of a controller, and the current source IB 1 The output terminal of the comparator is also connected with the positive phase input terminal of the comparator CMP; current source IB 2 The input terminal is used for connecting a low-voltage power supply VCC 、 The current signal IFB _ PEM and the current source IB are input into the output end 2 The output end of the comparator is also simultaneously connected with one end of the capacitor C1, the drain electrode of the NMOS tube NM1_1 and the inverting input end of the comparator CMP; the other end of the capacitor C1 is simultaneously connected with the source electrode of the NMOS tube NM1_1 and the ground of the controller; the grid of the NMOS tube NM1_1 is connected with the output end of the NAND gate nand, the first input end of the NAND gate nand is simultaneously connected with the output end of the latch LATH and the second input end CP of the D flip-flop DFF1, and the second input end of the NAND gate nand is connected with the third input end Clr _ L of the D flip-flop DFF1 for inputting a low-voltage initialization signal ENP _ lv inside the controller; the input of the latch is connected to the output of the comparator CMP; a first input terminal D of the D flip-flop DFF1 and a second output terminal of the D flip-flop
Figure FDA0003853489340000051
The input end of a first output end Q of the D trigger DFF1 and the input end of a NAND gate not4 are connected, the output end of the NOT4 is connected with a first input end CP _ L of a counter1, a second input end Clr _ L of the counter1 and the output end of a NAND gate not5 are connected, and the input end of the NOT5 inputs an instantaneous overpower state signal PEM _ EN _ L; the output end of the counter1 is connected with the input end of the NAND gate not6, the output end of the NOT6 is connected with the second input end of the AND gate and1, the first input end of the AND gate and1 is connected with the output end of the Delay, and the input end of the Delay inputs and outputs the state signal Vout _ ok _ H.
13. The transient overpower control circuit of claim 4, wherein: the PWM input gain and output state judging unit comprises a PWM input gain, an alternative data selector MUX3, a comparator CMP3 and a NOT7; the first input end of the PWM input gain is used for being connected with an FB pin of the controller, the second input end of the PWM input gain is connected with the third input end of the alternative data selector MUX3 and then inputs an instantaneous overpower state signal PEM _ EN _ L, the first output end of the PWM input gain is connected with the positive input end of the comparator CMP3, and the second output end, the third output end and the fourth output end of the PWM input gain respectively output a voltage signal VFB _ PFM, a voltage signal VFB _ PEM and a voltage signal VFB _ PWM; the first input end of the alternative data selector MUX3 is used for connecting a first reference voltage signal Vref1 input into the controller, the second input end of the alternative data selector MUX3 is used for connecting a second reference voltage signal Vref2 input into the controller, the output end of the alternative data selector MUX3 is connected with the negative phase input end of the comparator CMP3, the output end of the comparator CMP3 is connected with the input end of the nand gate not7, and the output end of the not gate not7 outputs an output state signal Vout _ ok _ H.
14. The transient overpower control circuit of claim 13, wherein: the PWM input gain comprises a switched capacitor Filter, an NMOS tube NM3, a resistor R1, a resistor R2, a resistor R3 and a resistor R4; the input end of the switched capacitor Filter is used for being connected with an FB pin of the controller, the first output end of the switched capacitor Filter is connected with the grid electrode of the NMOS tube NM3, and the second output end of the switched capacitor Filter outputs a voltage signal VFB _ PFM; the drain electrode of the NMOS tube NM3 is used for being connected with a low-voltage power supply VCC, the source electrode of the NMOS tube NM3 is connected with one end of a resistor R1, the other end of the resistor R1 is connected with one end of a resistor R2, and the connection intersection is connected with the positive phase input end of a comparator CMP 3; the other end of the resistor R2 is connected with one end of the resistor R3, and a voltage signal VFB _ PEM is output at the junction of the connection; the other end of the resistor R3 is connected with one end of the resistor R4, the voltage signal VFB _ PWM is output at the junction of the connection, and the other end of the resistor R4 is connected with the ground of the controller.
15. The transient overpower control circuit of claim 4, wherein: the frequency and duty ratio control unit comprises a voltage-controlled oscillator VCO, an AND gate and2, an RS latch RS3 and a drive; the first input end of the voltage-controlled oscillator VCO inputs an instantaneous overpower state signal PEM _ EN _ L, the second input end of the voltage-controlled oscillator VCO inputs a voltage signal VFB _ PFM, the first output end of the voltage-controlled oscillator VCO outputs a current signal IFB _ PEM, the second output end of the voltage-controlled oscillator VCO is connected with the S end of an RS latch RS3, the R end of the RS latch is connected with the output end of an AND GATE and2, the first input end of the AND GATE and2 inputs a duty ratio control signal PWM _ L, the second input end of the AND GATE and inputs a maximum duty ratio control signal PWM _ Lim _ L, the output end Q of the RS latch RS3 is connected with the input end of a Driver, the connection point outputs a low-voltage driving signal Driver _ H inside the controller, and the output end of the Driver outputs a driving signal GATE.
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