CN112928024B - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN112928024B CN112928024B CN201911241309.9A CN201911241309A CN112928024B CN 112928024 B CN112928024 B CN 112928024B CN 201911241309 A CN201911241309 A CN 201911241309A CN 112928024 B CN112928024 B CN 112928024B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
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Abstract
A semiconductor structure and a method of forming the same, comprising: providing a substrate, wherein the substrate is provided with a fin structure, and the fin structure comprises a plurality of overlapped first fin layers and second fin layers positioned between two adjacent first fin layers; forming a dummy gate structure crossing the fin structure on the substrate; forming grooves in fin structures on two sides of the pseudo gate structure; removing part of the first fin portion layer on the side wall of the groove to form a first modified fin portion layer, a first fin portion groove and a second fin portion groove; forming a first barrier layer in the first fin groove and a second barrier layer in the second fin groove, wherein the thickness of the first barrier layer is larger than that of the second barrier layer; and forming a source-drain doping layer in the groove. Through increasing the thickness of the first barrier layer, the isolation effect between the source-drain doped layer and the formed grid structure can be effectively improved, the parasitic capacitance between the source-drain doped layer and the grid structure is reduced, and the performance of the finally formed semiconductor structure is improved.
Description
Technical Field
The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a semiconductor structure and a method for forming the same.
Background
With the rapid development of semiconductor manufacturing technology, semiconductor devices are being developed toward higher element density, and higher integration. The device is used as the most basic semiconductor device, is widely applied at present, the control capability of the traditional planar device on channel current is weakened, short channel effect is generated to cause leakage current, and the electrical property of the semiconductor device is finally affected.
In order to overcome the short channel effect of the device and suppress the leakage current, the prior art proposes a Fin field effect transistor (Fin FET), which is a common multi-gate device, and the structure of the Fin field effect transistor includes: the barrier layer covers part of the side wall of the fin part, and the surface of the barrier layer is lower than the top of the fin part; gate structures located on the surface of the barrier layer, and on the top and sidewall surfaces of the fin; and the source region and the drain region are positioned in the fin parts at two sides of the grid structure.
However, the semiconductor structures formed by the prior art have poor performance.
Disclosure of Invention
The invention solves the technical problem of providing a semiconductor structure and a forming method thereof, which can effectively reduce parasitic capacitance between a source-drain doped layer and a grid structure and improve the performance of the finally formed semiconductor structure.
In order to solve the above problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, wherein the substrate is provided with a fin structure, and the fin structure comprises a plurality of layers of first fin layers overlapped along the normal direction of the surface of the substrate and a second fin layer positioned between two adjacent layers of first fin layers; forming a dummy gate structure on the substrate, wherein the dummy gate structure spans the fin structure and covers part of the side wall and part of the top surface of the fin structure; forming grooves in fin structures on two sides of the pseudo gate structure; removing part of the first fin portion layer on the side wall of the groove to form a first modified fin portion layer, a first fin portion groove and a second fin portion groove, wherein the first fin portion groove is positioned between the first modified fin portion layer on the bottom layer and the substrate, and the second fin portion groove is positioned between the second fin portion layers on two adjacent layers; forming a first barrier layer positioned in the first fin portion groove and a second barrier layer positioned in the second fin portion groove, wherein the thickness of the first barrier layer is larger than that of the second barrier layer; after the first barrier layer and the second barrier layer are formed, a source-drain doped layer is formed in the groove, and source-drain ions are arranged in the source-drain doped layer.
Optionally, the forming method of the first barrier layer and the second barrier layer includes: forming a first initial barrier layer on the side wall and the bottom surface of the groove and the side wall and the top surface of the pseudo gate structure; etching back the first initial barrier layer until the bottom surface of the groove and the top surface of the pseudo gate structure are exposed, and forming a second initial barrier layer; forming a sacrificial layer at the bottom of the groove, wherein the sacrificial layer covers part of the side wall of the second initial blocking layer, and the top surface of the sacrificial layer is lower than or flush with the top surface of the first modified fin layer positioned at the bottom layer; etching back the second initial barrier layer until the side wall of the second fin portion layer is exposed, and forming the first barrier layer and the second barrier layer; after forming the first barrier layer and the second barrier layer, the sacrificial layer is removed.
Optionally, the material of the first initial barrier layer comprises silicon nitride.
Optionally, the process of forming the first initial barrier layer includes a physical vapor deposition process or a chemical vapor deposition process.
Optionally, the process of etching back the first initial barrier layer includes an anisotropic dry etching process or an anisotropic wet etching process.
Optionally, the process of etching back the second initial barrier layer includes an anisotropic dry etching process or an anisotropic wet etching process.
Optionally, the material of the sacrificial layer is different from the material of the first initial barrier layer, and the material of the sacrificial layer includes an organic material containing carbon and oxygen.
Optionally, the forming process of the source-drain doped layer comprises an epitaxial growth process; the process of doping the source-drain ions in the source-drain doping layer comprises an in-situ doping process.
Optionally, the method for forming the groove includes: and etching the fin part structure by taking the pseudo gate electrode structure as a mask until the top surface of the substrate is exposed, and forming the grooves in the fin part structures at two sides of the pseudo gate electrode structure.
Optionally, the dummy gate structure includes a dummy gate layer.
Optionally, the material of the dummy gate layer includes polysilicon or amorphous silicon.
Optionally, the forming method of the fin structure includes: forming a fin material film on the substrate, wherein the fin material film comprises a plurality of layers of first fin films overlapped along the normal direction of the surface of the substrate and second fin films positioned in two adjacent layers of first fin films; forming a patterning layer on the fin material film; and etching the fin material film by taking the patterned layer as a mask until the top surface of the substrate is exposed, so as to form the fin structure, wherein the fin structure comprises a plurality of first fin layers overlapped along the normal direction of the surface of the substrate and a second fin layer positioned between two adjacent first fin layers.
Optionally, the material of the first fin portion layer is different from the material of the second fin portion layer; the material of the first fin portion layer is monocrystalline silicon or monocrystalline germanium silicon; the material of the second fin portion layer is monocrystalline silicon germanium or monocrystalline silicon.
Optionally, after forming the source-drain doped layer, the method further includes: forming a dielectric layer on the source-drain doping layer and the pseudo gate structure, wherein the dielectric layer covers the side wall of the pseudo gate structure; removing the dummy gate structure and the first modified fin portion layer covered by the dummy gate structure, and forming gate openings in the dielectric layer and between adjacent second fin portion layers; and forming a gate structure in the gate opening, wherein the gate structure surrounds the second fin portion layer.
Correspondingly, the invention also provides a semiconductor structure formed by any one of the methods, which comprises the following steps: the substrate is provided with a fin structure, and the fin structure comprises a plurality of layers of first modified fin layers overlapped along the normal direction of the surface of the substrate and a second fin layer positioned between two adjacent layers of first modified fin layers; a first fin groove positioned between the first modified fin layer and the substrate, and a second fin groove positioned between two adjacent second fin layers; a dummy gate structure located on the fin structure; grooves positioned on two sides of the pseudo gate structure; the first blocking layer is positioned in the first fin portion groove, and the second blocking layer is positioned in the second fin portion groove, and the thickness of the first blocking layer is larger than that of the second blocking layer; and the source-drain doping layer is positioned in the groove, and source-drain ions are arranged in the source-drain doping layer.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the technical scheme, the first blocking layer is formed in the first fin portion groove, the second blocking layer is formed in the second fin portion groove, and the thickness of the first blocking layer is larger than that of the second blocking layer. In the subsequent process, the isolation effect between the source-drain doped layer and the formed gate structure can be effectively improved by increasing the thickness of the first barrier layer, so that the parasitic capacitance between the source-drain doped layer and the gate structure is reduced, and the performance of the finally formed semiconductor structure is improved.
In addition, the thickness of the second barrier layer is smaller, so that the purpose is to avoid that when the thickness of the second barrier layer is larger, the side wall of the groove is comb-tooth-shaped, and in the subsequent process, the source-drain doped layer is not easy to grow between the first barrier layer and the second barrier layer.
Drawings
FIGS. 1 to 3 are schematic views showing steps of a method for forming a semiconductor structure;
fig. 4 to 15 are schematic views illustrating steps of a method for forming a semiconductor structure according to an embodiment of the invention.
Detailed Description
As described in the background, the prior art forms semiconductor structures with poor performance. The following will make a detailed description with reference to the accompanying drawings.
Referring to fig. 1, a substrate 100 is provided, and the substrate 100 has a fin structure thereon, where the fin structure includes a plurality of first fin layers 101 overlapping along a normal direction of a surface of the substrate, and a second fin layer 102 located between two adjacent first fin layers 101; a dummy gate structure 103 is formed on the substrate 100 across the fin structure, the dummy gate structure 103 covering a portion of the fin structure sidewall and a portion of the top surface.
Referring to fig. 2, grooves 104 are formed in fin structures on both sides of the dummy gate structure 103; removing a part of the first fin layer 101 on the side wall of the groove 104 to form a first modified fin layer 105, a first fin groove (not labeled) and a second fin groove (not labeled), wherein the first fin groove is positioned between the first modified fin layer 105 and the substrate 100 at the bottom layer, and the second fin groove is positioned between the second fin layers 102 at two adjacent layers; a first barrier layer 106 is formed in the first fin recess and a second barrier layer 108 is formed in the second fin recess.
Referring to fig. 3, a source-drain doped layer 107 is formed in the recess 104, and source-drain ions are provided in the source-drain doped layer 107.
In the above embodiment, in a subsequent process, the first modified fin layer 105 needs to be removed to form the gate structure. However, after the gate structure is formed, due to the small thickness of the first blocking layer 106, the isolation performance is poor, which easily results in parasitic capacitance formed between the source-drain doped layer 107 and the gate structure, and thus, the performance of the finally formed semiconductor structure is poor.
On the basis, the invention provides the semiconductor structure and the forming method thereof, and the thickness of the first barrier layer is increased, so that the isolation effect between the source-drain doped layer and the gate structure can be effectively improved in the subsequent process, the parasitic capacitance between the source-drain doped layer and the gate structure is reduced, and the performance of the finally formed semiconductor structure is further improved.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
Fig. 4 to 15 are schematic structural views illustrating a process of forming a semiconductor structure according to an embodiment of the present invention.
Referring to fig. 4, a substrate 200 is provided, and the substrate 200 has a fin structure thereon, where the fin structure includes a plurality of first fin layers 201 overlapping along a normal direction of a surface of the substrate, and a second fin layer 202 located between two adjacent first fin layers 201.
The material of the substrate 200 may be monocrystalline silicon or monocrystalline germanium silicon; in this embodiment, the substrate 200 is made of monocrystalline silicon germanium.
The fin structure forming method comprises the following steps: forming a fin material film (not shown) on the substrate 200, wherein the fin material film comprises a plurality of layers of first fin films (not shown) overlapped along the normal direction of the surface of the substrate, and a second fin film (not shown) positioned in two adjacent layers of first fin films; forming a patterned layer (not shown) on the fin material film; and etching the fin material film by taking the patterned layer as a mask until the top surface of the substrate is exposed, so as to form the fin structure, wherein the fin structure comprises a plurality of layers of first fin layers 201 overlapped along the normal direction of the surface of the substrate and a second fin layer 202 positioned between two adjacent layers of the first fin layers 201.
The materials of the first fin layer 201 and the second fin layer 202 are different, so that the first fin layer 201 needs to be removed when the gate structure is formed later, and therefore, the damage to the second fin layer 202 in the process of removing the first fin layer 201 is reduced by adopting the first fin layer 201 and the second fin layer 202 with different materials and having a larger etching selection ratio.
In this embodiment, the material of the first fin portion layer 201 is monocrystalline silicon, and the material of the second fin portion layer 202 is monocrystalline silicon germanium; in other embodiments, the material of the first fin layer is monocrystalline silicon germanium, and the material of the second fin layer is monocrystalline silicon.
Referring to fig. 5, a dummy gate structure is formed on the substrate 200 across the fin structure, the dummy gate structure covering a portion of the fin structure sidewall and a portion of the top surface.
The dummy gate structure includes: the device comprises a gate dielectric layer 203 positioned on the fin structure, a dummy gate layer 204 positioned on the gate dielectric layer 203, a protection layer 205 positioned on the dummy gate layer 204, and a side wall 206 positioned on the side walls of the dummy gate layer 204 and the protection layer 205.
In this embodiment, the material of the dummy gate layer 204 is polysilicon; in other embodiments, amorphous silicon may also be used as the material of the dummy gate layer 204.
In this embodiment, the material of the protection layer 205 is silicon nitride; in other embodiments, the material of the protective layer may also be silicon oxide.
The method for forming the side wall 206 includes: forming a sidewall material layer (not shown) on the top surface of the gate dielectric layer 203, the sidewall of the dummy gate layer 204, and the sidewall and top surface of the protection layer 205; and etching the side wall material layer until the top surfaces of the protective layer 205 and the gate dielectric layer 203 are exposed, thereby forming the side wall 206.
The forming process of the side wall material layer is one or a combination of a plurality of chemical vapor deposition processes, physical vapor deposition processes or atomic layer deposition processes. The material of the sidewall 206 includes silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride.
In this embodiment, the sidewall 206 is used to define the position of the subsequent source-drain doped layer.
Referring to fig. 6, grooves 207 are formed in the fin structures on both sides of the dummy gate structure.
The method for forming the groove 207 includes: and etching the fin structures by taking the pseudo gate structures as masks until the top surfaces of the substrates 200 are exposed, and forming grooves 207 in the fin structures at two sides of the pseudo gate structures.
In this embodiment, the recess 207 is used to provide a space for the source-drain doped layer to be formed later.
The process for etching the fin structure comprises the following steps: an anisotropic dry etching process or an anisotropic wet etching process.
In this embodiment, the process of etching the fin structure is an anisotropic dry etching process, and parameters of the dry etching process include: the etching gas comprises HBr and Ar, wherein the flow rate of the HBr is 10 sccm-1000 sccm, and the flow rate of the Ar is 10 sccm-1000 sccm.
Referring to fig. 7, a portion of the first fin layer 201 on the sidewall of the recess 207 is removed, and a first modified fin layer 208, a first fin recess 209 and a second fin recess 210 are formed, where the first fin recess 209 is located between the first modified fin layer 208 and the substrate 200, and the second fin recess 210 is located between the second fin layers 202 of two adjacent layers.
In this embodiment, the first fin recess 209 is used to provide space for a subsequently formed first barrier layer, and the second fin recess 210 is used to provide space for a subsequently formed second barrier layer.
In this embodiment, the process of removing a portion of the first fin layer 201 is a wet etching process. The etching liquid for wet etching has a good selection ratio to monocrystalline silicon and monocrystalline germanium silicon, and can ensure that the morphology of the monocrystalline germanium silicon is not influenced while the monocrystalline silicon is removed. The parameters of the wet etching process include: the etching solution is a tetramethyl ammonium hydroxide solution, the temperature is 20-80 ℃, and the volume percentage of the tetramethyl ammonium hydroxide solution is 10-80%.
After forming the first fin recess 209 and the second fin recess 210, a first barrier layer within the first fin recess 209 and a second barrier layer within the second fin recess 210 are formed, the first barrier layer having a thickness greater than a thickness of the second barrier layer. The specific process of forming the first barrier layer and the second barrier layer is shown in fig. 8 to 11.
Referring to fig. 8, a first initial barrier layer 211 is formed on the sidewalls and bottom surface of the recess 207 and the sidewalls and top surface of the dummy gate structure.
In this embodiment, the material of the first initial blocking layer 211 is silicon nitride.
In this embodiment, the first initial barrier layer 211 is formed by a physical vapor deposition process; in other embodiments, the first initial barrier layer may be formed by a chemical vapor deposition process.
Referring to fig. 9, the first initial barrier layer 211 is etched back until the bottom surface of the recess 207 and the top surface of the dummy gate structure are exposed, so as to form a second initial barrier layer 212.
The process of etching back the first initial barrier layer 211 includes anisotropyA dry etching process or an anisotropic wet etching process; in this embodiment, the process of etching back the first initial barrier layer 211 adopts an anisotropic dry etching process, and the parameters of the anisotropic dry etching process include: the etching gas includes CF 4 And CH (CH) 2 F 2 Wherein CF is 4 The flow rate of (C) is 50 sccm-500 sccm, CH 2 F 2 The flow rate of the water is 30sccm to 100sccm.
Referring to fig. 10, a sacrificial layer 213 is formed at the bottom of the recess 207, the sacrificial layer 213 covers a portion of the sidewall of the second initial barrier layer 212, and the top surface of the sacrificial layer 213 is lower than or flush with the top surface of the first fin layer 208 at the bottom.
The sacrificial layer 213 covers a portion of the sidewall of the second initial barrier layer 212, and is used to prevent the second initial barrier layer 212 from being etched when the second initial barrier layer 212 is etched back later, so as to ensure that the thickness of the first barrier layer formed later is larger.
The material of the sacrificial layer 213 is different from that of the first initial barrier layer 211, and since the second initial barrier layer 212 is formed by the first initial barrier layer 211, the material of the second initial barrier layer 212 is the same as that of the first initial barrier layer 211. A certain etching selectivity ratio is generated between the sacrificial layer 213 and the second initial barrier layer 212 through the difference of materials, so that the sacrificial layer 213 is ensured not to be removed by etching when the second initial barrier layer 212 is etched later.
In this embodiment, the material of the sacrificial layer 213 is an organic material containing carbon and oxygen.
Referring to fig. 11, the second initial barrier layer 212 is etched back until the sidewalls of the second fin layer 202 are exposed, so as to form the first barrier layer 214 and the second barrier layer 215; after the first barrier layer 214 and the second barrier layer 215 are formed, the sacrificial layer 213 is removed.
The process of etching back the second initial barrier layer 212 includes an anisotropic dry etching process or anisotropic etching processA wet etching process; in this embodiment, the process of etching back the second initial barrier layer 212 adopts an anisotropic dry etching process, and the parameters of the anisotropic dry etching process include: using fluorine-containing gases (e.g. CH 3 F、CH 2 F 2 Or CHF 3 ) The etching power is 200W-400W, the etching cavity pressure is 30-200 mtorr, and the etching temperature is 40-60 ℃.
The thickness of the first barrier layer 214 after formation is greater than the thickness of the second barrier layer 215, and the direction of the thickness is perpendicular to the sidewall of the first barrier layer 214, so as to increase the thickness of the first barrier layer 214. In the subsequent process, the isolation effect between the source-drain doped layer and the formed gate structure can be effectively improved by increasing the thickness of the first barrier layer 214, so that the parasitic capacitance between the source-drain doped layer and the gate structure is reduced, and the performance of the finally formed semiconductor structure is further improved.
In addition, the thickness of the second barrier layer 215 is smaller, so as to avoid that the sidewall of the groove 207 is comb-shaped when the thickness of the second barrier layer 215 is larger, and the source-drain doped layer is not easy to grow between the first barrier layer and the second barrier layer in the subsequent process.
Referring to fig. 12, after the first barrier layer 214 and the second barrier layer 215 are formed, a source-drain doped layer 216 is formed in the recess 207, and source-drain ions are contained in the source-drain doped layer 216.
In this embodiment, the forming process of the source-drain doped layer 216 includes an epitaxial growth process; the process of doping the source drain ions within the source drain doped layer 216 includes an in-situ doping process.
When the semiconductor structure is a P-type device, the material of the source-drain doped layer 216 includes: silicon, germanium or silicon germanium; the source-drain ions are P-type ions, and comprise boron ions and BF 2- Ions or indium ions; when the semiconductor structure is an N-type device, the materials of the source-drain doped layer 216 include: silicon, gallium arsenide or indium gallium arsenide; the saidThe source and drain ions are N-type ions, and the source and drain ions comprise phosphorus ions or arsenic ions.
In this embodiment, the semiconductor structure is an N-type device, the material of the source-drain doped layer 216 is silicon, and the source-drain ions are phosphorus ions.
After forming the source-drain doped layer 216, forming a dielectric layer on the source-drain doped layer 216 and the dummy gate structure, wherein the dielectric layer covers the sidewalls of the dummy gate structure; removing the dummy gate structure and the first modified fin layer 208 covered by the dummy gate structure, and forming gate openings in the dielectric layer and between adjacent second fin layers 202; a gate structure is formed within the gate opening, the gate structure surrounding the second fin layer 202. The specific process of forming the gate structure is shown in fig. 13 to 15.
Referring to fig. 13, a dielectric layer 217 is formed on the source-drain doped layer 216 and the dummy gate structure, and the dielectric layer 217 covers the sidewalls of the dummy gate structure.
In this embodiment, the dielectric layer 217 specifically covers the source-drain doped layer 216 and the sidewalls of the dummy gate structure, exposing the top surface of the dummy gate structure.
The method for forming the dielectric layer 217 includes: forming an initial dielectric layer (not shown) on the source-drain doped layer 216 and the dummy gate structure, wherein the initial dielectric layer covers the top surface and the side wall surface of the dummy gate structure; and flattening the initial dielectric layer until the surface of the protection layer 205 at the top of the pseudo gate structure is exposed, and forming the dielectric layer 217.
In this embodiment, the material of the dielectric layer 217 is silicon oxide.
Referring to fig. 14, the dummy gate structure and the first modified fin layer 208 covered by the dummy gate structure are removed, and a gate opening 218 is formed in the dielectric layer 217 and between adjacent second fin layers 202.
The method of removing the dummy gate structure and the first modified fin layer 208 covered by the dummy gate structure includes: removing the dummy gate layer 204 and forming an initial gate opening (not shown) in the dielectric layer 217; the first modified fin layer 208 exposed by the initial gate opening is removed, such that the initial gate opening forms the gate opening 218.
Specifically, the removal of the protection layer 205 on top of the dummy gate layer 214 is also included before the removal of the dummy gate layer 214.
In this embodiment, the process of removing the first fin layer 208 uses a wet etching process.
Referring to fig. 15, a gate structure 219 is formed in the gate opening 218, and the gate structure 219 surrounds the second fin layer 202.
The gate structure 219 includes a gate electrode layer of a metal material including one or more of copper, tungsten, nickel, chromium, titanium, tantalum, and aluminum.
In this embodiment, copper is used as the material of the gate layer.
Accordingly, in an embodiment of the present invention, there is further provided a semiconductor structure formed by the above method, with continued reference to fig. 12, the semiconductor structure includes: the substrate 200 is provided with a fin structure, wherein the fin structure comprises a plurality of first modified fin layers 208 overlapped along the normal direction of the surface of the substrate, and a second fin layer 202 positioned between two adjacent first modified fin layers 208; a first fin recess between the first modified fin layer 208 and the substrate 200, and a second fin recess between two adjacent layers of the second fin layer 202; a dummy gate structure located on the fin structure; grooves positioned on two sides of the pseudo gate structure; a first barrier layer 214 located within the first fin recess, and a second barrier layer 215 located within the second fin recess 210, the first barrier layer 214 having a thickness greater than a thickness of the second barrier layer 215; the source-drain doped layer 216 is located in the groove 207, and source-drain ions are located in the source-drain doped layer 216.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (14)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a fin structure, and the fin structure comprises a plurality of layers of first fin layers overlapped along the normal direction of the surface of the substrate and a second fin layer positioned between two adjacent layers of first fin layers;
forming a dummy gate structure on the substrate, wherein the dummy gate structure spans the fin structure and covers part of the side wall and part of the top surface of the fin structure;
forming grooves in fin structures on two sides of the pseudo gate structure;
removing part of the first fin portion layer on the side wall of the groove to form a first modified fin portion layer, a first fin portion groove and a second fin portion groove, wherein the first fin portion groove is positioned between the first modified fin portion layer on the bottom layer and the substrate, and the second fin portion groove is positioned between the second fin portion layers on two adjacent layers;
forming a first blocking layer positioned in the first fin portion groove and a second blocking layer positioned in the second fin portion groove, wherein the thickness of the first blocking layer is larger than that of the second blocking layer, and the direction of the thickness is perpendicular to the side wall of the first blocking layer;
after the first barrier layer and the second barrier layer are formed, a source-drain doping layer is formed in the groove, and source-drain ions are arranged in the source-drain doping layer;
the method for forming the first barrier layer and the second barrier layer comprises the following steps: forming a first initial barrier layer on the side wall and the bottom surface of the groove and the side wall and the top surface of the pseudo gate structure; etching back the first initial barrier layer until the bottom surface of the groove and the top surface of the pseudo gate structure are exposed, and forming a second initial barrier layer; forming a sacrificial layer at the bottom of the groove, wherein the sacrificial layer covers part of the side wall of the second initial blocking layer, and the top surface of the sacrificial layer is lower than or flush with the top surface of the first modified fin layer positioned at the bottom layer; etching back the second initial barrier layer until the side wall of the second fin portion layer is exposed, and forming the first barrier layer and the second barrier layer; after forming the first barrier layer and the second barrier layer, the sacrificial layer is removed.
2. The method of claim 1, wherein the material of the first initial barrier layer comprises silicon nitride.
3. The method of claim 1, wherein forming the first initial barrier layer comprises a physical vapor deposition process or a chemical vapor deposition process.
4. The method of claim 1, wherein the process of etching back the first initial barrier layer comprises an anisotropic dry etch process or an anisotropic wet etch process.
5. The method of claim 1, wherein the process of etching back the second initial barrier layer comprises an anisotropic dry etch process or an anisotropic wet etch process.
6. The method of claim 1, wherein a material of the sacrificial layer is different from a material of the first initial barrier layer, the material of the sacrificial layer comprising an organic material comprising a carbon-oxygen element.
7. The method of claim 1, wherein the forming of the source-drain doped layer comprises an epitaxial growth process; the process of doping the source-drain ions in the source-drain doping layer comprises an in-situ doping process.
8. The method of forming a semiconductor structure of claim 1, wherein the method of forming the recess comprises: and etching the fin part structure by taking the pseudo gate electrode structure as a mask until the top surface of the substrate is exposed, and forming the grooves in the fin part structures at two sides of the pseudo gate electrode structure.
9. The method of claim 1, wherein the dummy gate structure comprises a dummy gate layer.
10. The method of claim 9, wherein the material of the dummy gate layer comprises polysilicon or amorphous silicon.
11. The method of claim 1, wherein the forming the fin structure comprises: forming a fin material film on the substrate, wherein the fin material film comprises a plurality of layers of first fin films overlapped along the normal direction of the surface of the substrate and second fin films positioned in two adjacent layers of first fin films; forming a patterning layer on the fin material film; and etching the fin material film by taking the patterned layer as a mask until the top surface of the substrate is exposed, so as to form the fin structure, wherein the fin structure comprises a plurality of first fin layers overlapped along the normal direction of the surface of the substrate and a second fin layer positioned between two adjacent first fin layers.
12. The method of claim 1, wherein a material of the first fin layer and a material of the second fin layer are different; the material of the first fin portion layer is monocrystalline silicon or monocrystalline germanium silicon; the material of the second fin portion layer is monocrystalline silicon germanium or monocrystalline silicon.
13. The method of claim 1, wherein after forming the source drain doped layer, further comprising: forming a dielectric layer on the source-drain doping layer and the pseudo gate structure, wherein the dielectric layer covers the side wall of the pseudo gate structure; removing the dummy gate structure and the first modified fin portion layer covered by the dummy gate structure, and forming gate openings in the dielectric layer and between adjacent second fin portion layers; and forming a gate structure in the gate opening, wherein the gate structure surrounds the second fin portion layer.
14. A semiconductor structure formed by the method of any of claims 1 to 13, comprising:
the substrate is provided with a fin structure, and the fin structure comprises a plurality of layers of first modified fin layers overlapped along the normal direction of the surface of the substrate and a second fin layer positioned between two adjacent layers of first modified fin layers;
a first fin groove positioned between the first modified fin layer and the substrate, and a second fin groove positioned between two adjacent second fin layers;
a dummy gate structure located on the fin structure;
grooves positioned on two sides of the pseudo gate structure;
the first blocking layer is positioned in the first fin portion groove, and the second blocking layer is positioned in the second fin portion groove, the thickness of the first blocking layer is larger than that of the second blocking layer, and the direction of the thickness is perpendicular to the side wall of the first blocking layer;
and the source-drain doping layer is positioned in the groove, and source-drain ions are arranged in the source-drain doping layer.
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