CN112882400B

CN112882400B - Driving multiple I's simultaneously 2 Method for C slave device and chip driven by controller simultaneously

Info

Publication number: CN112882400B
Application number: CN202110037625.5A
Authority: CN
Inventors: 闵丙日
Original assignee: Hangzhou Xinge Microelectronics Co ltd
Current assignee: Hangzhou Xinge Microelectronics Co ltd
Priority date: 2021-01-12
Filing date: 2021-01-12
Publication date: 2022-10-25
Anticipated expiration: 2041-01-12
Also published as: CN112882400A

Abstract

The invention relates to driving a plurality of I's simultaneously ² A method of a slave device and a chip simultaneously driven by a controller. In the process of the invention, by I ² The communication mode C is that a controller connected with the two chips drives the two chips simultaneously, and the method comprises the following steps: if the controller sets one of the two chips as a master chip, the master chip outputs a driving wait signal to an enable input output pad of the master chip side, if the controller sets the other of the two chips as a slave chip, the slave chip receives the driving wait signal from the master chip through the slave chip side input output pad, if the controller transmits a driving start command to the master chip, the master chip outputs a driving start signal to the enable input output pad of the master chip side, and if the slave chip receives the driving start signal from the enable input output pad of the chip side, the slave chip can start driving. The process can be carried out by ² C to drive multiple sensors simultaneously.

Description

Driving multiple I's simultaneously 2 Method for C slave device and chip driven by controller simultaneously

Technical Field

The invention relates to the field of chip driving, in particular to a method for simultaneously driving multiple I chips ² Method of C slave and pass I ² And C, a chip driven by the controller simultaneously in a communication mode.

Background

The off-screen sensor is used not only for portable electronic devices such as mobile phones or tablet computers, but also for image electronic devices such as televisions or monitors. Recently, designs in which displays occupy almost the entire front face of electronic devices are increasing. Although the size of the display increases according to the demand for a large screen, at least a part of the area of the front surface must be reserved in order to place the camera, particularly the illuminance sensor. A proximity sensor using ultrasonic waves or the like can be applied to a structure covered with a display on the front, but it is difficult to integrate an illuminance detection function. On the other hand, the illuminance sensor may be located in an area other than the front surface, but may not detect ambient light due to a case for protecting the electronic device. Therefore, the most ideal position where the illuminance sensor can be mounted is the front face of the electronic apparatus, but in a design in which the display occupies the entire front face, it is difficult to ensure a position where a commonly used illuminance sensor is placed.

On the other hand, centered around portable electronic devices such as cell phones and tablet computers, the types and number of electronic devices equipped with fingerprint sensors are increasing. In order to mount the fingerprint sensor on the front surface of the electronic device, a sensing portion of the fingerprint sensor, which is in contact with the fingerprint, must be exposed to the outside. Therefore, in the case where the entire front surface of the electronic device is covered with a protective medium such as a cover glass or a transparent film in order to design or protect the display panel, it is difficult to mount a fingerprint sensor in a capacitive manner such as detecting a change in capacitance on the front surface of the electronic device. Also, it is difficult to locate the fingerprint sensor at the lower portion of the display panel.

In the case where an illuminance sensor or a fingerprint sensor (hereinafter, collectively referred to as a sensor) is disposed below the display, light generated from the display acts as noise that interferes with accurate measurement. In order to eliminate the influence of such noise, sensors having the same function must be arranged at two or more positions. In electronic equipment, semiconductor devices of a plurality of sensors or the like are controlled by serial communication, e.g. I ² And C, communication. I is ² C is a plurality of slave devices and a master device through a data line SDA _ I ² C and a clock line SCL _ I ² C, the mode of communication. In I ² In C communication, only one slave device can be operated at a time under the control of the master device. The sensor located at the lower portion of the display may be affected by the display varying even within several microseconds to several tens of microseconds. Therefore, in the case where the operating time differs between the sensors, it cannot be said that the detection value output by each sensor is affected equally by the display.

Disclosure of Invention

Technical problem to be solved

The invention provides compounds capable of passing through I ² C scheme of communicating to drive a plurality of sensors at the same time.

Means for solving the problems

According to an embodiment of the present invention, there is provided the method of ² And C, a method for driving the two chips simultaneously by a controller connected with the two chips in a communication mode. In the process of the invention, e.g.If the controller sets one of the two chips as a master chip, the master chip outputs a driving wait signal to an enable input/output pad of the master chip side, if the controller sets the other of the two chips as a slave chip, the slave chip receives the driving wait signal from the master chip through the slave chip side input/output pad, if the controller transmits a driving start command to the master chip, the master chip outputs a driving start signal to an enable input/output pad of the master chip side, and if the driving start signal is received through the enable input/output pad of the slave chip side, the slave chip can start driving.

As an embodiment, in the method of the present invention, if the controller sets one of the two chips as a clock master, the clock master outputs a driving clock to a clock input/output pad on the clock master side, and if the controller sets the other of the two chips as a clock slave, the clock slave may receive the driving clock from the clock master through the clock input/output pad on the clock slave side.

As an embodiment, in the method of the present invention, if the controller transmits the driving start command to the slave chip, the slave chip may wait until the driving start signal is received through an enable input output pad of the slave device side.

For one embodiment, the number of the slave chips may be plural.

According to another embodiment of the present invention, there is provided the compound represented by formula I ² C communication method of driving two chips at the same time by a controller connected to the two chips. In the method of the present invention, if the controller sets one of the two chips as a master chip and the other chip as a slave chip, the master chip monitors data received and transmitted through a data line between the slave chip and the controller, and if the controller transmits a driving start command to the slave chip, the master chip monitors data received and transmitted through a data line between the slave chip and the controllerThe master chip may start driving.

As an embodiment, the driving start command includes: a chip address for identifying the slave chip; a register address for storing a register value indicating the start of driving; the register value, the slave chip may transmit a reply signal to the controller whenever the reception of the chip address, the register address, and the register value is completed.

As an embodiment, in the monitoring, the master chip stores a chip address of the slave chip provided by the controller, captures a chip address received and transmitted through the data line to compare with the stored chip address, captures a register address transmitted to the slave chip if the captured chip address is the same as the stored chip address to compare whether the captured register address is a register address for storing a register value indicating the start of driving, and the master chip does not transmit a response signal to the controller even if the captured chip address is the same as the stored chip address.

As an embodiment, the master chip may start driving if the register address captured is a register address for storing a register value indicating the start of driving.

As an embodiment, the master chip captures a register value transferred to the slave chip if the captured register address is a register address for storing a register value indicating the start of driving, and may start driving if the captured register value is a register value indicating the start of driving.

As an embodiment, if the controller transmits the driving start command to the master chip, the master chip may wait until the slave chip starts driving.

As an embodiment, in the method of the present invention, if the controller sets one of the two chips as a clock master, the clock master outputs a driving clock to a clock input/output pad of a clock master side, and if the controller sets the other of the two chips as a clock slave, the clock slave may receive the driving clock from the clock master through a clock input/output pad of a clock slave side.

In one embodiment, the number of the main chips may be plural.

According to yet another embodiment of the present invention, there is provided the compound represented by formula I ² C communication mode is chip driven by controller at the same time, multiple chips pass through I ² And when the communication mode C is connected with the controller, the communication mode C is driven simultaneously by the control of the controller. The chip of the invention may comprise: enabling the input and output pad; I.C. A ² A C communication unit which receives a first register value for storing one of the master chip and the slave chip and a second register value indicating the start of driving from the controller via a data line; a register and/or memory for storing the first register value at a first register address and the second register value at a second register address; and a peripheral circuit outputting a driving standby signal to the enable input/output pad if the main chip is set by the first register value, and outputting a driving start signal to the enable input/output pad by the second register value.

As an embodiment, if the slave chip is set by the first register value, the peripheral circuit may receive the driving wait signal through the enable input output pad, and if the driving start signal is received through the enable input output pad, the peripheral circuit may start driving.

As an embodiment, the chip may further include a clock input/output pad, and if set as a clock master by the controller, a pass I ² C, the other chip connected in a communication mode provides a driving clock, and if the driving clock is set as a clock slave device, the driving clock is received from one of the other chips or from the outside.

As an embodiment, the chip may further include a clock generator for generating the driving clock output through the clock input output pad.

As an embodiment, the chip may further include a cell region, and the driving is controlled by the peripheral circuit to generate a pixel current corresponding to the intensity of the incident light.

In one embodiment, the chip is disposed below the display, and may be disposed below the first light selection layer, through which external light incident on the photovoltaic cell region and light generated by the display pass.

In one embodiment, the chip may be disposed at a lower portion of a second light selection layer through which the external light and a portion of the light generated by the display pass.

In one embodiment, the chip disposed under the first light selective layer and the chip disposed under the second light selective layer start driving at the same driving start time and end driving at the same driving end time.

According to yet another embodiment of the present invention, there is provided the compound represented by formula I ² C communication mode is chip driven by controller at the same time, multiple chips pass through I ² And C, when the communication mode is connected with the controller, the driving is simultaneously carried out by the control of the controller. The chip may include: i is ² A C communication section receiving a register value for specifying one of a master chip and a slave chip from the controller through a data line through which a start of driving of the slave chip is monitored; a register and/or memory for storing the register values; and a peripheral circuit which starts driving if the slave chip in monitoring starts driving by setting the register value to the master chip.

As an embodiment, if the master chip is set by the register value, the I ² The C communication part stores a chip address of the slave chip provided by the controller, captures a chip address received and transmitted through the data line to compare with the stored chip address, and if the captured chip address is the same as the stored chip address, captures a register address transmitted to the slave chip to compare whether the captured register address is usedIn storing a register address of a register value indicating the start of driving, the master chip does not transmit a response signal to the controller even if the captured chip address is the same as the stored chip address.

As an embodiment, the peripheral circuit may start driving if the register address captured is a register address for storing a signal indicating the start of driving.

As an embodiment, if the register address captured is a register address for storing a register value indicating the start of the driving, the I ² The C communication section captures a register value transferred to the slave chip, and the peripheral circuit may start driving if the captured register value is a register value indicating the start of driving.

As an embodiment, if the controller transmits a driving start command, the peripheral circuit may wait until the slave chip drives start.

As an embodiment, the chip may be disposed at a lower portion of the second light selection layer through which the external light and a portion of the light generated by the display pass.

In one embodiment, the chip disposed under the first light selective layer and the chip disposed under the second light selective layer start driving at the same driving start time, and may end driving at the same driving end time.

Effects of the invention

According to an embodiment of the invention, can be represented by ² C to drive multiple sensors simultaneously.

Drawings

The present invention will be described below with reference to embodiments shown in the drawings. To facilitate understanding, identical reference numerals have been given to identical structural elements throughout the figures. The structures shown in the drawings are intended to illustrate exemplary embodiments of the present invention and not to limit the scope of the present invention. In particular, some of the components in the drawings are illustrated in an exaggerated form in order to facilitate understanding of the present invention. The drawings are means for understanding the present invention, and it should be understood that the widths, thicknesses, and the like of the structural elements in the drawings may be different from those in actual embodiments.

Fig. 1 (a) and 1 (b) are views for illustrating the structure of a sensor that requires simultaneous driving, respectively.

Fig. 2 (a) to 2 (e) are views for exemplarily illustrating cross sections of the AA and BB sensors according to fig. 1, respectively.

Fig. 3 (a) and 3 (b) are views for exemplarily illustrating a structure for simultaneously driving a plurality of chips, respectively.

Fig. 4 is a diagram for exemplifying a method of simultaneously driving a plurality of chips in the structure shown in fig. 3.

Fig. 5 is a diagram for exemplary explanation of another method of simultaneously driving a plurality of chips in the structure shown in fig. 3.

Fig. 6 (a) and 6 (b) are diagrams for exemplarily illustrating a structure for simultaneously driving a plurality of chips, respectively.

Fig. 7 is a diagram for exemplifying a method of simultaneously driving a plurality of chips in the structure shown in fig. 3.

Fig. 8 is a diagram for illustrating an operation principle of the sensor.

Fig. 9 (a) and 9 (b) are diagrams for exemplarily illustrating an embodiment of a sensor having a first light selection layer, respectively.

Fig. 10 (a) and 10 (b) are diagrams for exemplarily illustrating an embodiment of a sensor having a second light selection layer, respectively.

Wherein the drawings are described as follows:

10. a display; 11. a display polarizing layer; 12. a display retarder layer; 13. a pixel layer; 20. external light; 21. linearly polarized light of the display; 22. display circular polarized light; 22a, linearly polarized light inside the first sensor; 22a', second sensor internal linearly polarized light; 23. a first sensor linearly polarized light; 23', first sensor linearly polarized light; 24. a second sensor linearly polarized light; 30. unpolarized light; 31. a third sensor linearly polarized light; 31', third sensor linearly polarized light; 24', a second sensor linearly polarized light; 32. a fourth sensor linearly polarized light; 32', a fourth sensor linearly polarized light; 100. a sensor of a first modality; 100a, a first sensor; 100b, a first sensor; 100c, a second sensor; 100d, a second sensor; 100e, a first sensor; 101a, a sensor of a second form; 101b, a sensor of a second form; 110. packaging; 110a, packaging; 111a, through holes; 111b, through holes; 120a, a first chip; 120b, a second chip; 120a', a master chip; 120b', a slave chip; 121a, a first light receiving part; 121b, a second light receiving part; 121. i is ² A communication unit (C); 121' and I ² A communication unit (C); 122. registers and/or memory; 123. a peripheral circuit; 124. a clock generator; 125. a photo cell area; 130. a first light selective layer; 130', a first light selective layer; 140. a second light selective layer; 140', a second light selective layer; 150. a controller; 310. a first sensor polarization layer; 315. a second sensor polarization layer; 320. a first sensor retarder layer; 325. a second sensor retarder layer.

Detailed Description

Since the present invention can be modified in various ways and can have various embodiments, specific embodiments will be illustrated in the drawings and described in detail. However, it should be understood that the present invention is not limited to the specific embodiments, and the present invention includes all modifications, equivalents, and alternatives included in the spirit and technical scope of the present invention. In particular, the functions, features, embodiments described below with reference to the drawings can be implemented alone or in combination with other embodiments. Therefore, it should be noted that the scope of the present invention is not limited by the form shown in the drawings.

On the other hand, in terms used in the present specification, expressions such as "substantially", "almost", "about" and the like are expressions considering a margin applied at the time of actual implementation or a possible error. For example, "substantially 90 degrees" should be interpreted to include angles at which the desired effect may be the same as the effect at 90 degrees. As another example, "almost free" should be interpreted to include something that is trivial to the extent that it can be ignored.

On the other hand, unless specifically mentioned otherwise, "side" or "horizontal" relates to the left-right direction of the drawing, and "vertical" relates to the up-down direction of the drawing. Also, unless otherwise specifically defined, the angle, the incident angle, and the like are based on a virtual straight line perpendicular to the horizontal plane shown in the drawings.

Throughout the drawings, the same or similar reference numbers refer to the same or similar elements.

Hereinafter, in the entire drawings, hatching illustrated in the retarder layer indicates the direction of the slow axis, and hatching illustrated in the polarizing layer exemplarily indicates the direction of the polarization axis with respect to the slow axis extending in the horizontal direction. On the other hand, the slow axis of the display retarder layer and the slow axis of the sensor retarder layer both extend in a horizontal direction, or the slow axis of the display retarder layer and the slow axis of the sensor retarder layer both extend in a vertical direction, as shown. It should be understood that this is presented purely to aid understanding and that there is no need to align the slow axis of the sensor retarder layer with the slow axis of the display retarder layer.

Fig. 1 is a diagram for exemplifying a structure of a sensor that needs to be driven simultaneously.

Simultaneous driving is required in a semiconductor device which operates in an environment where an object to be detected is affected by time-varying noise. In this specification, it is assumed that the semiconductor devices that need to be driven simultaneously are sensors such as an illuminance sensor, a color sensor, a fingerprint sensor, and the like, which are disposed below the display. The sensor located under the display detects not only a detection target (e.g., extraneous light or light generated from the display reflected from the cover glass) but also noise (light incident from the display). Therefore, since the detection value is influenced not only by the external light but also by the light generated from the display (hereinafter, referred to as internal light), a plurality of sensors are arranged below the display in order to measure the intensity of clean external light, and in particular, it is necessary to drive the plurality of sensors simultaneously. The intensity of the internal light may vary within several microseconds to several tens of microseconds, compared to the relatively constant external light. Therefore, even if a plurality of sensors are used, if the sensors are driven for different times, the measurement values of the respective sensors are different, and therefore, the noise component generated by the internal light cannot be removed from the measurement values. Of course, the simultaneous driving method proposed in the present specification can be applied not only to the sensor but also to the support I ² C other types of semiconductor devices for communication.

Referring to fig. 1 (a) and 1 (b), the plurality of sensors may be embodied by various structures. The sensor 100 of the first modality includes a plurality of first chips 120a and second chips 120b within one package 110. The sensor 101a of the second form comprises a first chip 120a within a package 110 a. The package 110 of the sensor 100 according to the first embodiment includes a plurality of through

holes

111a and 111b for exposing the first chip 120a and the second chip 120b to the outside. The package 110a of the sensor 101a of the second embodiment includes one through hole 111a for exposing the first chip 120a to the outside.

Basically, the first chip 120a and the second chip 120b may generally have a function for measuring the intensity of incident light, as in the case of a semiconductor having an illuminance detection function. However, characteristics of light incident to the respective first and

second chips

120a and 120b may be different, which will be described in detail with reference to fig. 8 to 10. As an example, in the sensor 100 of the first aspect, the first chip 120a and the second chip 120b both receive the external light and the internal light, but the first chip 120a receives the external light and the internal light (light passing through the first optical path) without loss, and the second chip 120b receives the external light and the internal light (light passing through the second optical path) with intensity proportional to the intensity of the light received by the first chip 120a. Similarly, in the second form of the sensor 101a and the second form of the sensor 101b, the first chip 120a of the second form of the sensor 101a receives external light and internal light without loss, and the second chip 120b of the second form of the sensor 101b receives external light and internal light having intensity proportional to the intensity of light received by the first chip 120a.

In the sensor 100 of the first embodiment, the sensor 101a of the second embodiment, and the sensor 101b of the second embodiment, the driving of the first chip 120a and the driving of the second chip 120b are substantially synchronized. That is, the driving start time and the driving end time of the first chip 120a and the second chip 120b are substantially the same. This is because the first chip 120a and the second chip 120b can remove the influence of the internal light from the detection value only if they receive the same internal light.

The sensor 100 of the first aspect, the sensor 101a of the second aspect, and the sensor 101b of the second aspect are substantially the same sensor, except that the first optical path and the second optical path are implemented in one package or different packages. Therefore, the following description will be centered on the sensor 100 of the first aspect.

Fig. 2 is a diagram for exemplarily illustrating a cross section of the sensor according to AA and BB of fig. 1. Fig. 2 (a), (b), and 2 (e) show cross-sectional structures for receiving light passing through a first optical path, and fig. 2 (c) and 2 (d) show cross-sectional structures for receiving light passing through a second optical path.

Referring to part (a) of fig. 2, the first sensor 100a includes a package 110, a first light selective layer 130, and a first chip 120a. The first light selective layer 130 forms a first light path and may be disposed on the upper surface of the first chip 120a. The first light selective layer 130 covers at least a photovoltaic cell region (photovoltaic cell region) of the first chip 120a. The first light selection layer 130 and the photocell region may receive external light and/or internal light incident to the display through the through holes 111a.

Referring to part (b) of fig. 2, the first sensor 100b includes a package 110, a first light selective layer 130' and a first chip 120a. The first light selective layer 130' forms a first light path and may be disposed on an upper face of the package 110. Wherein the first light selective layer 130' covers at least the through hole 111a.

Referring to part (c) of fig. 2, the second sensor 100c includes a package 110, a second light selection layer 140, and a second chip 120b. The second light selective layer 140 forms a second light path and may be disposed on the upper surface of the second chip 120b. Wherein the second light selective layer 140 covers at least the photovoltaic cell area of the second chip 120b. The second light selection layer 140 and the photocell region can receive external light and/or internal light incident to the display through the through holes 111b.

Referring to part (d) of fig. 2, the second sensor 100d includes a package 110, a second light selection layer 140', and a second chip 120b. The second light selective layer 140' forms a second light path and may be disposed on an upper face of the package 110. Wherein the second light selective layer 140' covers at least the through hole 111b.

Referring to fig. 2 (e), the first sensor 100e includes a package 110 and a first chip 120a. As described above, the first chip 120a and the second chip 120b can remove the influence of the internal light by using the difference between the detection values of the external light and the internal light received in the same driving time. Therefore, if there is only a proportional relationship between the detection values of the first chip 120a of the first sensor 100e and the second chips 120b of the second sensor 100c and the second sensor 100d, the first sensor 100e may be used even if the first light selection layer 130 or the first light selection layer 130' is not included.

The first light selective layer 130 provides the same function as the first light selective layer 130', i.e. provides a first light path, but its structure may be different, and the second light selective layer 140 provides a second light path with the second light selective layer 140', but may have a different structure. The structure of the first light selective layer 130, the first light selective layer 130', the second light selective layer 140 and the second light selective layer 140' will be described with reference to fig. 8 to 10. The example shown in fig. 2 is only used to illustrate that the first light selective layer 130, the first light selective layer 130', the second light selective layer 140, and the second light selective layer 140' can be disposed at a plurality of positions, and the specific structure is not limited to be disposed at a specific position.

Fig. 3 is a diagram for exemplarily illustrating a structure for simultaneously driving a plurality of chips. Fig. 3 (a) partially shows two chips and a controller that simultaneously drives them, and fig. 3 (b) partially shows a functional structure of the chips.

Referring to part (a) of fig. 3, two chips are set to a master mode and a slave mode, and a first chip 120a (hereinafter, referred to as a "master chip") set to the master mode supplies a driving start signal Enable (Enable) necessary for simultaneous driving start to a second chip 120b (hereinafter, referred to as a "slave chip") set to the slave mode. On the other hand, one of the two chips can supply a driving Clock (Clock) required for simultaneous driving termination to the remaining chips.

The simultaneous driving means that the driving start timing and the driving end timing are the same. In order to make the driving start time the same, one of the chips must be able to notify the remaining chips of the driving start, and in order to make the driving end time the same, the chips must be driven by the same driving clock. For this, the first chip 120a and the second chip 120b include enable input/output pads (enable input/output pads) for input/output driving start signal enable and clock input/output pads for input/output driving clocks, in addition to pads for inputting or outputting basic driving control required signals. Additionally or alternatively, the first chip 120a and the second chip 120b may further include one or more option pads for determining a master device mode or a slave device mode. If the option pads are used, the operation mode of each chip can be determined in advance.

Among them, a pad or a contact (hereinafter, collectively referred to as "pad") is a metal layer or a terminal formed on an upper surface or a lower surface of a chip. The pad is electrically connected to a lead frame, a Printed Circuit Board (PCB), or the like by various means such as a wire and a solder ball, and receives or transmits a signal from or to the outside through the lead frame. For example, in the case where a plurality of first and

second chips

120a and 120b are included in one package 110, a plurality of enable input and output pads may be directly connected through wires, or in the case where the first and

second chips

120a and 120b are attached to a printed circuit board, may be indirectly connected through the printed circuit board. For example, in the case where one first chip 120a is included in one package 110a, a plurality of enable input and output pads may be electrically connected through a lead frame. Summarizing, signal transmission between two chips by enabling input-output pads and/or clock input-output pads is not dependent on the way of electrical connection between pads.

The master chip first chip 120a and the slave chip second chip 120b may pass through the data line SDA _ I ² C and a clock line SCL _ I ² C to communicate with the controller 150. The controller 150 designates one chip among a plurality of chips having substantially the same function as a master chip first chip 120a and the other chip as a slave chip second chip 120b. The master chip first chip 120a supplies a driving start signal for controlling the driving of the slave chip second chips 120b to the plurality of slave chip second chips 120b by enabling the input-output pads. The controller 150 may start driving of the plurality of slave chip second chips 120b by controlling the driving start of one master chip first chip 120a.

On the other hand, the driving clock may be provided to the slave chip second chip 120b through the master chip first chip 120a, or may be received from the outside. When the driving clocks of the plurality of chips are different from each other, the driving end times are different. Therefore, in order to drive a plurality of chips at the same time, the plurality of chips should be driven by substantially the same driving clock. For this, the master chip first chip 120a supplies driving clocks to the plurality of slave chip second chips 120b through the clock input output pads, or the master chip first chip 120a and the slave chip second chips 120b may receive driving clocks from the outside through the clock input output pads.

As illustrated in fig. 1 and 2, the master chip first chip 120a and the slave chip second chip 120b are substantially functionally identical semiconductorsOnly the detection object may be different. Referring to fig. 3 (b), the master chip first chip 120a and the slave chip second chip 120b may include I ² C-communication section 121, registers and/or memory 122, peripheral circuitry 123, clock generator 124, and photocell area 125.

I ² The C communication unit 121 passes through the data line SDA _ I ² C and clock line SCL _ I ² C receives the control signal from the controller 150, and transmits the data generated by the first chip 120a and the second chip 120b to the controller 150. In I ² C communication, the controller 150 passes through the data line SDA _ I ² C transfer of I for assigning a unique chip address to each chip, the chip having a corresponding chip address ² The C communication unit 121 passes through the data line SDA _ I ² C transmits the response signal Ack to the controller 150, but the communication sections 121 of the remaining chips do not transmit the response signal. The controller 150 passes through the data line SDA _ I ² C to the chip responded to ² The C communication section 121 transmits data for storing the register address and/or the corresponding register address. I.C. A ² The C communication section 121 stores the received data at a register address on the register and/or the memory 122, and drives the peripheral circuit 123 by the stored data. On the other hand, I ² The C communication unit 121 passes through the data line SDA _ I under the control of the controller 150 ² C to transmit the sensed values stored in the registers and/or memory 122 to the controller 150.

The register and/or memory 122 has addresses for identifying storage locations and a data storage area allocated for each address. Registers and/or memory 122 need not be physically configured as one, registers may be built into peripheral circuitry 123 and memory may be separate from peripheral circuitry 123, as desired.

The peripheral circuit 123 refers to a circuit for controlling chip driving, such as a driver for driving the photo cell area, readout for reading out the pixel current from the photo cell area, an analog-to-digital converter (ADC) for converting the pixel current into a detection value, and the like. That is, the peripheral circuit 123 drives the photocell area 125 based on the data of the register address stored in the register and/or the memory 122 to generate the pixel current in the analog form corresponding to the intensity of the incident light, converts the pixel current into the detection value in the digital form, and stores the detection value in the register and/or the memory 122. In particular, the peripheral circuit 123 is driven to the master mode or the slave mode by the control of the controller 150. If the master mode is set, the peripheral circuit 123 supplies a driving start signal enable to the slave chip second chip 120b. Additionally, the peripheral circuit 123 may provide a driving clock to the slave chip second chip 120b. On the other hand, if the slave mode is set, the peripheral circuit 123 enables the start of driving by the driving start signal received from the master chip first chip 120a and drives a time corresponding to the prescribed number of driving clocks. The driving clock may be received from the main chip first chip 120a or externally.

The clock generator 124 is used to generate the driving clock. In the case of receiving the driving clock from the outside, the clock generator 124 may be omitted. In the case where the master chip first chip 120a provides the driving clock, the clock generator 124 of the slave chip second chip 120b is disabled through the peripheral circuit 123 or the peripheral circuit 123 may operate with the driving clock input through the clock input output pad.

The photovoltaic cell region 125 may include a plurality of first and second

light receiving parts

121a and 121b (see fig. 8 to 10). For example, the first and second

light receiving parts

121a and 121b may be photodiodes, but various light receiving devices may be used instead. The first and second photoreceivers 121a and 121b output pixel currents corresponding to incident light.

The method of driving the plurality of chips may be divided into a master/slave setting process (steps S10 to S17) of setting one of the plurality of chips to a master mode and setting the other chip to a slave mode, and a driving start process (steps S18 to S20) of starting the driving of the master first chip 120a simultaneously with the driving of the slave second chip 120b. If the master chip first chip 120a and the slave chip second chip 120b are determined in advance through the option pads, the entire master/slave setting process (steps S10 to S17) or the clock master (cloak master)/clock slave (cloak slave) setting process (steps S10 to S13) in the master/slave setting process may be omitted.

Referring to fig. 4, the controller 150 sets one of the plurality of chips as a clock master (step S10). The controller 150 passes through the data line SDA _ I ² C transfers a chip address of a chip set as a clock master, a first register address, and a first register value (data) indicating the clock master stored in the first register address.

After the first register value is stored in the first register address, the chip set as the clock master device passes through the data line SDA _ I ² C transmits an acknowledgement signal Ack (step S11). The chip that has been set as the clock master supplies the driving clock through the clock input output pad.

The controller 150 sets the remaining chips, which are not set as clock masters, among the plurality of chips as clock slaves (step S12). The controller 150 passes through the data line SDA _ I ² C transfers a chip address of a chip set as a clock slave, a first register address, and a second register value indicating the clock slave stored at the first register address.

After the second register value is stored at the first register address, the chip set as the clock slave device passes through the data line SDA _ I ² C transmits a response signal Ack (step S13). The chip that has been set as a clock slave receives the driving clock through the clock input output pad.

In the case where a plurality of chips receive the same driving clock from the outside, steps S10 to S13 may be omitted.

The controller 150 sets one of the plurality of chips as an enabled master (master chip) (step S14). The controller 150 passes through the data line SDA _ I ² C transfers a chip address of the master chip first chip 120a, a second register address, and a third register value indicating an enabled master stored at the second register address.

After the third register value is stored at the second register address, the first master chip 120a passes through the data line SDA _ I ² C transmits an acknowledgement signal Ack (step S15). The main chip first chip 120a provides a driving standby signal Disable (Disable) through the enable input output pad.

The controller 150 sets the remaining chips, which are not set as the enabling master, among the plurality of chips as enabling slaves (slave chips) (step S16). The controller 150 is connected to the data line SDA _ I ² C transfers the chip address of the slave chip second chip 120b, the second register address, and a fourth register value indicating the enabled slave device stored at the second register address.

After the fourth register value is stored at the second register address, the slave chip second chip 120b passes through the data line SDA _ I ² C transmits an acknowledgement signal Ack (step S17). The slave chip second chip 120b receives a driving standby signal Disable (Disable) through the enable input output pad. Thereby, the slave chip second chip 120b enters a drive waiting state.

For example, the clock master and the enable master may be the same chip. In this case, steps S14 and S15 may be omitted, and the chip set as the clock master may output the driving clock through the clock input output pad while being disabled by the enable input output pad output driving standby signal. On the other hand, as another embodiment, the clock master and the enable master may be different chips. In this case, the clock master is set as an enable slave, receives a drive start signal enable from the enable master to drive, or may supply a clock only to the clock slave. That is, the clock master may be a clock generator connected with a plurality of chips through clock input and output pads.

If the controller 150 commands the driving start of the master chip first chip 120a (step S18), the master chip first chip 120a supplies a driving start signal enable to the slave chip second chip 120b through the enable input output pad (step S19). The driving start command may include a chip address of the main chip first chip 120a, a third register address, and a fifth register value indicating a driving start stored at the third register address. Therefore, a plurality of chips respectively designated as the master chip first chip 120a and the slave chip second chip 120b can be simultaneously driven to start.

Fig. 5 is a diagram for exemplifying another method of simultaneously driving a plurality of chips in the structure shown in fig. 3. Steps S30 to S37 are the same as steps S10 to S17 of fig. 4, and therefore, a description thereof is omitted.

If the controller 150 commands the start of driving of the second chip 120b (step S38), the response signal Ack is transmitted from the second chip 120b to enter a driving waiting state (step S39). The driving start command may include a chip address from the chip second chip 120b, a third register address, and a fifth register value indicating the start of driving stored in the third register address. That is, the controller 150 commands the slave chip second chip 120b to start driving, and the slave chip second chip 120b waits until receiving the driving start signal enable from the master chip first chip 120a after receiving the driving start command of the controller 150.

If the controller 150 commands the driving start of the master chip first chip 120a (step S40), the master chip first chip 120a supplies a driving start signal enable to the slave chip second chip 120b through the enable input output pad (step S41). Accordingly, a plurality of chips respectively designated as the master chip first chip 120a and the slave chip second chip 120b can be simultaneously driven to start.

Fig. 6 is a diagram for exemplarily explaining a structure for simultaneously driving a plurality of chips, in which fig. 6 (a) partially shows two chips and a controller for driving the same, and fig. 6 (b) partially shows a functional structure of the chips. The same description as in fig. 3 will be omitted, and the differences will be described.

Referring to fig. 6 (a), the plurality of chips are set to a master mode and a slave mode, respectively, and the master chip 120a 'set to the master mode detects the start of driving of the slave chip 120b' set to the slave mode, thereby starting driving. Thus, when comparing the illustrated embodiments with reference to fig. 3 to 5, the chip shown in fig. 6 does not have an enable input output pad. On the other hand, one of the plurality of chips may supply the driving clock necessary for simultaneous driving end to the remaining chips.

The simultaneous driving means that the driving start timing and the driving end timing are the same. In order to make the driving start time the same, one or more master chips 120a 'of the plurality of chips should be able to detect the driving start of one slave chip 120b', and in order to make the driving end time the same, the plurality of chips must be driven by the same driving clock. To this end, the master chip 120a ', the slave chip 120b' includes clock input and output pads for inputting and outputting driving clocks. The clock input output pad is a pad for one chip to supply a driving clock to the remaining chips or receive the driving clock from the outside. Additionally or alternatively, the master chip 120a ', the slave chip 120b' may further include one or more option pads for determining a master mode or a slave mode. If the option pads are used, the operation mode of each chip can be determined in advance.

The master chip 120a 'and the slave chip 120b' may pass through the data line SDA _ I ² C and a clock line SCL _ I ² C to communicate with the controller 150. The controller 150 designates at least one of a plurality of chips having substantially the same function as a master chip 120a 'and one of the remaining chips as a slave chip 120b'. The master chip 120a ' detects the start of driving of the slave chip 120b ' to start driving substantially simultaneously with the slave chip 120b '. The controller 150 controls the driving start of the slave chip 120b 'so that more than one master chip 120a' can be driven to start.

Referring to fig. 6 (b), the master chip 120a 'and the slave chip 120b' may include I ² C-communication section 121', registers and/or memory 122, peripheral circuitry 123, clock generator 124, and photocell area 125.

I ² The C communication unit 121' passes through the data line SDA _ I ² C and clock line SCL _ I ² C receives control signals from the controller 150 and transmits data generated by the chips 120a', 120b to the controller 150. When operating in master mode, I ² The C communication unit 121' passes through the data line SDA _ I ² C monitors the received and transmitted control signals to detect the start of operation of the slave chip 120b'. In detail, I ² The C communication unit 121 'knows the chip address of the slave chip 120b', the third register address for storing the operation start command, and the address corresponding to the operation start commandIf it passes the data line SDA _ I ² C transmits a work start command of the slave chip 120b ', and accordingly, a register value corresponding to the work start command is stored in a register of the master chip 120 a'. Wherein (1) in the case where the response signal Ack indicating the completion of reception of the third register address for storing the register value indicating the start of driving is transmitted from the chip 120b 'to the controller 150, or (2) in the case where the response signal Ack indicating the completion of reception of the fifth register value indicating the start of driving is transmitted from the chip 120b' to the controller 150, the I of the master chip 120a ² The C communication section 121' may store the fifth register value in the register and/or the memory 122.

Fig. 7 is a diagram for exemplifying a method of simultaneously driving a plurality of chips in the structure shown in fig. 3. Steps S50 to S53 are the same as steps S10 to S13 of fig. 4, and therefore, the description thereof is omitted.

The controller 150 sets at least one of the plurality of chips as the master chip 120a' (step S54). The controller 150 passes through the data line SDA _ I ² C transfers a chip address of the master chip 120a ', a second register address, a third register value indicating an enable master stored in the second register address, and a chip address of the slave chip 120b'.

After the third register value and the chip address of the slave chip 120b 'are stored in the second register address, the master chip 120a' passes through the data line SDA _ I ² C transmits a response signal Ack (step S55). Thereafter, the master chip 120a' captures a pass through the data line SDA _ I ² C, and performs monitoring for comparison with the chip address of the slave chip 120b' stored in the second register address.

In the monitoring, even if the chip address of the slave chip 120b 'is received, the master chip 120a' only makes a comparison, and does not transmit the acknowledge signal Ack. The chip address of the slave chip 120b ' is captured, and if the slave chip 120b ' transmits the acknowledge signal Ack, the master chip 120a ' captures the register address transmitted by the controller 150, confirming whether it is the third register value for storing the fifth register value indicating the start of driving. If the slave chip 120b 'transmits the acknowledge signal Ack, the master chip 120a' captures the register value transmitted from the controller 150, confirming whether it is the fifth register value indicating the start of driving.

After the monitoring of the master chip 120a' is started, the controller 150 sets one of the plurality of sensors as a slave chip (step S56). The controller 150 passes through the data line SDA _ I ² C transfers the chip address of the slave chip 120b', the second register address, and a fourth register value representing an enabled slave device stored at the second register address.

After the fourth register value is stored at the second register address, the slave chip 120b' passes through the data line SDA _ I ² C transmits a response signal Ack (step S57). The slave chip 120b' enters a drive wait state.

If the controller 150 commands the start of driving of the master chip 120a '(step S58), the master chip 120a' transmits an acknowledgement signal Ack and enters a driving wait state (step S59). The driving start command may include a chip address of the master chip 120a', a third register address, and a fifth register value indicating a start of driving stored at the third register address. That is, the controller 150 commands the master chip 120a ' to start driving, but the master chip 120a ' waits until the slave chip 120b ' under monitoring receives a driving start command from the controller 150.

If the controller 150 commands the start of driving of the slave chip 120b '(step S60), the slave chip 120b' transmits a response signal Ack and starts driving (step S61). The driving start command may include a chip address from the chip 120b', a third register address, and a fifth register value indicating the start of driving stored at the third register address.

The master chip 120a ', if capturing the chip address of the slave chip 120b', starts driving by a register address and a response signal Ack thereto transmitted later, or by a register value or a response signal Ack thereto (step S62). Therefore, a plurality of chips respectively designated as the master chip 120a 'and the slave chip 120b' can be simultaneously driven to start.

Fig. 8 is a diagram for exemplifying the operation principle of the sensor.

The sensor 100 of the first aspect may be disposed at a lower portion of the display 10. For example, the sensor 100 according to the first aspect may be an illuminance sensor for measuring the intensity of outside light, a color sensor for measuring the intensity of light in each of at least two wavelength bands for measuring the intensity of outside light, or a fingerprint sensor for generating a fingerprint image in contact with a fingerprint acquisition area. The sensor 100 of the first modality generally includes a sensor retarder layer and a sensor polarization layer. The sensor retarder layer and the sensor polarizing layer reduce the effect of light generated by the display. The illumination sensor and the color sensor have the same structure except for the color filter, and the fingerprint sensor and the illumination sensor are the same except for receiving light reflected by the cover glass of the display 10, and therefore the illumination sensor will be mainly described below.

The sensor 100 of the first embodiment is a device for measuring the intensity of incident light. For example, when the illuminance sensor is disposed below the display, light generated inside the display is incident on the illuminance sensor in addition to external light passing through the display (light reflected by the cover glass in the case of a fingerprint sensor). Therefore, at least in order to distinguish the extraneous light from the light generated by the display, it is necessary to measure the intensity of the incident light through different light paths, respectively. The intensity of the measured extraneous light can be ensured. The sensor 100 of the first aspect measures the intensity of light passing through a first light path and the sensor of the second aspect measures the intensity of light passing through a second light path.

The display 10 includes a pixel layer 13 formed with a plurality of pixels P for generating light, a display polarization layer 11 laminated on an upper portion of the pixel layer 13, and a display retarder layer 12. In order to protect the display polarizing layer 11, the display retarder layer 12, and the pixel layer 13, a protective layer formed of an opaque material such as metal or synthetic resin may be disposed on the lower surface of the display 10. As an embodiment, the sensor 100 of the first type including the first light selective layer 130, the second light selective layer 140, the first chip 120a, and the second chip 120b may be disposed in a region where a portion of the protection layer is removed (hereinafter, referred to as a "complete structure"). As another example, the first light selective layer 130 and the second light selective layer 140 of the sensor 100 in the first aspect may be manufactured in a film form and laminated on the lower surface of the display 10. The first chip 120a and the second chip 120b are attached to the lower surfaces of the first light selection layer 130 and the second light selection layer 140, and thus a sensor (hereinafter, referred to as "package structure") can be realized. In order to avoid redundant description, the following description will focus on the completed structure.

The display polarizing layer 11 and the display retarder layer 12 improve the visibility of the display 10. The external light 20 incident through the upper surface of the display 10 is unpolarized light. If the external light 20 is incident toward the upper surface of the display polarizing layer 11, only the display linearly polarized light 21 substantially coincident with the polarization axis of the display polarizing layer 11 passes through the display polarizing layer 11. If the display linearly polarized light 21 passes through the display retarder layer 12, then display circularly polarized light (or elliptically polarized light) 22 is formed that rotates clockwise or counter-clockwise. Display circularly polarized light 22, if reflected to pixel layer 13 and then incident to display retarder layer 12, forms reflected linearly polarized light. Wherein the polarization axis of the display linearly polarized light 21 and the polarization axis of the reflected linearly polarized light are mutually orthogonal if the polarization axis of the display retarder layer 12 is tilted by about 45 degrees with respect to the slow axis. Therefore, the reflected linearly polarized light, i.e., the external light reflected by the pixel layer 13 is blocked by the display polarizing layer 11 and cannot be irradiated to the outside of the display. Accordingly, the visibility of the display 10 can be improved.

The unpolarized light 30 generated by the pixel P travels toward the upper and lower surfaces of the display 10. A part of the unpolarized light 30 traveling toward the upper surface is reflected inside the display 10 and travels toward the lower surface again. Unlike the display circularly polarized light 22, the unpolarized light 30 passes directly through the display retarder layer 12, becomes linearly polarized light by the display polarizing layer 11, and is irradiated to the outside.

The sensor 100 of the first embodiment includes a first optical selective layer 130 and a second optical selective layer 140 having different optical paths, and a first chip 120a and a second chip 120b for detecting light passing through the respective optical paths. The light incident on the sensor 100 in the first mode is display circularly polarized light 22 coming from outside and unpolarized light 30 generated outside the display. The first optical path formed by the first light selective layer 130 and the second optical path formed by the second light selective layer 140 do not contribute differently to the display circularly polarized light 22 than to the unpolarized light 30. The first optical path passes all of the display circularly polarized light 22 and unpolarized light 30. Conversely, the second optical path passes unpolarized light 30 and substantially blocks display circularly polarized light 22. The display circularly polarized light 22 passing through the first optical path becomes the first sensor linearly polarized light 23, the display circularly polarized light 22 passing through the second optical path becomes the second sensor linearly polarized light 24, and the unpolarized light 30 passing through the first optical path and the second optical path becomes the third sensor linearly polarized light 31 and the fourth sensor linearly polarized light 32. The second sensor linearly polarized light 24 may be different according to Polarization Efficiency (PE) of the first light selection layer 130 and the second light selection layer 140. For example, if the polarization efficiency of the first light selective layer 130, the second light selective layer 140 is 100%, the display circularly polarized light 22 passes through the first light selective layer 130 without loss and is completely blocked by the second light selective layer 140. If the polarization efficiency of the first light selective layer 130 and the second light selective layer 140 is less than 100%, a portion of the display circularly polarized light 22 passes through the second light selective layer 140 and becomes the second sensor linearly polarized light 24.

The first chip 120a includes a photocell region 125 constituted by a plurality of first light receivers 121a corresponding to the first light path, and the second chip 120b includes a photocell region 125 constituted by a plurality of second light receivers 121b corresponding to the second light path. For example, first light receiving portions 121a generate a first pixel current that is substantially proportional to the light of first sensor linearly polarized light 23 and third sensor linearly polarized light 31, and second light receiving portions 121b generate a second pixel current that is substantially proportional to the light of second sensor linearly polarized light 24 and fourth sensor linearly polarized light 32. For example, the first and second

light receiving parts

121a and 121b may be formed of one photodiode or a plurality of photodiodes (hereinafter, referred to as "PD array"). As an embodiment, one or two photodiodes may correspond to one pixel P. As still another embodiment, the PD array may correspond to one pixel P. As another embodiment, one or two photodiodes may correspond to a plurality of pixels P. As still another embodiment, the PD array may correspond to a plurality of pixels P.

As described above, the third sensor linearly polarized light 31 and the fourth sensor linearly polarized light 32 from the unpolarized light 30 can be detected by the first light receiving part 121a and the second light receiving part 121b, respectively. On the other hand, although described in detail below, the intensities of the third sensor linearly polarized light 31 and the fourth sensor linearly polarized light 32 may be substantially the same, and conversely, may be different. However, since the third sensor linearly polarized light 31 and the fourth sensor linearly polarized light 32 are derived from the unpolarized light 30 generated by one or a plurality of pixels, a linear proportional relationship or a non-linear proportional relationship holds between the intensities of the two. The non-linear proportional relationship may be caused by various factors such as the structural characteristics of the display 10, the difference in pixel regions corresponding to the respective light receiving portions, and the wavelength band of the unpolarized light 30. The proportional relationship between the third sensor linear polarized light 31 and the fourth sensor linear polarized light 32 can be measured in an environment unaffected by extraneous light. Based on the linear relationship, the degree of contribution of the third sensor linearly polarized light 31 to the intensity measured at the first photoreceivers 121a can be calculated from the intensity of the fourth sensor linearly polarized light 32 measured at the second photoreceivers 121 b.

Fig. 9 is a diagram for exemplifying an embodiment of a sensor having a first light selection layer.

Referring to fig. 9 (a), the first sensor 100a includes a first light selective layer 130 and a first chip 120a. The first light selective layer 130 includes a first sensor retarder layer 320 and a first sensor polarization layer 310. The polarization axis of the first sensor polarization layer 310 is tilted by a first angle, e.g., +45 degrees, with respect to the slow axis of the first sensor retarder layer 320. The first sensor retarder layer 320 is disposed on the first sensor polarization layer 310, and the first chip 120a is disposed on the first sensor polarization layer 310. A color filter layer (not shown) and/or an ultraviolet blocking filter (not shown) that define a wavelength band of light incident to the first light receiving part 121a may be disposed between the first light selecting layer 130 and the first chip 120a. On the other hand, referring to fig. 9 (b), in the first sensor 100b, the first light selection layer 130' may be formed of the second sensor retarder layer 325 and the second sensor polarization layer 315.

The first chip 120a includes a plurality of first light receiving parts 121a that receive light passing through a first light path formed through the first light selection layer 130 or the first light selection layer 130'. The first photoreceivers 121a is used to detect the first sensor linearly polarized light 23 and the third sensor linearly polarized light 31 from the first sensor polarizing layer 310. The first light receiving part 121a may generate a pixel current having a magnitude corresponding to the brightness of the incident light. For example, the first light receiving part 121a may be a photodiode, but is not limited thereto.

The operation of the first sensor 100a having the first light selective layer 130 or the first light selective layer 130' having the above-described structure will be described below.

Display circularly polarized light 22 and unpolarized light (not shown, 30 in fig. 8) are incident on the first sensor retarder layer 320 in the configuration shown in part (a) of fig. 9, and on the upper side of the second sensor retarder layer 325 in the configuration shown in part (b) of fig. 9. The display circularly polarized light 22 is light that is passed by the external light 20 through the display polarizing layer 11 and the display retarder layer 12, and the unpolarized light 30 is light that travels from the pixel P down towards the first light selecting layer 130 or the first light selecting layer 130'.

The display polarizing layer 11 may have a polarizing axis tilted by a second angle (e.g., -45 degrees) with respect to the slow axis of the display retarder layer 12. Thus, the display linearly polarized light 21 passing through the display polarizing layer 11 may be incident at a second angle with respect to the slow axis of the display retarder layer 12. If the first polarized light element of the display linearly polarized light 21 transmitted with the fast axis and the second polarized light element of the display linearly polarized light 21 transmitted with the slow axis pass through the display retarder layer 12, a phase difference of λ/4 is generated therebetween. Thus, display linearly polarized light 21 passing through display retarder layer 12 may become display circularly polarized light 22 rotating in a counter-clockwise direction.

In the structure shown in part (a) of fig. 9, the display circular polarized light 22 having a phase difference of λ/4 between the fast axis and the slow axis passes through the first sensor retarder layer 320 to become the first sensor internal linear polarized light 22a. The polarization axis of the first sensor internal linearly polarized light 22a is orthogonal to the polarization axis of the display linearly polarized light 21. The display circular polarized light 22 having the λ/4 phase difference between the first polarized light element and the second polarized light element can be the first sensor internal linear polarized light 22a having the polarization axis substantially perpendicular to the polarization axis of the display linear polarized light 21, because the λ/4 phase difference of the first sensor retarder layer 320 is reduced. Unpolarized light 30, on the other hand, passes directly through the first sensor retarder layer 320.

The polarization axis of first sensor polarizing layer 310 is substantially parallel to the polarization axis of first sensor inner linearly polarized light 22a, and thus, first sensor inner linearly polarized light 22a from first sensor retarder layer 320 may pass through first sensor polarizing layer 310. On the other hand, unpolarized light 30 from the first sensor retarder layer 320 passes through the first sensor polarization layer 310 to become third sensor linearly polarized light 31.

In the structure shown in part (b) of fig. 9, the second sensor retarder layer 325 causes the phase difference to disappear, and the display circular polarized light 22 can be the second sensor internal linear polarized light 22a' having the polarization axis substantially parallel to the polarization axis of the display linear polarized light 21. Unpolarized light 30, on the other hand, passes directly through the second sensor retarder layer 325.

The polarization axis of the second sensor polarizing layer 315 is substantially parallel to the polarization axis of the second sensor internal linearly polarized light 22a ', and thus the second sensor internal linearly polarized light 22a' from the second sensor retarder layer 325 may pass through the second sensor polarizing layer 315. On the other hand, the unpolarized light 30 from the second sensor retarder layer 325 passes through the second sensor polarization layer 315 to become third sensor linearly polarized light 31'.

That is, the first photoreceivers 121a can detect the first sensor linearly polarized light 23 or the first sensor linearly polarized light 23 'and the third sensor linearly polarized light 31 or the third sensor linearly polarized light 31' by the first optical path formed by the first sensor retarder layer 320-the first sensor polarizing layer 310 or the second sensor retarder layer 325-the second sensor polarizing layer 315.

Fig. 10 is a diagram for exemplifying an embodiment of a sensor having a second light selection layer.

Referring to fig. 10 (a), the second sensor 100c includes a second light selective layer 140 and a second chip 120b. The second light selection layer 140 includes a first sensor retarder layer 320 and a second sensor polarization layer 315. The polarization axis of the second sensor polarization layer 315 may be tilted at a second angle, e.g., -45 degrees, with respect to the slow axis of the first sensor retarder layer 320. The first sensor retarder layer 320 is disposed on the second sensor polarization layer 315, and the second chip 120b is disposed on the second sensor polarization layer 315. A color filter layer (not shown) and/or an ultraviolet blocking filter (not shown) that define a wavelength band of light incident on the light receiving portion 121b may be disposed between the second light selection layer 140 and the second chip 120b. On the other hand, referring to fig. 10 (b), in the second sensor 100d, the second light selection layer 140' may be formed of the second sensor retarder layer 325 and the first sensor polarization layer 310.

The second chip 120b includes a plurality of second light receiving parts 121b that receive light passing through a second light path formed through the second light selection layer 140 or the second light selection layer 140'. The second photoreceivers 121b is used to detect the second sensor linearly polarized light 24 and the fourth sensor linearly polarized light 32 from the second sensor polarizing layer 315. The second light receiving part 121b may generate a pixel current having a magnitude corresponding to the brightness of the incident light. For example, the second light receiving part 121b may be a photodiode, but is not limited thereto.

The operation of the second sensor 100b having the second light selective layer 140 or the second light selective layer 140' having the above-described structure will be described below.

The display circularly polarized light 22 and unpolarized light (not shown, 30 in fig. 8) enter the first sensor retarder layer 320 in the configuration shown in fig. 10 (a), and enter the upper surface of the second sensor retarder layer 325 in the configuration shown in fig. 10 (b).

In the structure shown in part (a) of fig. 10, the display circular polarized light 22 having the phase difference of λ/4 between the fast axis and the slow axis passes through the first sensor retarder layer 320 to become the first sensor internal linear polarized light 22a. The polarization axis of the first sensor internal linearly polarized light 22a is orthogonal to the polarization axis of the display linearly polarized light 21. The display circular polarized light 22 having the λ/4 phase difference between the first polarized light element and the second polarized light element can be the first sensor internal linear polarized light 22a having the polarization axis substantially perpendicular to the polarization axis of the display linear polarized light 21, because the λ/4 phase difference of the first sensor retarder layer 320 is reduced. Unpolarized light 30, on the other hand, passes directly through the first sensor retarder layer 320.

The polarization axis of second sensor polarizing layer 315 is substantially perpendicular to the polarization axis of first sensor internal linearly polarized light 22a, and thus, first sensor internal linearly polarized light 22a from first sensor retarder layer 320 is mostly blocked by second sensor polarizing layer 315 and only a portion passes through. The light passing through the second sensor polarization layer 315 becomes second sensor linearly polarized light 24. On the other hand, the unpolarized light 30 from the first sensor retarder layer 320 passes through the second sensor polarizing layer 315 to become fourth sensor linearly polarized light 32.

In the structure shown in part (b) of fig. 10, the second sensor retarder layer 325 causes the phase difference to disappear, and the display circular polarized light 22 can be the second sensor internal linear polarized light 22a' having the polarization axis substantially parallel to the polarization axis of the display linear polarized light 21. Unpolarized light 30, on the other hand, passes directly through the second sensor retarder layer 325.

The polarization axis of first sensor polarizing layer 310 is substantially perpendicular to the polarization axis of second sensor internal linearly polarized light 22a ', so that a majority of second sensor internal linearly polarized light 22a' from second sensor retarder layer 325 is blocked by first sensor polarizing layer 310 and only a portion passes through. The light passing through the first sensor polarizing layer 310 becomes second sensor linearly polarized light 24'. On the other hand, unpolarized light 30 from the second sensor retarder layer 325 passes through the first sensor polarization layer 310 and becomes fourth sensor linearly polarized light 32'.

That is, the second light receiving portions 121b can detect the second sensor linearly polarized light 24 or 24 'and the fourth sensor linearly polarized light 32 or 32' by the second optical path constituted by the first sensor retarder layer 320-the second sensor polarizing layer 315 or the second sensor retarder layer 325-the first sensor polarizing layer 310.

On the other hand, although not shown, the first sensor 100a does not include the first light selective layer 130, and only the second sensor 100b may include the second light selective layer 140 or the second light selective layer 140'.

The present invention has been described above for illustrative purposes, and it will be understood by those skilled in the art that the present invention may be easily modified into other specific forms without changing the technical spirit or essential features of the present invention. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive.

The scope of the present invention is defined by the appended claims, rather than the detailed description given above, and all changes and modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included in the scope of the present invention.

Claims

1. Simultaneously driving a plurality of I ² Method of C slave device, through I ² The communication mode C is characterized in that the two chips are driven by a controller connected with the two chips simultaneously, and the method comprises the following steps:

if the controller sets one of the two chips as a master chip, the master chip outputs a driving wait signal to an enable input/output pad of the master chip side;

receiving, by the slave chip, the driving wait signal from the master chip through an input-output pad on the slave chip side if the controller sets the other of the two chips as a slave chip;

if the controller transmits a driving start command to the main chip, the main chip outputs a driving start signal to an enable input/output pad of the main chip side;

and if the driving start signal is received through the enable input and output pad of the slave chip side, the slave chip starts driving.

2. Driving multiple I simultaneously as claimed in claim 1 ² The method of the slave device C, further comprising:

a step in which if the controller sets one of the two chips as a clock master, the clock master outputs a driving clock to a clock input/output pad on the clock master side;

a step in which the clock slave receives the driving clock from the clock master through a clock input-output pad on the clock slave side if the controller sets the other of the two chips as a clock slave.

3. Driving multiple I simultaneously as claimed in claim 1 ² The method of the C slave device is characterized by further comprising:

and a step in which the slave chip waits until the driving start signal is received through an enable input/output pad of the slave device side if the controller transmits the driving start command to the slave chip.

4. Driving multiple I simultaneously as claimed in claim 1 ² The method of the C slave device is characterized in that the number of the slave chips is multiple.

5. Through I ² The C communication mode is a chip driven by the controller at the same time, and is characterized in that a plurality of chips pass through I ² When the communication mode C is connected with the controller, the chips are driven simultaneously by the control of the controller through I ² C-shaped connectorThe chip whose signal mode is driven by the controller simultaneously comprises:

enabling the input and output pad;

I ² a C communication unit which receives a first register value for specifying one of the master chip and the slave chip and a second register value indicating the start of driving from the controller via a data line;

a register and/or memory storing the first register value at a first register address and the second register value at a second register address;

and a peripheral circuit outputting a driving wait signal to the enable input output pad if the master chip is set by the first register value, and outputting a driving start signal to the enable input output pad by the second register value.

6. The process of claim 5 via I ² C a chip whose communication mode is simultaneously driven by a controller, wherein if the slave chip is set by the first register value, the peripheral circuit receives the driving wait signal through the enable input output pad, and if the driving start signal is received through the enable input output pad, the peripheral circuit starts driving.

7. The process of claim 5 via I ² C communication mode is by the chip of controller simultaneous drive, its characterized in that still includes:

a clock input/output pad, if set as a clock master by the controller, passes through the I ² The other chips connected by the C communication method provide a driving clock, and if set as a clock slave, receive the driving clock from any one of the other chips or from the outside.

8. The process of claim 7 by I ² C communication mode is by chip that the controller drove simultaneously, its characterized in that still includes:

a clock generator generating the driving clock output through the clock input output pad.

9. The process of claim 5 via I ² C communication mode is by the chip of controller simultaneous drive, its characterized in that still includes:

a cell area which controls driving by the peripheral circuit and generates a pixel current corresponding to an intensity of incident light.

10. The process of claim 9 by I ² C, a chip driven by the controller in a communication mode, wherein the chip is configured at the lower part of the display; and is

The chip is disposed under a first light selective layer that passes both ambient light incident on the photocell area and light generated by the display.

11. The process of claim 10 via I ² And a chip driven by the controller in a communication mode, wherein the chip is disposed under a second light selective layer, and the second light selective layer allows the external light and a part of the light generated by the display to pass therethrough.

12. The process of claim 11 by I ² And a chip driven by the controller at the same time in the communication mode, wherein the chip disposed under the first optical selection layer and the chip disposed under the second optical selection layer start driving at the same driving start time and end driving at the same driving end time.