CN112881887A

CN112881887A - Chip testing method, computing chip and digital currency mining machine

Info

Publication number: CN112881887A
Application number: CN202110056648.0A
Authority: CN
Inventors: 刘建波; 陈默; 范志军; 郭海丰; 杨作兴
Original assignee: Shenzhen MicroBT Electronics Technology Co Ltd
Current assignee: Shenzhen MicroBT Electronics Technology Co Ltd
Priority date: 2021-01-15
Filing date: 2021-01-15
Publication date: 2021-06-01
Anticipated expiration: 2041-01-15
Also published as: CN112881887B

Abstract

The present disclosure relates to a chip testing method, a computing chip and a digital currency miner. The to-be-tested computing chip comprises a plurality of cores, and the chip testing method comprises the following steps: each core of the plurality of cores performs the following operations, respectively: receiving a reset signal, wherein the reset signal is configured to generate a corresponding first test vector in a core; based on a secure hash algorithm, obtaining a core test result of the core according to a test vector and a test random value, wherein the test vector comprises a first test vector; and generating a chip test result of the computing chip according to the core test results of the plurality of cores.

Description

Chip testing method, computing chip and digital currency mining machine

Technical Field

The disclosure relates to the technical field of chip testing, in particular to a chip testing method, a computing chip and a digital currency mining machine.

Background

Digital currency is typically virtually encrypted and is in the form of P2P (Peer-to-Peer), such as bitcoin. Digital currency is unique in that it is not typically issued by a particular currency institution, but rather is generated by a large number of operations depending on a particular algorithm. For example, bitcoin transactions use a distributed database of numerous nodes throughout the P2P network to validate and record all transactions and use cryptographic designs to ensure security.

Digital currency mining is possible using a digital currency mining machine, which is primarily rewarded based on the operational capabilities of the mining machine, i.e., the digital currency mining machine is of the proof of work (POW) type. For a digital currency mining machine, the computing power (i.e., the number of operations per unit time) and power consumption (i.e., the power consumed to perform the same number of operations per unit time) of a computing chip are the most important factors in determining the performance of the machine.

In order to screen out from the chips produced that can function properly, and to determine and optimize the performance of the digital currency miner formed from the computing chips, it is necessary to test the computing chips. For example, testing may be performed by Automated Test Equipment (ATE) or a digital currency miner. Since testing costs are generally closely related to testing time, there is a need to improve testing efficiency to reduce testing costs.

Disclosure of Invention

It is an object of the present disclosure to provide a chip testing method, a computing chip and a digital currency miner.

According to a first aspect of the present disclosure, there is provided a chip testing method, in which a computing chip to be tested includes a plurality of cores, the chip testing method including:

each core of the plurality of cores performs the following operations, respectively:

receiving a reset signal, wherein the reset signal is configured to generate a corresponding first test vector in a core;

generating a core test result of the core according to a test vector and a test random value based on a secure hash algorithm, wherein the test vector comprises a first test vector; and

and generating a chip test result of the computing chip according to the core test results of the plurality of cores.

According to a second aspect of the present disclosure, there is provided a computing chip comprising:

a plurality of cores, each of the plurality of cores including a test vector register or a test vector latch, wherein when a reset terminal of the test vector register or the test vector latch receives a reset signal, bits thereof are reset to a state corresponding to a corresponding first test vector; and

a top-level module communicatively connected with the plurality of cores.

According to a third aspect of the present disclosure, there is provided a digital currency miner including a computing chip as described above.

Other features of the present disclosure and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.

The present disclosure may be more clearly understood from the following detailed description, taken with reference to the accompanying drawings, in which:

FIG. 1 shows a flow diagram of a chip testing method according to an example embodiment of the present disclosure;

FIG. 2 shows a schematic structural diagram of a computing chip according to an exemplary embodiment of the present disclosure;

FIG. 3 illustrates a first test vector in a specific embodiment according to the present disclosure;

FIG. 4 illustrates a second test vector in a specific embodiment according to the present disclosure;

fig. 5 shows a schematic flow chart of step S200 in the chip testing method of fig. 1.

Note that in the embodiments described below, the same reference numerals are used in common between different drawings to denote the same portions or portions having the same functions, and a repetitive description thereof will be omitted. In this specification, like reference numerals and letters are used to designate like items, and therefore, once an item is defined in one drawing, further discussion thereof is not required in subsequent drawings.

For convenience of understanding, the positions, sizes, ranges, and the like of the respective structures shown in the drawings and the like do not sometimes indicate actual positions, sizes, ranges, and the like. Therefore, the disclosed invention is not limited to the positions, dimensions, ranges, etc., disclosed in the drawings and the like. Furthermore, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components.

Detailed Description

Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. That is, the chip testing method and the computing chip herein are shown by way of example to illustrate different embodiments of the circuit or method in the present disclosure and are not intended to be limiting. Those skilled in the art will appreciate that they are merely illustrative of ways that the invention may be practiced, not exhaustive.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

During the manufacturing process of a computing chip and a digital currency miner, the computing chip is typically tested to obtain performance parameters associated with the computing chip to help screen out properly functioning computing chips, determine performance metrics for the digital currency miner, and optimize performance of the digital currency miner. The tests can be performed in different stages to meet the respective requirements.

For a computing Chip prepared on a wafer and not packaged, a Probe may be used to apply signal excitation to a relevant pad on the wafer, so as to test a basic function of the computing Chip, i.e., Chip Probe (CP) test. Through CP test, can realize the prescreening to calculating the chip, reject unqualified calculating the chip in time before carrying on the encapsulation, thus reduce the subsequent production manufacturing cost.

After the computing chips are cut from the wafer and packaged, Final Tests (FT) may be performed on the computing chips to remove the computing chips that fail due to slicing, packaging, etc. processes, preventing them from being assembled into the digital currency miner, thereby ensuring the quality of the digital currency miner.

Typically, both CP and FT tests may be performed by Automated Test Equipment (ATE). That is, the ATE may test the computing chips before they are assembled into the digital currency miner, thereby screening out properly functioning computing chips. The cost of ATE testing is closely related to the test time, and the longer the test time, the higher the test cost.

In addition, the computer chip may be subjected to a search frequency test in the digital currency miner prior to shipment. In particular, the testing may be performed by testing software built into the digital currency miner. Through the frequency searching test, parameters such as the optimal operating frequency and the optimal operating voltage of the computing chip can be determined, and therefore the performance index of the digital currency mining machine is determined. In practice, a digital currency miner with better performance metrics may have a higher price, thereby achieving better benefits. It is understood that it is also desirable to reduce the time required for the frequency search test as much as possible in order to avoid delays in the factory shipment.

All or some of the three tests described above may be performed during the manufacturing process of the computing chip and the digital currency miner. When all tests are executed, the performance parameters of the computing chips are monitored in each link, unqualified computing chips are removed in time, and accordingly the test cost is usually high. In order to save the test cost, some tests can be omitted, for example, in the case that the normal computing function of the chip is to be tested in the FT test, the same test for the computing function can be omitted in the previous CP test, and only the current, leakage, analog IP and the like are tested in the CP test, so that the repeated test items are omitted, and the test cost is reduced.

During the operation of the digital currency mining machine, random values are generated continuously to perform collision operation with a test vector (work) based on the test vector given in the calculation of the current round until a result meeting specific requirements is calculated.

Similarly, in the test process of the computing chip, a test vector can be provided for each core in the computing chip, and a different test random value is adopted to perform a collision operation with the corresponding test vector so as to test whether the core is normal. Wherein the compute chip may provide the test vectors to the cores serially or in parallel through the interface component. In the case of serial transmission, the number of corresponding pins and traces in the computing chip can be saved, but the required transmission time is generally longer. In the case of parallel transmission, although the transmission time can be reduced to a certain extent, the number of required pins and wires will be increased, which will occupy the number of pins and increase the difficulty of PCB-level wiring of the product, so that the data transmission between chips will usually adopt a serial mode. Moreover, the test vectors require a certain transmission time in serial or parallel mode, and the time required in the conventional serial mode is more, which may result in the increase of the test cost.

In order to solve the above problems, the present disclosure provides a chip testing method and a computing chip, in which at least one test vector is embedded in a core of the computing chip, so as to eliminate or reduce the time required for transmitting the test vector in the testing process, thereby improving the testing efficiency and reducing the testing cost.

In an exemplary embodiment of the present disclosure, as shown in fig. 1 and 2, a computing chip may include a plurality of cores 910 and a top-level module 920 communicatively connected to the cores 910. Among other things, the top module 920 may be configured for booting, communicating, controlling, etc. operations of the computing chip. Each core 910 may perform the following operations:

step S100, a reset signal is received, wherein the reset test vector register (or test vector latch) is configured to generate a corresponding first test vector in core 910.

The first test vector may be included in a given test vector for testing. The first test vector may be fixed and invariant over a round of testing. In general, the first test vector may include a plurality of bits, e.g., in a specific example, the first test vector may include 352 bits. It will be appreciated that when the top-level module 920 of the computing chip transmits such a first test vector to the core 910 through the interface component therein, the required transmission time is longer. In this embodiment, the top module 920 may transmit a reset signal to the core 910 instead of the first test vector itself. The reset signal itself may occupy only one or a few bits compared to the first test vector, and thus the time required to transmit the reset signal may be significantly reduced. By pre-configuring core 910, when core 910 receives a reset signal, a corresponding first test vector may be generated therein.

As shown in FIG. 2, in an exemplary embodiment, core 910 may include a test vector register (or test vector latch) 911. The register or latch may store binary code so that a pre-configuration of the first test vector may be achieved. In a register or latch, each memory cell (for storing one bit) may be reset to 0 or 1 (as determined by the particular memory cell) after receiving a reset signal. Thus, the test vector register (or test vector latch) 911 corresponding to the reset default value may be arranged by the value of each bit in the first test vector.

For example, in a specific embodiment shown in FIG. 3, the memory cells in test vector register (or test vector latch) 911 may be arranged as shown, where each memory cell will be reset to 1, 0, 1, respectively, after receiving a reset signal, in a left-to-right order. Accordingly, in this test vector register (or test vector latch) 911, the embedded first test vector may be 1011011001101011. Thus, when core 910 receives a reset signal, test vector register (or test vector latch) 911 is reset, generating a first test vector therein. In a subsequent step, this first test vector may be used for collision operations with the test random values.

In some embodiments, the respective first test vectors of each core 910 of the plurality of cores 910 of the compute chip may be identical to each other. In this way, the test vector registers (or test vector latches) 911 in each core 910 may have a similar configuration, thereby simplifying the manufacturing of the computing chip. Of course, the technical solution of the present disclosure is not limited thereto, and in some other embodiments, the same first test vector may be set in only some cores 910 of the cores 910, or different first test vectors may be set in different cores 910, respectively, according to the test requirement.

By embedding the first test vector in the core 910 of the computing chip, the time required for transmitting the test vector can be reduced during the test process, and in addition, noise interference during the test vector transmission process can be avoided, so that the test result is more reliable and stable.

However, to achieve a more complete test, collision operations may need to be performed based on more different test vectors during the test.

In some embodiments of the present disclosure, more first test vectors may be embedded in core 910 to improve the completeness of the test. For example, more test vector registers (or test vector latches) 911 may be provided in the same core 910 to embed more first test vectors in the core 910. During testing, a corresponding first test vector may be generated in one or more particular test vector registers (or test vector latches) 911 by sending a reset signal to the corresponding test vector register (or test vector latch) 911; and when testing based on the other first test vector is required, a reset signal is sent to the other corresponding test vector register (or test vector latch) 911. However, it is understood that when too many test vector registers (or test vector latches) 911 are provided in the same core 910, the area required for the core 910 increases, and thus the computational chip increases.

In view of the above, in some embodiments of the present disclosure, at least some cores 910 of the plurality of cores 910 may also obtain corresponding second test vectors. The second test vector may be transferred to the corresponding core 910 in series or in parallel during testing in a conventional manner, and the test vector register (or test vector latch) of the present invention may receive a new value for storage in addition to having a function of resetting to a particular value. In particular, the top-level module 920 of the computing chip may include an interface component through which the second test vector may be transmitted to the core 910. The interface component may specifically include at least one of a universal asynchronous receiver transmitter (UART, which converts between serial and parallel communications), a Serial Peripheral Interface (SPI), and an I2C interface. Although the transmission of the second test vector will take a certain time, the total test time can be reduced due to the existence of the first test vector under the same test coverage rate, thereby improving the test efficiency.

In some embodiments, the second test vector may be stored in the test vector register (or test vector latch) 911 without requiring additional registers or latches to be provided for the second test vector. That is, when testing based on the second test vector, the second test vector received by core 910 will overwrite the original first test vector in test vector register (or test vector latch) 911.

For example, in one embodiment shown in FIG. 4, when core 910 receives the second test vector, the storage locations in test vector register (or test vector latch) 911 are set to 1, 0, 1, 0, 1, 0, in left-to-right order, i.e., the corresponding written second test vector may be 1001110011100001.

In some embodiments, a second test vector based test may be performed on all of the cores 910 of the plurality of cores 910 to learn the performance parameters of each core 910. Of course, the technical solution of the present disclosure is not limited thereto, and in other embodiments, in order to save the testing time and improve the testing efficiency, the test based on the second test vector may also be performed on only a part of the cores 910.

The respective second test vectors of each core 910 may be identical to each other. In this way, the top module 920 of the computing chip may receive the same second test vector from the outside through the external interface, and transmit the second test vector to a different core 910 through the interface component, so as to improve the testing efficiency. In other embodiments, the same second test vector may be transmitted to only some cores 910, or different second test vectors may be transmitted to different cores 910, respectively, to meet specific test requirements.

Returning to fig. 1, each core 910 in the compute chip may perform the following operations:

and step S200, generating a core test result of the core according to the test vector and the test random value based on a secure hash algorithm.

Where the test vector may include a first test vector embedded in a test vector register (or test vector latch) 911 of core 910. In some embodiments, the test vectors may also include a second test vector transmitted to the core 910 by the top-level module 920 of the compute chip.

The test random value is typically a once-used non-repeating random number nonce (number used once) that may ensure that authentication information is not reused against replay attacks in communication applications of various authentication protocols. During testing, a test random value may be generated by core 910. That is, during testing of a core 910, the core 910 may generate a number of different test random values, which are used together with the test vectors to perform the collision operation, thereby obtaining the core test result of the core 910.

As shown in fig. 5, generating a core test result of the core according to the test vector and the test random value based on the secure hash algorithm may include:

step S210, acquiring a test random value within a preset value range;

step S220, based on the secure hash algorithm, calculating a test output value of the core according to the test vector and the obtained test random value;

step S231, when a test random value which enables the test output value to be consistent with the preset output value exists in the preset numerical range and the test random value which enables the test output value to be consistent with the preset output value is consistent with the theoretical expected value, determining that the core test result of the core is a pass test; and

step S232, when there is no test random value in the preset value range that makes the test output value consistent with the preset output value, or when the test random value that makes the test output value consistent with the preset output value is inconsistent with the theoretical expected value, determining that the core test result of the core is a failed test.

Each core 910 in the computing chip may be configured to operate in different preset value ranges, and the provided test vectors are configured to enable the normal core 910 to calculate a test output value consistent with the preset output value according to the test vector and the test random value in the corresponding preset value range. Based on the secure hash algorithm, through multiple collision operations, when a test random value that makes the test output value consistent with the preset output value can be found within the preset value range, and the test random value used at this time is also consistent with the theoretical expected value, it may be considered that the core 910 is normal, that is, the test is passed, otherwise, the core 910 is considered to have a fault, that is, the test is not passed.

There may be a variety of ways to set the preset output value. In some embodiments, the preset output value may be a value in which a preset number of consecutive bits are all zero, for example a value of 0 for 8 consecutive bits. In other embodiments, the preset output value corresponding to each core 910 may also be pre-calculated according to the attribute of the core 910 and the corresponding test vector, and the preset output value may be stored in the corresponding register of the core 910.

Generally, the number of bits occupied by the core test results of each core 910 may be 1, so as to save memory space in the computing chip. For example, when a core passes a test, the core test result of the core may be set to 1; and when the core fails the test, the core test result of the core may be set to 0.

Returning to fig. 1, the chip testing method may further include:

step S300, generating a chip test result of the computing chip according to the core test results of the plurality of cores 910.

Specifically, the top module 920 in the computing chip may receive the core test result of each core 910 and generate the chip test result of the computing chip according to the core test result.

In some embodiments, especially in the frequency search test, the chip test method may be further performed on the computing chip at least two test frequencies, respectively, to obtain chip test results of the computing chip at the at least two test frequencies. As described above, the optimum operating frequency, optimum operating voltage, etc. of the computing chip may be found through a frequency search test to obtain performance parameters of the digital currency miner formed from the computing chip.

The present disclosure also provides a digital currency miner that may include a computing chip according to the above. In particular, the digital currency miner may include one or more computing chips. Multiple computing chips may perform computing tasks in parallel, such as performing SHA-256 algorithms and the like, to perform digital currency mining.

According to the technical scheme, at least one test vector is embedded in the core of the computing chip, and the reset signal is adopted to generate the test vector in the test process, so that the time required for transmitting the test vector can be effectively reduced, the test time is further reduced, and the test cost is saved and the delivery speed is improved. In addition, because the test vector can be embedded in the core of the computing chip, noise (such as noise introduced by serial communication) interference in the communication process is also avoided, so that the results of chip testing and whole machine frequency searching are more accurate, and the frequency searching performance is improved. The normal register (or latch) function of the test vector register (or test vector latch) with the reset terminal arranged in the core of the computing chip is not influenced, and the ATE and the digital currency mining machine can still transmit new test vectors to the corresponding core for more complete testing, and the normal mining work of the digital currency mining machine is not influenced.

In addition, embodiments of the present disclosure may also include the following examples:

1. a chip testing method, a computing chip to be tested comprises a plurality of cores, and the chip testing method comprises the following steps:

2. The chip testing method according to 1, the respective first test vectors of each of the plurality of cores being identical to each other.

3. The chip testing method according to claim 1, wherein each of the plurality of cores includes a test vector register or a test vector latch, and wherein each bit therein is reset to a state corresponding to a corresponding first test vector when the test vector register or the test vector latch receives a reset signal.

4. The chip testing method according to 3, further comprising:

at least some of the plurality of cores respectively perform the following:

acquiring a corresponding second test vector;

wherein the test vectors further comprise a second test vector.

5. The chip testing method of 4, the respective second test vectors of each of the at least some cores being identical to each other.

6. The chip testing method of claim 4, the at least some cores comprising all of the plurality of cores.

7. According to the chip testing method of 4, the second test vector is stored in the test vector register or the test vector latch of the corresponding core.

8. The chip testing method according to 1, wherein the generating of the core test result of the core according to the test vector and the test random value based on the secure hash algorithm comprises:

acquiring a test random value within a preset value range;

calculating a test output value of the core according to the test vector and the obtained test random value based on a secure hash algorithm;

when a test random value which enables the test output value to be consistent with the preset output value exists in the preset numerical range, and the test random value which enables the test output value to be consistent with the preset output value is consistent with the theoretical expected value, determining that the core test result of the core is a pass test; and

and when a test random value which enables the test output value to be consistent with the preset output value does not exist in the preset numerical value range, or the test random value which enables the test output value to be consistent with the preset output value is not consistent with the theoretical expected value, determining that the core test result of the core is a failed test.

9. According to the chip testing method described in 8, the preset output value is a value in which a consecutive preset number of bits are all zero.

10. According to the chip test method described in 1, the test random value is a non-repetitive random number nonce used only once, and the test random value is generated in the core.

11. According to the chip testing method of 1, the chip testing method is respectively executed on the computing chip under at least two testing frequencies, so as to obtain chip testing results of the computing chip under the at least two testing frequencies.

12. A computing chip, the computing chip comprising:

a top-level module communicatively connected with the plurality of cores.

13. The computing chip of claim 12, each core of the plurality of cores configured to generate a core test result for the core from a test vector and a test random value based on a secure hash algorithm, wherein the test vector comprises a first test vector.

14. The computing chip of claim 13, the top module comprising an interface component configured to obtain a second test vector and transmit the second test vector to a test vector register or a test vector latch of at least some of the plurality of cores, wherein the test vector comprises the second test vector.

15. The computing chip of claim 14, the interface component comprising at least one of: universal asynchronous receiver transmitter, serial peripheral interface and I2C interface.

16. The computing chip of claim 13, the top module configured to generate chip test results for the computing chip from core test results for the plurality of cores.

17. A digital currency miner including a computing chip according to any one of 12 to 16.

In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

The terms "front," "back," "top," "bottom," "over," "under," and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the disclosure described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

As used herein, the word "exemplary" means "serving as an example, instance, or illustration," and not as a "model" that is to be replicated accurately. Any implementation exemplarily described herein is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, the disclosure is not limited by any expressed or implied theory presented in the preceding technical field, background, brief summary or the detailed description.

As used herein, the term "substantially" is intended to encompass any minor variation resulting from design or manufacturing imperfections, device or component tolerances, environmental influences, and/or other factors. The word "substantially" also allows for differences from a perfect or ideal situation due to parasitic effects, noise, and other practical considerations that may exist in a practical implementation.

The above description may indicate elements or nodes or features being "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" means that one element/node/feature is directly connected to (or directly communicates with) another element/node/feature, either electrically, mechanically, logically, or otherwise. Similarly, unless expressly stated otherwise, "coupled" means that one element/node/feature may be mechanically, electrically, logically, or otherwise joined to another element/node/feature in a direct or indirect manner to allow for interaction, even though the two features may not be directly connected. That is, coupled is intended to include both direct and indirect joining of elements or other features, including connection with one or more intermediate elements.

It will be further understood that the terms "comprises/comprising," "includes" and/or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Those skilled in the art will appreciate that the boundaries between the above described operations merely illustrative. Multiple operations may be combined into a single operation, single operations may be distributed in additional operations, and operations may be performed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments. However, other modifications, variations, and alternatives are also possible. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the foregoing examples are for purposes of illustration only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any combination without departing from the spirit and scope of the present disclosure. It will also be appreciated by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A chip testing method is characterized in that a to-be-tested computing chip comprises a plurality of cores, and the chip testing method comprises the following steps:

2. The chip testing method of claim 1, wherein the respective first test vectors of each of the plurality of cores are identical to each other.

3. The chip testing method according to claim 1, wherein each of the plurality of cores comprises a test vector register or a test vector latch, wherein each bit therein is reset to a state corresponding to the corresponding first test vector when the test vector register or the test vector latch receives a reset signal.

4. The chip testing method according to claim 3, further comprising:

at least some of the plurality of cores respectively perform the following:

acquiring a corresponding second test vector;

wherein the test vectors further comprise a second test vector.

5. The chip testing method of claim 4, wherein the respective second test vectors of each of the at least some cores are identical to each other.

6. The chip testing method of claim 4, wherein the at least some cores comprise all of the plurality of cores.

7. The chip test method of claim 4, wherein the second test vector is stored in a test vector register or a test vector latch of the corresponding core.

8. The chip testing method of claim 1, wherein generating the core test result of the core from the test vector and the test random value based on a secure hash algorithm comprises:

acquiring a test random value within a preset value range;

9. The chip test method according to claim 8, wherein the preset output value is a value in which a consecutive preset number of bits are all zero.

10. The chip testing method according to claim 1, wherein the test random value is a non-repetitive random number nonce used only once, and the test random value is generated in a core.

11. The chip testing method according to claim 1, wherein the chip testing method is performed on the computing chip at least two testing frequencies respectively to obtain chip testing results of the computing chip at the at least two testing frequencies.

12. A computing chip, comprising:

a top-level module communicatively connected with the plurality of cores.

13. The computing chip of claim 12, wherein each core of the plurality of cores is configured to generate a core test result for the core from a test vector and a test random value based on a secure hash algorithm, wherein the test vector comprises a first test vector.

14. The computing chip of claim 13, wherein the top module comprises an interface component configured to obtain a second test vector and transmit the second test vector to a test vector register or a test vector latch of at least some of the plurality of cores, wherein the test vector comprises the second test vector.

15. The computing chip of claim 14, wherein the interface component comprises at least one of: universal asynchronous receiver transmitter, serial peripheral interface and I2C interface.

16. The computing chip of claim 13, wherein the top-level module is configured to generate chip test results for the computing chip from core test results for the plurality of cores.

17. A digital currency miner, comprising a computing chip according to any one of claims 12 to 16.