CN112885851B - Array substrate and method for preparing the same - Google Patents

Abstract

The present invention discloses an array substrate and a method for preparing the array substrate. The array substrate comprises: a substrate; a first transistor, the first transistor is arranged on one side of the substrate, the first transistor comprises a metal oxide layer, a polycrystalline composite material layer and a first polycrystalline silicon layer stacked along the vertical direction of the array substrate, the conductivity of the polycrystalline composite material layer is greater than the conductivity of the metal oxide layer, and less than the conductivity of the first polycrystalline silicon layer; a second transistor, the second transistor is arranged on the same side of the substrate as the first transistor, the second transistor comprises a second polycrystalline silicon layer. The conductivity of the polycrystalline composite material layer is stronger than the conductivity of the metal oxide layer. In the first transistor, the conductivity of the polycrystalline composite material layer is between the conductivity of the first polycrystalline silicon layer and the conductivity of the metal oxide layer, which improves the electrical uniformity of the first transistor and reduces the number of transistors required. When applied to a display panel, the pixel density can be increased, and the power consumption of the transistor and the risk of leakage can be reduced.

Description

Array substrate and method for preparing the same

Technical Field

The present invention belongs to the technical field of electronic products, and in particular relates to an array substrate and a method for preparing the array substrate.

Background technique

For the existing LTPO (Low Temperature Polycrystalline Oxide) display panel, since it contains LTPS (Low Temperature Poly-Silicon) transistors and IGZO (indium gallium zinc oxide) transistors, the active layers of low-temperature polycrystalline silicon are polycrystalline silicon and IGZO respectively. Due to the limitation of process materials, IGZO has the risk of uneven electrical properties and is prone to leakage and other problems.

Therefore, a new array substrate and a method for preparing the array substrate are urgently needed.

Summary of the invention

An embodiment of the present invention provides an array substrate and a method for preparing the array substrate. In a first transistor, the conductivity of the polycrystalline composite material layer is between the conductivity of the first polysilicon layer and the metal oxide layer, thereby improving the electrical uniformity of the first transistor and reducing the required number of transistors. When applied to a display panel, the pixel density can be increased and the power consumption of the transistor and the risk of leakage can be reduced.

On the one hand, an embodiment of the present invention provides an array substrate, comprising: a substrate; a first transistor, the first transistor is arranged on one side of the substrate, the first transistor comprises a metal oxide layer, a polycrystalline composite material layer and a first polycrystalline silicon layer stacked along the vertical direction of the array substrate, the conductivity of the polycrystalline composite material layer is greater than the conductivity of the metal oxide layer, and less than the conductivity of the first polycrystalline silicon layer; a second transistor, the second transistor is arranged on the same side of the substrate as the first transistor, the second transistor comprises a second polycrystalline silicon layer.

According to one aspect of the present invention, the polycrystalline composite material layer comprises metal oxide and polycrystalline silicon.

On the other hand, an embodiment of the present invention further provides a method for preparing an array substrate, comprising: providing a substrate; forming a first active portion and a second active portion on the substrate, the first active portion comprising a stacked metal oxide layer and a first amorphous silicon layer, the metal oxide layer being arranged close to the substrate, and the second active portion comprising a second amorphous silicon layer; crystallizing the first amorphous silicon layer of the first active portion to form a first polycrystalline silicon layer, and heating a contact interface between the first polycrystalline silicon layer and the metal oxide layer to form a polycrystalline composite material layer.

According to another aspect of the present invention, in the step of crystallizing the first amorphous silicon layer of the first active portion: the first amorphous silicon layer is irradiated with laser to crystallize the first amorphous silicon layer to form a first polycrystalline silicon layer.

According to another aspect of the present invention, in the step of irradiating the first amorphous silicon layer with laser to crystallize the first amorphous silicon layer to form a first polycrystalline silicon layer: the energy penetration depth of the laser is greater than the minimum distance between the surface of the side where the first amorphous silicon layer and the metal oxide layer are in contact to the surface of the side of the first amorphous silicon layer away from the metal oxide layer.

According to another aspect of the present invention, the minimum distance between the surface of the first amorphous silicon layer in contact with the metal oxide layer and the surface of the first amorphous silicon layer away from the metal oxide layer is 4.5nm-5.5nm; the energy penetration depth of the laser is 5.6nm-7.0nm.

According to another aspect of the present invention, the laser has a wavelength of 157nm to 353nm; preferably, the laser is a xenon chloride excimer laser with a wavelength of 308nm.

According to another aspect of the present invention, in the step of forming the first active portion and the second active portion on the substrate: the minimum distance between the surface of the metal oxide layer in contact with the substrate and the surface of the metal oxide layer away from the substrate is 40nm to 50nm.

According to another aspect of the present invention, after the step of crystallizing the first amorphous silicon layer of the first active part to form a first polycrystalline silicon layer, it also includes: forming an interlayer insulating layer on the side of the first polycrystalline silicon layer away from the metal oxide layer; and forming a gate layer on the side of the interlayer insulating layer away from the first polycrystalline silicon layer.

According to another aspect of the present invention, after the step of forming a gate layer on a side of the interlayer insulating layer away from the first polysilicon layer, the method further includes: forming a source and drain layer on a side of the first polysilicon layer away from the metal oxide layer.

Compared with the prior art, the array substrate provided in the embodiment of the present invention includes a substrate, a first transistor and a second transistor, the first transistor includes a metal oxide layer, a polycrystalline composite material layer and a first polycrystalline silicon layer stacked in the vertical direction of the array substrate, and the atomic arrangement structure of the polycrystalline composite material layer is more orderly than the atomic arrangement structure of the metal oxide layer. Therefore, the conductivity of the polycrystalline composite material layer is stronger than that of the metal oxide layer. In the first transistor, the conductivity of the polycrystalline composite material layer is between the conductivity of the first polycrystalline silicon layer and the metal oxide layer, which improves the electrical uniformity of the first transistor, reduces the number of transistors required, and can improve the pixel density when applied to the display panel, and reduce the power consumption of the transistor and the risk of leakage.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

FIG. 1 is a film layer structure diagram of an array substrate provided in an embodiment of the present invention.

FIG2 is a flow chart of a method for preparing an array substrate provided in an embodiment of the present invention;

3 is a film layer structure diagram of an array substrate in a preparation process of the array substrate preparation method provided in an embodiment of the present invention;

4 is a film layer structure diagram of another array substrate in the preparation process of the array substrate preparation method provided in an embodiment of the present invention;

5 is a diagram showing a film layer structure of another array substrate in the preparation process of the array substrate preparation method provided in an embodiment of the present invention;

6 is a diagram showing a film layer structure of another array substrate in the preparation process of the array substrate preparation method provided in an embodiment of the present invention;

7 is a film layer structure diagram of another array substrate in the preparation process of the array substrate preparation method provided in an embodiment of the present invention;

In the attached figure:

1-substrate; 20-first transistor; 2-first active part; 21-metal oxide layer; 22-first amorphous silicon layer; 23-first polycrystalline silicon layer; 24-polycrystalline composite material layer; 25-interlayer insulating layer; 26-gate layer; 27-source and drain layer; 30-second transistor; 3-second active part; 31-second amorphous silicon layer; 4-inorganic insulating layer.

Detailed ways

The features and exemplary embodiments of various aspects of the present invention will be described in detail below. In the detailed description below, many specific details are proposed to provide a comprehensive understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present invention by illustrating examples of the present invention.

It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

In order to better understand the present invention, an array substrate and a method for manufacturing the array substrate according to an embodiment of the present invention are described in detail below with reference to FIGS. 1 to 7 .

Referring to FIG. 1 , an embodiment of the present invention provides an array substrate, comprising: a substrate 1; a first transistor 20, the first transistor 20 is disposed on one side of the substrate 1, the first transistor 20 comprises a metal oxide layer 21, a polycrystalline composite material layer 24 and a first polycrystalline silicon layer 23 stacked along the vertical direction of the array substrate, the conductivity of the polycrystalline composite material layer 24 is greater than the conductivity of the metal oxide layer 21, and less than the conductivity of the first polycrystalline silicon layer 23; a second transistor 30, the second transistor 30 is disposed on the same side of the substrate 1 as the first transistor 20, the second transistor 30 comprises a second polycrystalline silicon layer. Optionally, an inorganic insulating layer 44 is disposed between the first transistor 20 and the second transistor 30.

The array substrate provided by the embodiment of the present invention includes a substrate 1, a first transistor 20 and a second transistor 30. The first transistor 20 includes a metal oxide layer 21, a polycrystalline composite material layer 24 and a first polycrystalline silicon layer 23 stacked in the vertical direction of the array substrate. The atomic arrangement structure of the polycrystalline composite material layer 24 is more regular than the atomic arrangement structure of the metal oxide layer 21. Therefore, the conductivity of the polycrystalline composite material layer 24 is stronger than that of the metal oxide layer 21. In the first transistor 20, the conductivity of the polycrystalline composite material layer 24 is between the conductivity of the first polycrystalline silicon layer 23 and the conductivity of the metal oxide layer 21, which improves the electrical uniformity of the first transistor 20, reduces the number of transistors required, and can improve the pixel density when applied to the display panel, and reduce the power consumption of the transistor and the risk of leakage.

In some optional embodiments, the polycrystalline composite material layer 24 includes metal oxide and polycrystalline silicon. Specifically, the polycrystalline composite material layer 2 can be formed when the first polycrystalline silicon layer 23 is formed, and the contact interface between the first polycrystalline silicon layer 23 and the metal oxide layer 21 is heated and rearranged atomically to form the polycrystalline composite material layer 2.

Referring to FIG. 2 to FIG. 5 , an embodiment of the present invention further provides a method for preparing an array substrate, which is used to prepare the array substrate in any of the above embodiments. The method for preparing the array substrate includes:

S110: providing a substrate 1, as shown in FIG3 ;

S120: forming a first active portion 2 and a second active portion 3 on the substrate 1, wherein the first active portion 2 includes a metal oxide layer 21 and a first amorphous silicon layer 22 which are stacked, the metal oxide layer 21 being disposed close to the substrate 1, and the second active portion 3 including a second amorphous silicon layer 31, as shown in FIG4 ;

S130 : performing crystallization treatment on the first amorphous silicon layer 22 of the first active portion 2 to form a first polycrystalline silicon layer 23 , and heating the contact interface between the first polycrystalline silicon layer 23 and the metal oxide layer 21 to form a polycrystalline composite material layer 24 , as shown in FIG. 5 .

The preparation method of the array substrate provided in an embodiment of the present invention first provides a substrate 1, and the base body can be a flexible or rigid substrate 1, and then a first active part 2 and a second active part 3 are formed on the substrate 1, and the first active part 2 includes a stacked metal oxide layer 21 and a first amorphous silicon layer 22, the metal oxide layer 21 and the substrate 1 are arranged in contact, and the first amorphous silicon layer 22 is arranged on the side of the metal oxide layer 21 away from the substrate 1, and then the first amorphous silicon layer 22 is crystallized so that the first amorphous silicon layer 22 absorbs energy and converts it into a first polycrystalline silicon layer 23, and in the process of crystallization of the first amorphous silicon layer 22, the contact interface between the formed first polycrystalline silicon layer 23 and the metal oxide layer 21 can be heated and rearranged atomically to form a polycrystalline composite material layer 24, and the atomic arrangement structure of the polycrystalline composite material layer 24 is more orderly than the atomic arrangement structure of the metal oxide layer 21. Therefore, the conductivity of the polycrystalline composite material layer 24 is stronger than that of the metal oxide layer 21. In the first active part 2, the conductivity of the polycrystalline composite material layer 24 is between that of the first polysilicon layer 23 and the metal oxide layer 21, which improves the electrical uniformity of the first active part 2 and reduces the required number of transistors. When applied to a display panel, it can increase the pixel density and reduce transistor power consumption and leakage risk.

It should be noted that the metal oxide layer 21 can specifically be made of materials such as IGZO (indium gallium zinc oxide). Specifically, IGZO is an amorphous oxide containing indium, gallium and zinc, and its carrier mobility is 20 to 30 times that of amorphous silicon. It can greatly improve the charging and discharging rate of the transistor to the pixel electrode, improve the response speed of the pixel, and achieve a faster refresh rate. At the same time, the faster response also greatly improves the row scanning rate of the pixel. The first amorphous silicon layer 22 and the second amorphous silicon layer 31 specifically refer to film layers formed by a-Si (amorphous silicon), and the first polycrystalline silicon layer 23 specifically refers to a film layer formed by p-Si (polycrystalline silicon).

Optionally, the second amorphous silicon layer 31 is crystallized by laser irradiation or other processes to form a second polycrystalline silicon layer. The second amorphous silicon layer 31 and the first amorphous silicon layer 22 can be formed by the same process or can be formed separately. The first active portion 2 and the second active portion 3 can be arranged in the same layer for easy forming, or can be arranged in different layers. There is no special limitation.

It can be understood that the array substrate formed by the embodiment of the present invention is an array substrate formed by the LTPO (Low Temperature Polycrystalline Oxide) process, including two types of transistors whose active layers are respectively the first active part 2 and the second active part 3, namely, LTPS (Low Temperature Poly-Silicon) transistor and IGZO transistor.

The substrate 1 may be a rigid substrate 1 or a flexible substrate 1 to provide support for the remaining film layers on the array substrate; when the substrate 1 is a rigid substrate 1, the material of the substrate 1 may be glass; when the substrate 1 is a flexible substrate 1, the material of the substrate 1 may be polyimide; in some other embodiments, the substrate 1 may also be a transparent substrate 1 so that the array substrate can be applied to a bottom-emitting display panel.

Optionally, in the step of crystallizing the first amorphous silicon layer 22 of the first active portion 2: laser irradiation is performed on the first amorphous silicon layer 22 to crystallize the first amorphous silicon layer 22 to form a first polycrystalline silicon layer 23. Energy is provided to the first amorphous silicon layer 22 by laser irradiation to cause the first amorphous silicon layer 22 to produce a crystallization effect to form the first polycrystalline silicon layer 23.

In some optional embodiments, in the step of performing laser irradiation on the first amorphous silicon layer 22 to crystallize the first amorphous silicon layer 22 to form a first polycrystalline silicon layer 23: the energy penetration depth of the laser is greater than the minimum distance between the surface of the side where the first amorphous silicon layer 22 and the metal oxide layer 21 are in contact and the surface of the side of the first amorphous silicon layer 22 facing away from the metal oxide layer 21.

It is understood that the energy penetration depth of the laser specifically refers to the thickness of the material that the energy of the laser can penetrate, that is, the depth that the energy of the laser can reach. The energy penetration depth of the laser is greater than the minimum distance between the surface of the first amorphous silicon layer 22 and the metal oxide layer 21 in contact with each other and the surface of the first amorphous silicon layer 22 away from the metal oxide layer 21, that is, the energy of the laser can not only act on the entire first amorphous silicon layer 22, so that the first amorphous silicon layer 22 is heated and crystallized to be converted into the first polycrystalline silicon layer 23, but also pass through the first amorphous silicon layer 22 to act on part of the metal oxide layer 21, so that part of the metal oxide layer 21 is heated and rearranged atomically, and combined with the adjacent part of the first polycrystalline silicon layer 23 to form a polycrystalline composite material layer 24 with more orderly atomic arrangement and better conductivity, thereby improving the carrier mobility of the polycrystalline composite material layer 24. It is understood that the energy penetration depth of the laser can be adjusted accordingly by adjusting the light intensity of the laser.

In some optional embodiments, the minimum distance between the surface of the first amorphous silicon layer 22 in contact with the metal oxide layer 21 and the surface of the first amorphous silicon layer 22 facing away from the metal oxide layer 21 is 4.5nm to 5.5nm; the energy penetration depth of the laser is 5.6nm to 7.0nm.

In order to avoid the array substrate from being too thick, the minimum distance between the surface of the first amorphous silicon layer 22 in contact with the metal oxide layer 21 and the surface of the first amorphous silicon layer 22 facing away from the metal oxide layer 21 is 4.5nm~5.5nm, that is, the thickness of the first amorphous silicon layer 22 is 4.5nm~5.5nm. In order to allow the energy of the laser to pass through the first amorphous silicon layer 22 so that the metal oxide layer 21 can also be heated to rearrange its atoms, the energy penetration depth of the laser can be 5.6nm~7.0nm, as long as it is greater than the thickness of the first amorphous silicon layer 22.

In order to ensure the absorption rate of the first amorphous silicon layer 22 to the laser energy, in some optional embodiments, the laser has a wavelength of 157nm to 353nm; specifically, the laser is a xenon chloride excimer laser with a wavelength of 308nm.

It should be noted that in order to crystallize and transform the first amorphous silicon layer 22 into the first polycrystalline silicon layer 23, an ELA (Excimer Laser Annealing) process is required. Excimer laser refers to the laser emitted when the molecules formed by the mixed gas formed by the combination of inert gas and halogen gas excited by the electron beam transition to their ground state. Excimer laser is a pulsed laser with strong directionality, high wavelength purity and high output power. The photon energy wavelength range is 157nm~353nm, and the life span is tens of nanoseconds. It belongs to ultraviolet light. The most common wavelengths are 157nm, 193nm, 248nm, 308nm, 351~353nm. According to actual tests, when the first amorphous silicon layer 22 is irradiated with a xenon chloride excimer laser with a wavelength of 308nm, the first amorphous silicon layer 22 has the highest absorption rate for laser energy, and the conversion rate for the first polycrystalline silicon layer 23 is also relatively high.

In some optional implementations, in the step of forming the first active portion 2 and the second active portion 3 on the substrate 1: the minimum distance between the surface of the metal oxide layer 21 in contact with the substrate 1 and the surface of the metal oxide layer 21 away from the substrate 1 is 40nm to 50nm. Specifically, the thickness of the metal oxide layer 21 is 40nm to 50nm. In the above embodiment, the thickness of the first amorphous silicon layer 22 is 4.5nm to 5.5nm, and the energy penetration depth of the laser can be 5.6nm to 7.0nm. Therefore, after penetrating the first amorphous silicon layer 22, the laser will only act on the part of the metal oxide layer 21 close to the first amorphous silicon layer 22, and the heated part of the metal oxide layer 21 and the contacted part of the first polycrystalline silicon layer 23 are combined to form a polycrystalline composite material layer 24. Therefore, the first polycrystalline silicon layer 23, the polycrystalline composite material layer 24 and the metal oxide layer 21 are finally formed in a stacked arrangement.

Please refer to Figure 6. In some optional embodiments, after the step of crystallizing the first amorphous silicon layer 22 of the first active part 2 to form the first polysilicon layer 23, it also includes: forming an interlayer insulating layer 25 on the side of the first polysilicon layer 23 away from the metal oxide layer 21; and forming a gate layer 26 on the side of the interlayer insulating layer 25 away from the first polysilicon layer 23.

It is understandable that the interlayer insulating layer 25 can be made of inorganic insulating materials such as silicon nitride, silicon oxide or silicon oxynitride, and a gate layer 26 is formed on the side of the interlayer insulating layer 25 away from the first polysilicon layer 23. The gate layer 26 can be made of materials such as molybdenum metal. Molybdenum metal has stable properties, good corrosion resistance, and is not easy to react with water vapor, so it will not be corroded and broken by water vapor. The interlayer insulating layer 25 and the gate layer 26 can be formed in the form of deposition or evaporation. Optionally, the thickness of the interlayer insulating layer 25 is 120nm to 150nm, and the thickness of the gate layer 26 is 200nm to 300nm.

Please refer to FIG. 7 , in some optional embodiments, after the step of forming the gate layer 26 on the side of the interlayer insulating layer 25 away from the first polysilicon layer 23 , the step further includes: forming a source and drain layer 27 on the side of the first polysilicon layer 23 away from the metal oxide layer 21 .

It should be noted that the source and drain electrode layer 27 can be formed specifically by a sputtering process. The sputtering process uses ions in the plasma to bombard the sputtered material electrode, so that the gas phase plasma contains particles of the sputtered material. These particles are deposited on the surface of the metal oxide layer 21 to form the source and drain electrode layer 27. Specifically, the source and drain electrode layer 27 can be made of a titanium-aluminum-titanium composite metal layer, which has good corrosion resistance and good electrical conductivity.

The array substrate provided in the embodiment of the present invention can be applied to mobile phones, and can also be applied to any electronic products with display functions, including but not limited to the following categories: televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, medical equipment, industrial control equipment, touch interactive terminals, etc. The embodiment of the present invention does not make special limitations on this.

The above is only a specific implementation of the present invention. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present invention is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present invention, and these modifications or replacements should be covered within the protection scope of the present invention.

It should also be noted that the exemplary embodiments mentioned in the present invention describe some methods or systems based on a series of steps or devices. However, the present invention is not limited to the order of the above steps, that is, the steps can be performed in the order mentioned in the embodiments, or in a different order from the embodiments, or several steps can be performed simultaneously.

Claims (11)

1. An array substrate, comprising: substrate; a first transistor, the first transistor being disposed on one side of the substrate, the first transistor comprising a metal oxide layer, a polycrystalline composite material layer and a first polycrystalline silicon layer stacked in a vertical direction of the array substrate, the conductivity of the polycrystalline composite material layer being greater than the conductivity of the metal oxide layer and less than the conductivity of the first polycrystalline silicon layer; The second transistor is disposed on the same side of the substrate as the first transistor, and the second transistor includes a second polysilicon layer. 2 . The array substrate according to claim 1 , wherein the polycrystalline composite material layer comprises metal oxide and polycrystalline silicon. 3. A method for preparing an array substrate, for preparing the array substrate according to any one of claims 1 to 2, characterized in that it comprises: providing a substrate; forming a first active portion and a second active portion on the substrate, wherein the first active portion comprises a metal oxide layer and a first amorphous silicon layer which are stacked, the metal oxide layer being arranged close to the substrate, and the second active portion comprises a second amorphous silicon layer; The first amorphous silicon layer of the first active portion is crystallized to form a first polycrystalline silicon layer, and a contact interface between the first polycrystalline silicon layer and the metal oxide layer is heated to form a polycrystalline composite material layer. 4. The method for preparing an array substrate according to claim 3, characterized in that in the step of crystallizing the first amorphous silicon layer of the first active portion: The first amorphous silicon layer is irradiated with laser light to crystallize the first amorphous silicon layer to form a first polycrystalline silicon layer. 5. The method for preparing an array substrate according to claim 4, characterized in that in the step of irradiating the first amorphous silicon layer with laser to crystallize the first amorphous silicon layer to form a first polycrystalline silicon layer: The energy penetration depth of the laser is greater than the minimum distance between a surface of the first amorphous silicon layer in contact with the metal oxide layer and a surface of the first amorphous silicon layer facing away from the metal oxide layer. 6. The method for preparing an array substrate according to claim 5, characterized in that a minimum distance between a surface of the first amorphous silicon layer in contact with the metal oxide layer and a surface of the first amorphous silicon layer facing away from the metal oxide layer is 4.5 nm to 5.5 nm; The energy penetration depth of the laser is 5.6nm to 7.0nm. 7 . The method for preparing an array substrate according to claim 6 , wherein the laser has a wavelength of 157 nm to 353 nm. 8 . The method for preparing an array substrate according to claim 7 , wherein the laser is a xenon chloride excimer laser with a wavelength of 308 nm. 9. The method for preparing an array substrate according to claim 3, characterized in that in the step of forming the first active portion and the second active portion on the substrate: The minimum distance between the surface of the metal oxide layer in contact with the substrate and the surface of the metal oxide layer away from the substrate is 40 nm to 50 nm. 10. The method for preparing an array substrate according to claim 3, characterized in that after the step of crystallizing the first amorphous silicon layer of the first active portion to form a first polycrystalline silicon layer, the method further comprises: forming an interlayer insulating layer on a side of the first polysilicon layer away from the metal oxide layer; A gate layer is formed on a side of the interlayer insulating layer away from the first polysilicon layer. 11. The method for preparing an array substrate according to claim 10, characterized in that after the step of forming a gate layer on a side of the interlayer insulating layer away from the first polysilicon layer, the method further comprises: A source and drain layer is formed on a side of the first polysilicon layer away from the metal oxide layer.