CN112885393B - A flash memory word line driving circuit - Google Patents
A flash memory word line driving circuit Download PDFInfo
- Publication number
- CN112885393B CN112885393B CN202110209114.7A CN202110209114A CN112885393B CN 112885393 B CN112885393 B CN 112885393B CN 202110209114 A CN202110209114 A CN 202110209114A CN 112885393 B CN112885393 B CN 112885393B
- Authority
- CN
- China
- Prior art keywords
- word line
- row
- voltage
- driving circuit
- inverter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000015654 memory Effects 0.000 title claims abstract description 40
- 239000000758 substrate Substances 0.000 claims description 8
- 239000003990 capacitor Substances 0.000 description 5
- 230000006870 function Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000004088 simulation Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000003491 array Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
Landscapes
- Read Only Memory (AREA)
Abstract
本发明公开了一种闪存存储器字线驱动电路，包括：第一行地址选择信号驱动电路，用于在某行被选中时将行地址选择信号经逻辑电路处理后产生的行译码输出控制信号转换为能够驱动字线的高压信号；字线选择开关，用于在所述行地址选择信号驱动电路输出的高压信号的控制下将读输出电压VPOS_RD接通至该选中行的字线以读取该选中行的信息；第二行地址选择信号驱动电路，用于在某行未被选中时将行地址选择信号经逻辑电路处理后产生的行译码输出控制信号低电平转换为高电平以将该未被选中行的字线接地。
The present invention discloses a flash memory word line driving circuit, comprising: a first row address selection signal driving circuit, used for converting a row decoding output control signal generated after a row address selection signal is processed by a logic circuit into a high voltage signal capable of driving a word line when a row is selected; a word line selection switch, used for connecting a read output voltage VPOS_RD to the word line of the selected row under the control of the high voltage signal output by the row address selection signal driving circuit to read the information of the selected row; and a second row address selection signal driving circuit, used for converting a row decoding output control signal generated after a row address selection signal is processed by a logic circuit into a high voltage level when a row is not selected to ground the word line of the unselected row.
Description
Technical Field
The invention relates to the technical field of flash memories, in particular to a novel flash memory word line driving circuit.
Background
The erase, write (program) and read (read) operations of memory cells in a flash memory (flash memory) all require a high voltage above the power supply voltage VDD, which is typically provided by integrating a charge pump circuit inside the memory. When a flash memory has two memory cell arrays (array) for parallel read-write operation, the high voltage required by erase and program operation is provided by a charge pump, and the high voltage required by read operation is provided by a boost module.
When the flash memory performs a read operation, a Word Line (WL) side high voltage is generated by the boost module and transferred to the word line through the word line driving circuit. A simple working schematic of the boost module is shown in fig. 1. The Boost module mainly increases the output voltage through the principle that the voltages at two ends of the capacitor cannot be suddenly changed, when the control signal controls the Boost module to start working, the output voltage can be increased from a voltage state (Vpower) when the Boost module is not working to a high voltage state (vpos_rd) when the Boost module is working, but the voltage finally generated is closely related to the size of the capacitor load. The larger the capacitive load, the lower the final output voltage, so in order to obtain a higher output voltage, the load capacitance needs to be reduced as much as possible. As can be seen from fig. 1, assuming that the voltage value of V out is V 1 when Clk is low, when Clk is raised from low to V clk to high, if transmission loss is not considered, it can be calculated when there is no load capacitance C load:
Vout＝V1+Vclk (1)
if a load capacitance C load is present, it can be calculated:
Vout＝V1+(VclkC1)/(C1+Cload) (2)
as can be seen from equation 2, the output voltage V out decreases continuously as the capacitive load C load increases in the output voltage without changing C1.
As shown in fig. 2, a word line driving circuit commonly used in a flash memory is composed of a row address selection signal driving circuit 10 and a word line selection switch 20. The row address selection signal driving circuit 10 is composed of a voltage converter I1 and an inverter I2, and is used for converting a row decoding output control signal decoder output generated by processing a row address selection signal through a logic circuit into a high voltage signal capable of driving word lines, and the word line selection switch 20 is composed of a PMOS driving tube PM1 and an NMOS driving tube NM1, and is used for switching on the word lines under the control of the high voltage signal output by the row address selection signal driving circuit 10 so as to read information of a designated row.
Wherein vpos_rd is a read output voltage of a boost (boost) module, decoder output is a row decoding output control signal generated after a row address selection signal is processed by a logic circuit, I1 is a voltage converter, I2 is an inverter, C WL is a capacitive load on a whole row word line, and C gNM1 is a gate (gate) capacitance of an NMOS drive tube NM1 tube.
As can be seen from the figure, when the flash memory performs a read operation, the decoder output signal is changed from low level "0" to high level "1" for the word line driving circuit of the selected row, the output n1 voltage of the voltage converter I1 is increased from VSS to vpos_rd through the voltage converter process, the output n2 voltage of the inverter I2 is changed from vpos_rd to VSS, and the PMOS driving tube PM1 is turned on, and the voltage of the word line WL is increased from VSS to vpos_rd. For the word line driving circuit of the unselected row, the decoder output signal is always at low level "0", the output n1 voltage of the voltage converter I1 is VSS, the output n2 voltage of the inverter I2 is vpos_rd, the NMOS driving transistor NM1 is turned on, and the voltage of the word line WL is VSS.
When a read operation is performed, the read output voltage vpos_rd of the boost (boost) module increases, and the output n2 voltage of the inverter I2 also increases. The NMOS drive transistor NM1 corresponds to a MOS capacitor in which the gate voltage gradually increases. Therefore, during the read operation, the capacitive load C load on the read output voltage vpos_rd of the boost (boost) module is composed of two parts, one part is the capacitive load C WL on the selected row word line, the other part is the gate (gate) capacitance C gNM1 of the NM1 tube in the unselected row word line driving circuit, and since the PMOS driving tube PM1 and the NMOS driving tube NM1 of the last stage of the word line driving circuit need to drive the whole row of memory cells, the size is generally larger, the capacitance of the gate capacitance C gNM1 is also larger, so that the vpos_rd high voltage output during the operation of the boost (boost) module is reduced, the voltage of the word line WL cannot meet the requirement of the read mode, and the efficiency of the boost (boost) module is also reduced. This problem becomes more serious when the number of rows of the flash memory is large.
To improve this problem, as shown in equation 2, it is common practice to increase the output voltage by increasing the capacitor C 1 in the boost module, but increasing the capacitor has a certain disadvantage that on one hand, the area of the whole flash memory is increased, and on the other hand, the power consumption in the read mode is increased.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention aims to provide a word line driving circuit of a flash memory, so as to solve the problem that the output voltage is reduced due to the fact that the output voltage load capacitance of a boost module is too large when the flash memory uses a word line driver with a traditional structure, thereby influencing the reading function of the flash memory.
To achieve the above and other objects, the present invention provides a word line driving circuit for a flash memory, comprising:
A first row address selection signal driving circuit for converting a row decoding output control signal generated by processing a row address selection signal by a logic circuit into a high voltage signal capable of driving a word line when a certain row is selected;
A word line selection switch for switching on a read output voltage vpos_rd to a word line of the selected row under control of a high voltage signal output from the row address selection signal driving circuit to read information of the selected row;
and the second row address selection signal driving circuit is used for converting a low level of a row decoding output control signal generated by processing a row address selection signal through the logic circuit into a high level when a certain row is not selected so as to grounded the word line of the unselected row.
Preferably, the first row address selection signal driving circuit includes a voltage converter (I1) and a second inverter (I2), the row decoding output control signal is connected to an input terminal of the voltage converter (I1) and the second row address selection signal driving circuit, an output of the voltage converter (I1) is connected to an input terminal of the second inverter (I2), an output of the second inverter (I2) is connected to the word line selection switch, and power supply negative terminals of the voltage converter (I1) and the second inverter (I2) are grounded.
Preferably, the word line selection switch includes a PMOS driving transistor (PM 1) and an NMOS driving transistor (NM 1), the output of the second inverter (I2) is connected to the gate of the PMOS driving transistor (PM 1), the source and the substrate of the PMOS driving transistor (PM 1) are connected to the read output voltage vpos_rd, the gate of the NMOS driving transistor (NM 1) is connected to the second row address selection signal driving circuit, the source and the substrate of the NMOS driving transistor (NM 1) are grounded, and the drain of the PMOS driving transistor (PM 1) is connected to the word line WL after being connected to the NMOS driving transistor (NM 1).
Preferably, the second row address selection signal driving circuit includes a third inverter (I3), an input terminal of the third inverter (I3) is connected to the row decoding output control signal, an output of the third inverter is connected to a gate of the NMOS driving tube (NM 1), a source electrode of the NMOS driving tube (NM 1) is grounded to a substrate, a power supply positive terminal of the third inverter (I3) is connected to a voltage VDD, and a power supply negative terminal is grounded.
Preferably, when the flash memory performs a read operation, for the word line driving circuit of the selected row, the row decoding output control signal is changed from low level "0" to high level "1", the output voltage thereof is raised from VSS to the read output voltage vpos_rd through the voltage converter (I1), the output voltage of the second inverter (I2) is changed from the read output voltage vpos_rd to VSS, the PMOS driving transistor (PM 1) is turned on, and the voltage of the word line WL is raised from VSS to the read output voltage vpos_rd.
Preferably, for the word line driving circuits of the unselected rows, the row decoding output control signal is always at a low level "0", the output voltage of the voltage converter (I1) is VSS through the voltage converter (I1), the output of the second inverter (I2) is the read output voltage vpos_rd, the PMOS driving transistor (PM 1) is controlled to be turned off, the counter signal voltage generated by the row decoding output control signal through the third inverter (I3) is VDD, the NMOS driving transistor (NM 1) is controlled to be turned on, and the voltage of the word line WL is VSS.
Compared with the prior art, the word line driving circuit of the flash memory can effectively reduce the capacitance load of the output voltage of the boosting module in the reading mode, thereby solving the problem that the output voltage is reduced due to the fact that the capacitance of the load of the output voltage of the boost module is too large when the word line driver with the traditional structure is used in the flash memory, and further influencing the reading function of the flash memory. Simulation results show that the word line driving circuit with the novel structure effectively improves the WL voltage and avoids the influence on the reading function of the flash memory when the WL voltage is lower.
Drawings
FIG. 1 is a schematic diagram of the operation of a boost module;
fig. 2 is a circuit configuration diagram of a word line driving circuit of a conventional structure;
Fig. 3 is a circuit diagram of a word line driving circuit of a flash memory according to the present invention.
Detailed Description
Other advantages and effects of the present invention will become readily apparent to those skilled in the art from the following disclosure, when considered in light of the accompanying drawings, by describing embodiments of the present invention with specific embodiments thereof. The invention may be practiced or carried out in other embodiments and details within the scope and range of equivalents of the various features and advantages of the invention.
Fig. 3 is a circuit diagram of a word line driving circuit of a flash memory according to the present invention. As shown in fig. 3, a word line driving circuit for a flash memory according to the present invention includes a first row address selection signal driving circuit 10, a word line selection switch 20, and a second row address selection signal driving circuit 30.
The first row address selection signal driving circuit 10 is composed of a voltage converter I1 and an inverter I2, and is used for converting a row decoding output control signal decoder output generated after a row address selection signal is processed by a logic circuit into a high voltage signal capable of driving word lines when a row is selected, the word line selection switch 20 is composed of a PMOS driving tube PM1 and an NMOS driving tube NM1, and is used for switching on a read output voltage vpos_rd to the word line of the selected row under the control of the high voltage signal output by the row address selection signal driving circuit 10 so as to read information of the selected row, and the second row address selection signal driving circuit 30 is composed of an inverter I2, and is used for converting a row decoding output control signal decoder output generated after a row address selection signal is processed by the logic circuit into a high level so as to ground the word line of the unselected row.
The row decoding output control signal decoder output is connected to an input end of the voltage converter I1 and an input end of the inverter I3, an output n1 of the voltage converter I1 is connected to an input end of the inverter I2, an output n2 of the inverter I2 is connected to a grid electrode of the PMOS driving tube PM1, a source electrode and a substrate of the PMOS driving tube PM1 are connected to the read output voltage VPOS_RD, power supply positive ends of the voltage converter I1 and the inverter I2 are connected to the read output voltage VPOS_RD, power supply negative ends of the voltage converter I1 and the inverter I2 are grounded VSS, an output n3 of the inverter I3 is connected to a grid electrode of the NMOS driving tube NM1, a source electrode and a substrate of the NMOS driving tube NM1 are grounded VSS, a power supply positive end of the inverter I3 is connected to the voltage VDD, a power supply negative end of the inverter I3 is grounded VSS, and a drain electrode of the PMOS driving tube PM1 is connected to the NMOS driving tube NM1 and then connected to the word line WL.
Compared with the traditional structure circuit, the NMOS drive tube NM1 is not controlled by the output n2 signal of the inverter I2, but is controlled by the inverse signal n3 generated after the decoder output passes through the inverter I3. Thus, for selected rows, the PMOS drive tube PM1 is turned on, the circuit functions the same as a conventional structure circuit, for unselected rows, the decoder output signal is "0", the output n3 signal of the inverter I3 is VDD, the NMOS drive tube NM1 is turned on, and the voltage of the word line WL is VSS. However, since the NMOS driving transistor NM1 is controlled by the output n3 of the inverter I3, the capacitive load on the read output voltage vpos_rd of the boost (boost) module is only the capacitive load C WL on the selected row word line, so that the vpos_rd voltage and the voltage of the selected row word line WL are effectively improved, and the boost efficiency is improved.
As shown in FIG. 3, where VPOS_RD is the output voltage of the boost module, decoder output is the address selection signal processed by the logic circuit, I1 is the voltage converter, I2 and I3 are inverters, and CWL is the capacitance on the word line. As can be seen from the figure, compared with the word line driving circuit with the conventional structure, the control circuit of the NMOS driving transistor NM1 is changed, the original n2 signal only controls the PMOS driving transistor PM1, and the NMOS driving transistor NM1 is controlled by the inverse signal n3 signal of the decoder output after passing through the inverter I3.
When the flash memory performs a read operation, for the word line driving circuit of the selected row, the decoder output signal is changed from low level "0" to high level "1", the n1 voltage is increased from VSS to vpos_rd through the voltage converter process, the output n2 voltage of the inverter I2 is changed from vpos_rd to VSS, so that the PM1 pipe is opened, and the voltage of the word line WL is increased from VSS to vpos_rd, which is the same as the function of the word line driving circuit of the conventional structure.
For the word line driving circuit of the unselected row, the decoder output control signal is always at low level "0", the output n1 voltage of the voltage converter I1 is VSS, the output n2 voltage of the inverter I2 is vpos_rd, the PMOS driving transistor PM1 is controlled to be turned off, the inverse signal n3 voltage generated by the decoder output through the inverter I3 is VDD, the NMOS driving transistor NM1 is controlled to be turned on, and the voltage of the word line WL is VSS. However, since the NMOS driving transistor NM1 is no longer controlled by the output n2 signal of the inverter I2, the capacitive load on the read output voltage vpos_rd of the boost (boost) module is only the capacitive load C WL on the selected row word line, so that the load capacitance is effectively reduced, thereby significantly improving the vpos_rd voltage and the voltage of the selected row word line WL, and reducing the area of the flash memory and the power consumption in the read mode to some extent.
Examples
Taking the existing design circuit as an example, the capacity of the flash memory is 128K Byte, and the flash memory has a single block (bank) structure, and each bank has 512 rows. The wordline driving circuit with the traditional structure and the novel structure of the invention are respectively simulated, other module circuits are kept consistent, and the simulation is carried out under three typical process angles (Corner, TT, typical PMOS, typical NMOS, SS, slow PMOS, slow NMOS and FF, fast PMOS and fast NMOS) to obtain voltage simulation values of the wordlines WL before and after the structure of the wordline driving circuit is changed as shown in the table 1:
TABLE 1 simulation values of WL voltage before and after a change of word line driving circuit
As can be seen from table 1, by using the novel structure word line driving circuit of the present invention, the voltage of the word line WL is significantly improved without increasing the boost (boost) module capacitance, and the problem of reduced or even failed read reliability of the flash memory caused by lower voltage of the word line WL is avoided. Moreover, it is expected that the voltage of the word line WL increases more significantly as the number of rows increases.
In addition, when the flash memory is simulated (the device burner is TT, the power supply voltage Vpower is 1.2V, and the temperature is 25 ℃) to find that when the wordline driving circuit with the conventional structure is used, if the voltage of the wordline WL is raised to be the same as that of the wordline driving circuit with the novel structure, the capacitance area of the boost (boost) module needs to be increased by 60%, and the power consumption of the boost (boost) module needs to be increased by 37.4% in the read mode. From this, it is known that the power consumption and area of the flash memory can be effectively reduced by using the word line driving circuit of the novel structure.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, the scope of the invention is to be indicated by the appended claims.
Claims (3)
1. A flash memory word line driving circuit, comprising:
A first row address selection signal driving circuit for converting a row decoding output control signal generated by processing a row address selection signal by a logic circuit into a high voltage signal capable of driving a word line when a certain row is selected;
A word line selection switch for switching on a read output voltage vpos_rd to a word line of a selected row under control of a high voltage signal output from the row address selection signal driving circuit to read information of the selected row;
A second row address selection signal driving circuit for converting a low level of a row decoding output control signal generated by processing a row address selection signal by a logic circuit into a high level when a row is not selected so as to ground a word line of the unselected row;
The first row address selection signal driving circuit comprises a voltage converter (I1) and a second inverter (I2), wherein a row decoding output control signal is connected to the input end of the voltage converter (I1) and the second row address selection signal driving circuit, the output of the voltage converter (I1) is connected to the input end of the second inverter (I2), the output of the second inverter (I2) is connected to the word line selection switch, and the power negative ends of the voltage converter (I1) and the second inverter (I2) are grounded;
The word line selection switch comprises a PMOS driving tube (PM 1) and an NMOS driving tube (NM 1), wherein the output of the second inverter (I2) is connected to the grid electrode of the PMOS driving tube (PM 1), the source electrode and the substrate of the PMOS driving tube (PM 1) are connected to the read output voltage VPOS_RD, the grid electrode of the NMOS driving tube (NM 1) is connected to the second row address selection signal driving circuit, the source electrode and the substrate of the NMOS driving tube (NM 1) are grounded, and the drain electrode of the PMOS driving tube (PM 1) is connected to the word line WL after being connected with the NMOS driving tube (NM 1);
The second row address selection signal driving circuit comprises a third inverter (I3), wherein the input end of the third inverter (I3) is connected with the row decoding output control signal, the output of the third inverter is connected to the grid electrode of the NMOS driving tube (NM 1), the source electrode of the NMOS driving tube (NM 1) is grounded with the substrate, the positive end of a power supply of the third inverter (I3) is connected with a voltage VDD, and the negative end of the power supply is grounded.
2. A word line driving circuit for a flash memory according to claim 1, wherein when a read operation is performed in said flash memory, said row decode output control signal is changed from "0" at a low level to "1" at a high level for a word line driving circuit for a selected row, an output voltage thereof is raised from VSS to a read output voltage VPOS_RD by said voltage converter (I1), an output voltage of said second inverter (I2) is changed from the read output voltage VPOS_RD to VSS, and said PMOS driving transistor (PM 1) is turned on, and a voltage of the word line WL is raised from VSS to the read output voltage VPOS_RD.
3. A word line driving circuit for a flash memory according to claim 2, wherein for a word line driving circuit for an unselected row, the row decode output control signal is always "0" at a low level, the output voltage of the voltage converter (I1) is VSS through the voltage converter (I1), the output of the second inverter (I2) is VPOS_RD, the PMOS driving transistor (PM 1) is controlled to be turned off, the counter signal voltage generated by the row decode output control signal through the third inverter (I3) is VDD, the NMOS driving transistor (NM 1) is controlled to be turned on, and the voltage of the word line WL is VSS.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110209114.7A CN112885393B (en) | 2021-02-24 | 2021-02-24 | A flash memory word line driving circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110209114.7A CN112885393B (en) | 2021-02-24 | 2021-02-24 | A flash memory word line driving circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112885393A CN112885393A (en) | 2021-06-01 |
| CN112885393B true CN112885393B (en) | 2025-02-07 |
Family
ID=76054745
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110209114.7A Active CN112885393B (en) | 2021-02-24 | 2021-02-24 | A flash memory word line driving circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112885393B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105810247A (en) * | 2016-04-19 | 2016-07-27 | 北京兆易创新科技股份有限公司 | Word line driving circuit |
| CN106158022A (en) * | 2016-07-22 | 2016-11-23 | 上海华力微电子有限公司 | A kind of word line driving circuit for common source framework embedded flash memory and method thereof |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101519061B1 (en) * | 2008-01-21 | 2015-05-11 | 삼성전자주식회사 | Flash memory device having row decoder sharing single high voltage level shift |
| KR101361131B1 (en) * | 2008-04-11 | 2014-02-13 | 삼성전자주식회사 | Flash memory device having shared row decoder |
| JP4913878B2 (en) * | 2009-05-27 | 2012-04-11 | ルネサスエレクトロニクス株式会社 | Word line selection circuit, row decoder |
| KR102131812B1 (en) * | 2013-03-13 | 2020-08-05 | 삼성전자주식회사 | Source line floating circuit, memory device and method of reading data using the same |
| CN106340320B (en) * | 2015-07-15 | 2019-06-21 | 中国科学院微电子研究所 | Memory reading method and reading system |
| CN106504787B (en) * | 2016-10-24 | 2019-07-23 | 上海华力微电子有限公司 | A kind of embedded flash memory and its electric current compare reading circuit |
| CN111768807B (en) * | 2020-06-28 | 2024-06-14 | 上海磁宇信息科技有限公司 | Word line power supply control circuit of magnetic random access memory unit |
| CN112002366B (en) * | 2020-07-30 | 2024-09-03 | 澜智集成电路(苏州)有限公司 | Word line output gating circuit |
| CN111968696B (en) * | 2020-08-27 | 2021-07-06 | 海光信息技术股份有限公司 | Read-only memory circuit and design method thereof, read-only memory and electronic equipment |
-
2021
- 2021-02-24 CN CN202110209114.7A patent/CN112885393B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105810247A (en) * | 2016-04-19 | 2016-07-27 | 北京兆易创新科技股份有限公司 | Word line driving circuit |
| CN106158022A (en) * | 2016-07-22 | 2016-11-23 | 上海华力微电子有限公司 | A kind of word line driving circuit for common source framework embedded flash memory and method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112885393A (en) | 2021-06-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI669714B (en) | Voltage control device and memory system | |
| US6333662B1 (en) | Latch type level shift circuit | |
| JP5642269B2 (en) | Device, method and chip for memory write processing | |
| US6791897B2 (en) | Word line driving circuit | |
| JP5209083B2 (en) | Semiconductor device | |
| CN113870911B (en) | Sense amplifier, storage device and reading and writing method | |
| US10255956B2 (en) | Semiconductor device | |
| CN115565565B (en) | Control circuit, reading and writing method, and memory | |
| CN108962311B (en) | SRAM control circuit and method for sequentially entering and exiting low-power-consumption state | |
| TW559820B (en) | Method to test several word-lines of a semiconductor-memory arrangement | |
| JP3998908B2 (en) | Nonvolatile memory device | |
| US6269046B1 (en) | Semiconductor memory device having improved decoders for decoding row and column address signals | |
| CN112885393B (en) | A flash memory word line driving circuit | |
| JP6287043B2 (en) | Semiconductor memory device | |
| JP2014078305A (en) | Semiconductor storage device | |
| CN112652338B (en) | Line decoder for memory | |
| US11862283B2 (en) | Sense amplifier, storage device and read-write method | |
| CN113129976B (en) | Row decoding circuit and memory | |
| US7102909B2 (en) | Storage circuit, semiconductor device, and electronic apparatus | |
| US6597201B1 (en) | Dynamic predecoder circuitry for memory circuits | |
| CN112652337B (en) | Line decoder for memory | |
| US8547777B2 (en) | Nor logic word line selection | |
| JP4068194B2 (en) | MOS transistor and method for controlling potential of MOS transistor | |
| CN116030854B (en) | Column selection signal control circuit, storage circuit and semiconductor memory | |
| TWI792833B (en) | Apparatus for page-data accessing in memory chip |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant |