CN112864141A - Semiconductor device structure, preparation method and electronic equipment - Google Patents
Semiconductor device structure, preparation method and electronic equipment Download PDFInfo
- Publication number
- CN112864141A CN112864141A CN202110027472.6A CN202110027472A CN112864141A CN 112864141 A CN112864141 A CN 112864141A CN 202110027472 A CN202110027472 A CN 202110027472A CN 112864141 A CN112864141 A CN 112864141A
- Authority
- CN
- China
- Prior art keywords
- chip
- device structure
- bipolar transistor
- insulated gate
- gate bipolar
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 27
- 238000002360 preparation method Methods 0.000 title abstract description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 35
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 35
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 17
- 229910052710 silicon Inorganic materials 0.000 claims description 17
- 239000010703 silicon Substances 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 11
- 229910052782 aluminium Inorganic materials 0.000 claims description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 10
- 229910000679 solder Inorganic materials 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 230000008569 process Effects 0.000 claims description 5
- 238000004806 packaging method and process Methods 0.000 claims description 3
- 238000005520 cutting process Methods 0.000 claims description 2
- 229910001316 Ag alloy Inorganic materials 0.000 claims 1
- 238000011084 recovery Methods 0.000 description 27
- 238000010586 diagram Methods 0.000 description 24
- 230000009286 beneficial effect Effects 0.000 description 3
- 230000009471 action Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 229910052745 lead Inorganic materials 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 229910052718 tin Inorganic materials 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49113—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The embodiment of the application provides a semiconductor device structure, a preparation method and electronic equipment, wherein the semiconductor device structure comprises an insulated gate bipolar transistor chip and a Schottky diode chip, and the insulated gate bipolar transistor chip and the Schottky diode chip are reversely combined and sealed.
Description
Technical Field
The embodiments of the present application relate to the field of semiconductors, and in particular, to a semiconductor device structure, a manufacturing method, and an electronic device.
Background
The Diode is generally a Freewheeling Diode (FWD) which is usually a fast Recovery Diode (frd) on silicon and is connected in reverse parallel with two ends of a single tube of an insulated gate bipolar transistor, and the Freewheeling Diode is used for protecting other elements in a circuit when voltage or current in the circuit suddenly changes.
According to the traditional insulated gate bipolar transistor structure, an insulated gate bipolar transistor chip and a Si-based FRD (fast recovery diode) are sealed, and in the prior art, as a large reverse recovery current with a long time exists during reverse recovery of a freewheeling diode Si-based FRD, the traditional insulated gate bipolar transistor is high in temperature rise, and the system efficiency is greatly reduced. Meanwhile, the existing circuit system is large in size and heavy in weight.
Disclosure of Invention
The embodiment of the application aims to overcome the problems or at least partially solve or alleviate the problems, and the technical scheme provided by the application can reduce power consumption and temperature rise, so that the system efficiency is improved, and equipment is miniaturized and lightened.
In a first aspect, an embodiment of the present application provides a semiconductor device structure, which includes an insulated gate bipolar transistor chip and a schottky diode chip, where the insulated gate bipolar transistor chip and the schottky diode chip are arranged in an inverted and combined manner.
Compared with the prior art, the insulated gate bipolar transistor chip and the Schottky diode chip are fully combined and utilized, so that the power consumption of the insulated gate bipolar transistor chip device can be reduced, the temperature rise can be reduced, and the system efficiency can be improved.
In a second aspect, an embodiment of the present application further provides a method for manufacturing a semiconductor device structure, including obtaining an insulated gate bipolar transistor chip and a schottky diode chip;
and the insulated gate bipolar transistor chip and the Schottky diode chip are reversely combined and sealed.
Compared with the prior art, the beneficial effects of the embodiments provided in the second aspect of the present application are the same as those of the technical solutions in any one of the above aspects, and are not described herein again.
In a third aspect, an embodiment of the present application further provides an electronic device, including the semiconductor device structure according to the first aspect.
Compared with the prior art, the beneficial effects of the embodiments provided in the third aspect of the present application are the same as the beneficial effects of any one of the above technical solutions, and are not described herein again.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. Some specific embodiments of the present application will be described in detail hereinafter by way of illustration and not limitation with reference to the accompanying drawings. The same reference numbers will be used throughout the drawings to refer to the same or like parts or portions, and it will be understood by those skilled in the art that the drawings are not necessarily drawn to scale, in which:
FIG. 1 is a schematic structural diagram of a conventional IGBT device;
FIG. 2 is a schematic diagram of the bridge arm circuit T/4 of the existing IGBT device structure being turned on;
FIG. 3 is a schematic diagram of the bridge arm circuit 2T/4 of the existing IGBT device structure being turned on;
FIG. 4 is a schematic structural diagram of a structure principle of a conventional IGBT device;
FIG. 5 is a waveform diagram of FIG. 3 at time t 1;
FIG. 6 is a schematic current flow diagram of FIG. 3 at time t 1;
FIG. 7 is a waveform diagram of FIG. 3 at time t 2;
fig. 8 is a waveform diagram of fig. 3 at time t3 (a waveform diagram of an IGBT device structure encapsulated with a Si-based FRD at time t 3);
fig. 9 is a schematic structural diagram of an IGBT device provided in the embodiment of the present application;
FIG. 10 is a waveform diagram of an IGBT device structure encapsulated with an SiC SBD at time t3 according to an embodiment of the present application;
fig. 11 is a temperature rise simulation curve diagram when the IGBT device structure of the embodiment of the present application is collocated with a silicon FRD and a silicon carbide SBD;
FIG. 12 is an IF-VF curve of a 1200V 20A Si-based FRD of an embodiment of the present application;
FIG. 13 is a comparison of the curves of SBD IF-VF of SiC of 1200V 10A in the present application;
fig. 14 is a flowchart of a method for manufacturing a semiconductor device structure according to an embodiment of the present disclosure.
Detailed Description
In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only partial embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that, for simplicity, the "insulated gate bipolar transistor chip" is abbreviated as "IGBT", the "silicon-based fast recovery diode" is abbreviated as "FRD", the "schottky diode chip" is abbreviated as "SBD", and the "silicon carbide schottky diode chip" is abbreviated as "SiCSBD".
Referring to fig. 1, fig. 1 is a conventional IGBT device structure, 1 is a substrate, 2 is a Si-based IGBT chip (21 is a Si-based IGBT chip emitter, 22 is a Si-based IGBT chip gate, 3 is a Si-based FRD, 4 is an IGBT device structure gate, 5 is an IGBT device structure collector, 6 is an IGBT device structure emitter, 7 is an aluminum wire connecting the IGBT chip gate and a gate pin, 8 is an aluminum wire connecting the IGBT chip emitter and an emitter pin, 9 is an aluminum wire connecting an FRD anode and an emitter pin, the aluminum wire and the IGBT chip emitter and the FRD anode are connected by bonding, and the IGBT chip collector and the FRD cathode are both welded on the substrate 1 by solder.
Referring to fig. 2, fig. 2 is a schematic diagram of a bridge arm circuit of the IGBT device structure of fig. 1 (also one bridge arm is not shown in fig. 2); in fig. 2, the freewheeling diode is FRD, the load is an inductor L, when T/4 is turned on, a current flows from a to B in the inductor L, and then the PWM wave is controlled to turn off 2T/4, so that no current flows through the circuit indicated by the arrow in fig. 2.
Referring to fig. 3, the current B under the inductor L continues to flow in the original direction; meanwhile, because the current on the circuit is interrupted, the reverse electromotive force can be generated, the reverse electromotive force is added to the positive electrode through a freewheeling diode of the IGBT device structure III, because a filter capacitor is arranged in front of the positive electrode, the reverse electromotive force can charge the capacitor, and thus, the current flows to C, the voltage of the positive electrode cannot rise, the FRD beside the IGBT device structure III works normally, because a larger reverse recovery current with longer time exists during the reverse recovery of the FRD, the temperature rise of the IGBT device structure is higher, the system efficiency is greatly reduced, and if the existing IGBT device structure is used in a radiator, the radiator is large in size, the system is large in size, and the weight is large.
FIG. 4 is a schematic diagram of the operating principle of the IGBT device structure; for the purpose of simplifying the analysis, the gate of the upper IGBT device structure G2 is turned off by applying a negative voltage (but FRDs at both ends thereof can be operated), and the object of the study is the lower IGBT device structure G1, to which the dc pulse voltage Vge is applied.
Referring to fig. 5, fig. 5 is a waveform diagram of fig. 3 at time t 1; at time t0, the gate generates the first pulse, the IGBT device structure G1 is turned on in saturation, the electromotive force U is applied to the load L, the current of the load L rises linearly, and the current expression is: and I is Ut/L. At time t1, the value of the load L current is determined by U and L, and when both U and L are determined, the value of the current is determined by t1, with the longer the time, the greater the current.
Referring to fig. 6, fig. 6 is a schematic diagram of the current flow of fig. 3 at time t1, at time t1, the IGBT device structure G1 is turned off, and the load L current freewheels from the FRD across the IGBT device structure G2, which slowly decays.
Referring to fig. 7, fig. 7 is a waveform diagram of fig. 3 at time t2 (the dotted line in the diagram represents the attenuation of the current flowing through the load L at times t1 to t 2); at time t2, the rising edge of the second pulse arrives, the IGBT device structure G1 is turned on again, the freewheeling diode enters reverse recovery, and the reverse recovery current will pass through the IGBT device structure G1.
Referring to fig. 8, fig. 8 is a waveform diagram of fig. 3 at time t 3; at time t3, the IGBT device structure G1 is turned off again, and at this time, the current is large, and a certain voltage spike is generated due to the existence of the stray inductance.
During FRD reverse recovery, since the total collector current Ic of the IGBT device structure G1 is large (Ic is the sum of the current IL flowing from the load L to G1 and the reverse recovery current IFWD flowing from FRD to G1, i.e., Ic is IL + IFWD), the power consumption vcelc is large, and therefore the IGBT device structure temperature rises, and the system efficiency is low.
In order to reduce power consumption and temperature rise, according to the formula of power consumption, P power consumption is known as VceIc, Ic is required to be reduced, and according to Ic is known as IL + IFWD, IFWD is required to be reduced, FRD causes large reverse recovery current IFWD due to the existence of P +/N-junction. Meanwhile, the reverse recovery time is very long due to the blocking effect of the junction formed at the double-layer epitaxial interface in the drift region. Since the FRD reverse recovery current is large and long in duration, the collector current Ic flowing through the IGBT device structure G1 is large and long in duration, so that the IGBT sealed with the FRD consumes large power.
In order to solve the problem of excessive power consumption of the IGBT device structure, fig. 9 is a schematic structural diagram of the semiconductor device structure proposed in the present application; reference numeral 1 denotes a substrate, 2 denotes a Si-based IGBT chip (where 21 denotes a Si-based IGBT chip emitter, 22 denotes a Si-based IGBT chip gate), 3 denotes an SBD, 4 denotes a Si-based IGBT device structure gate, 5 denotes an IGBT device structure collector, 6 denotes an IGBT device structure emitter, 7 denotes an aluminum wire connecting the IGBT chip gate and a gate pin, 8 denotes an aluminum wire connecting the IGBT chip emitter and an emitter pin, 9 denotes an aluminum wire connecting an SBD anode and an emitter pin, the aluminum wire and the IGBT chip emitter and the SBD anode are connected by bonding, the IGBT chip collector and the SBD cathode are both soldered to the substrate 1 by solder, and the SBD in fig. 9 may be a SiC SBD, which is not limited in the embodiments of the present invention.
Referring to fig. 10, fig. 10 is a waveform diagram of an IGBT device structure encapsulated with a SiC SBD at time t 3; as can be seen from comparison with the waveform diagram of the IGBT device structure sealed with the silicon-based FRD at the time t3 in fig. 8, the IGBT device structure sealed with the silicon-based FRD has a triangular freewheeling diode reverse recovery current with an upward peak at the time t2 (this is only a schematic diagram, and the peak of the actual waveform is in an arc shape). The formation process of the reverse recovery current is as follows: in the process of reverse recovery, reverse voltage is added at the moment of reverse recovery, and at the moment, the freewheeling diode has larger forward current, so that the forward voltage flowing upwards is gradually reduced to zero under the action of the reverse voltage, then the maximum value is gradually reached under the action of a reverse electric field due to the upward flow of multi-photon holes in the drift region, and then the current is gradually reduced to zero due to the recombination of the multi-photon holes. The peak up current is seen in fig. 8, which is the reverse recovery current of the freewheeling diode. However, in the IGBT device structure sealed with the SiC SBD, since the SBD chip has no reverse recovery characteristic at time t2, the triangular freewheeling diode with upward peak in fig. 8 has no reverse recovery current, so that the waveform diagram of the IGBT device structure sealed with the SiC SBD in fig. 10 at time t3 is obtained. This is a great improvement over FRD-sealed IGBTs because the peak value of the reverse recovery current is generally large and long (tens to hundreds of nanoseconds), and the power loss caused by the IGBT device structure is large when the frequency is high.
Referring to fig. 11, fig. 11 is a temperature rise simulation graph of the IGBT device structure in combination with Si-based FRD and SiCSBD; the horizontal axis in fig. 11 represents time in seconds. In fig. 11, after the freewheeling diode matched with the IGBT device structure is replaced by the SiC SBD chip from the Si-based FRD chip, the junction temperature of the IGBT device structure is reduced from 137 ℃ to 110 ℃, and reduced by 27 ℃. The junction temperature of the freewheeling diode is reduced from 79 ℃ to 73 ℃ and 6 ℃. Therefore, after the IGBT device structure is matched with the SiC SBD chip, the influence from reverse recovery is removed due to the turn-on loss of the IGBT device structure, and compared with the matched Si-based FRD chip, the temperature difference is obvious.
Since the SiC SBD chip has no reverse recovery time, the time from forward on to reverse off switching is only tens of ps (Si-based FRD is tens of ns), there is no reverse recovery current of the SiC SBD chip in the collector current of the IGBT device structure. Since the peak value of the reverse recovery current is zero and the duration is zero, the power consumption is obviously reduced.
Because the reverse recovery speed of the SiC SBD chip is very high, the current change rate di/dt is very high, and very large electromotive force at two ends of a load inductor can be caused, so that the SiC SBD chip generates large temperature rise. Because the heat conductivity of SiC is 3.27 times of that of silicon, the SiC SBD chip can quickly discharge the generated heat without heat accumulation, so the SiC SBD chip can bear large di/dt, thereby expanding the safe working area when the IGBT device structure dynamically works.
The current level of the freewheeling diode connected in anti-parallel with the IGBT device structure can be reduced. In one embodiment, in a conventional 1200V 40A IGBT, a 1200V 20A is typically used for Si-based FRD chips. And the SiC SBD chip only needs to adopt 1200V 10A.
Referring to fig. 12 and 13, fig. 12 and 13 compare IF-VF curves for a 1200V 20A Si based FRD chip with a 1200V 10A SiC SBD chip; wherein FIG. 12 is the IF-VF curve for a 1200V 20A Si-based FRD chip, and FIG. 13 is the IF-VF curve for a 1200V 10A SiC SBD chip; as can be seen from fig. 12 and 13, the forward conduction voltage drop VF of the 1200V 20A Si-based FRD chip is equal to about 1.9V (IF 20A, Ta 25 ℃), and the forward conduction voltage drop VF of the 1200V 10A SiC SBD chip is equal to about 1.9V (IF 20A, Ta 25 ℃).
The size of a chip of a freewheeling diode connected with an IGBT chip in an anti-parallel mode can be reduced, and the critical breakdown electric field of the silicon carbide is 12.8 times that of silicon, so that the same voltage level can be achieved, the resistivity of a drift region of the silicon carbide can be much lower than that of the silicon, and therefore the area of the silicon carbide diode can be greatly reduced. In one embodiment, the 1200V 20 ASi-based FRD chip size in the conventional 1200V 40A IGBT device structure is 3.4 × 3.4mm2, while the 1200V 10ASiC SBD chip size employed in the present application is 2.3 × 2.3mm2, which reduces the freewheeling diode chip area by 54%.
Referring to fig. 14, fig. 14 is a flowchart of a method for manufacturing a semiconductor device structure according to an embodiment of the present application, including the following steps:
step S01, obtaining an insulated gate bipolar transistor chip and a Schottky diode chip;
firstly, the IGBT wafer and the SiC SBD wafer are divided into small chips through scribing.
And step S02, the insulated gate bipolar transistor chip and the Schottky diode chip are reversely combined and sealed.
The step S02 specifically includes the following steps,
step S021, connecting the collector of the insulated gate bipolar transistor chip with a substrate by adopting solder, and connecting the cathode of the Schottky diode chip with the substrate by adopting solder;
in the step, the collector of the IGBT chip and the back metal of the SiC SBD, i.e. the cathode, are respectively fixed on the frame substrate, i.e. the collector of the tube, by solder, usually the solder used is Pb90Sn10 (the contents of Pb and Sn are 90% and 10%, respectively), and the solder used in the present case is pb95.5sn2ag2.5 (the contents of Pb, Sn and Ag are 95.5%, 2% and 2.5%, respectively), so as to increase the thermal conductivity of the IGBT device structure, increase the operating junction temperature of the IGBT device structure, and increase the reliability of the operation of the IGBT device structure.
Step S022, connecting the emitter of the silicon-based insulated gate bipolar transistor chip and the anode of the silicon carbide Schottky diode chip with a base pin of the emitter through a first conductive wire and a second conductive wire respectively; and connecting the grid of the silicon-based insulated gate bipolar transistor chip with a grid pin through a third conducting wire.
In the step, the emitter of the IGBT chip and the anode of the SiC SBD chip are connected with the base pin of the emitter of the IGBT device structure through an aluminum wire by a cold welding process (without heating).
And S023, carrying out plastic package on the bonded insulated gate bipolar transistor chip, the bonded Schottky diode chip and the whole frame substrate.
In the step, the IGBT chip and the SiC SBD chip are wrapped by plastic package materials and isolated from the outside.
And S024, cutting ribs of the insulated gate bipolar transistor chip and the Schottky diode chip after plastic packaging, and enabling an emitter pin, a gate tube pin and a collector pin of the insulated gate bipolar transistor to be mutually and independently separated to obtain a semiconductor device structure.
In this step, the whole IGBT is cut into individual single tubes.
Through the semiconductor device structure that this application provided can greatly promote system efficiency, reduce IGBT device structure temperature rise, and can reduce the chip size with the anti-parallelly connected freewheel diode of IGBT chip, under the certain circumstances of base plate size, the reduction of anti-parallelly connected freewheel diode area makes its metal substrate area increase around, more is favorable to the heat dissipation to reduce the temperature rise, also can reduce simultaneously and the anti-parallelly connected freewheel diode's of IGBT chip current rating.
The application also provides an electronic device, wherein the semiconductor device structure provided by the application is arranged in the electronic device.
As the embodiment of the application, the equipment can be a radiator, the size of the radiator of a direct current-alternating current circuit can be reduced by adopting the semiconductor device structure provided by the application, and the loss of the IGBT device structure is reduced by introducing the silicon carbide diode, so that the thermal resistance of the radiator can be increased under the condition of ensuring that the junction temperature does not exceed the safe operation range of the device. Increasing the thermal resistance represents a physical meaning of a reduction in heat sink volume.
According to the invention, the Si-based IGBT chip and the SiC SBD chip are skillfully matched, and the respective characteristics of silicon and silicon carbide are fully combined and utilized, so that the structural performance of the IGBT device is greatly improved.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present application.
Claims (8)
1. The semiconductor device structure is characterized by comprising an insulated gate bipolar transistor chip and a Schottky diode chip, wherein the insulated gate bipolar transistor chip and the Schottky diode chip are reversely combined and sealed.
2. The semiconductor device structure of claim 1, wherein the insulated gate bipolar transistor chip is a silicon-based insulated gate bipolar transistor chip and the schottky diode chip is a silicon carbide schottky diode chip.
3. The semiconductor device structure of claim 2, wherein the emitter of the silicon-based igbt die and the anode of the sic schottky diode die are connected to an emitter pin by a first conductive line and a second conductive line, respectively, to form the emitter of the semiconductor device structure;
the silicon-based insulated gate bipolar transistor chip collector is connected with the substrate to form a collector of the semiconductor device structure; the grid of the silicon-based insulated gate bipolar transistor chip is connected with a grid pin through a third conducting wire to form a grid of the semiconductor device structure;
wherein, the cathode of the silicon carbide Schottky diode chip is connected with the substrate.
4. The semiconductor device structure of claim 3, wherein said first conductive line, said second conductive line, and said third conductive line are aluminum lines.
5. A method for fabricating a semiconductor device structure, comprising,
obtaining an insulated gate bipolar transistor chip and a Schottky diode chip;
and the insulated gate bipolar transistor chip and the Schottky diode chip are reversely combined and sealed.
6. The method for manufacturing a semiconductor device structure according to claim 5, wherein the step of disposing the IGBT chip and the Schottky diode chip in an inverted and combined manner comprises,
connecting the collector electrode of the insulated gate bipolar transistor chip with a substrate by adopting solder, and connecting the cathode of the Schottky diode chip with the substrate by adopting solder;
respectively connecting the emitter of the silicon-based insulated gate bipolar transistor chip and the anode of the silicon carbide Schottky diode chip with an emitter pin through a first conductive wire and a second conductive wire through a bonding process; connecting the grid of the silicon-based insulated gate bipolar transistor chip with a grid pin through a third conducting wire by a bonding process;
plastically packaging the bonded insulated gate bipolar transistor chip, the bonded Schottky diode chip and the whole substrate;
and cutting ribs of the insulated gate bipolar transistor chip and the Schottky diode chip after plastic packaging, so that pins of an emitting electrode, a grid electrode and a collector electrode of the insulated gate bipolar transistor chip are mutually and independently separated, and the semiconductor device structure is obtained.
7. The method of claim 6, comprising wherein the solder is a lead-tin-silver alloy.
8. An electronic device characterized by comprising the semiconductor device structure according to any one of claims 1 to 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110027472.6A CN112864141A (en) | 2021-01-10 | 2021-01-10 | Semiconductor device structure, preparation method and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110027472.6A CN112864141A (en) | 2021-01-10 | 2021-01-10 | Semiconductor device structure, preparation method and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112864141A true CN112864141A (en) | 2021-05-28 |
Family
ID=76002054
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110027472.6A Pending CN112864141A (en) | 2021-01-10 | 2021-01-10 | Semiconductor device structure, preparation method and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112864141A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103065978A (en) * | 2012-12-25 | 2013-04-24 | 佛山市蓝箭电子股份有限公司 | Composite loading ligature method of insulated gate bipolar translator (IGBT) device |
| US20140167060A1 (en) * | 2012-12-14 | 2014-06-19 | Stmicroelectronics S.R.L. | Normally off power electronic component |
| CN107093587A (en) * | 2016-02-17 | 2017-08-25 | 富士电机株式会社 | Semiconductor device and its manufacture method |
| CN110534509A (en) * | 2018-05-24 | 2019-12-03 | 苏州东微半导体有限公司 | Semiconductor power device |
| CN213878088U (en) * | 2021-01-10 | 2021-08-03 | 深圳基本半导体有限公司 | Semiconductor device structure and electronic equipment |
-
2021
- 2021-01-10 CN CN202110027472.6A patent/CN112864141A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20140167060A1 (en) * | 2012-12-14 | 2014-06-19 | Stmicroelectronics S.R.L. | Normally off power electronic component |
| CN103065978A (en) * | 2012-12-25 | 2013-04-24 | 佛山市蓝箭电子股份有限公司 | Composite loading ligature method of insulated gate bipolar translator (IGBT) device |
| CN107093587A (en) * | 2016-02-17 | 2017-08-25 | 富士电机株式会社 | Semiconductor device and its manufacture method |
| CN110534509A (en) * | 2018-05-24 | 2019-12-03 | 苏州东微半导体有限公司 | Semiconductor power device |
| CN213878088U (en) * | 2021-01-10 | 2021-08-03 | 深圳基本半导体有限公司 | Semiconductor device structure and electronic equipment |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10756057B2 (en) | Half-bridge power semiconductor module and method of manufacturing same | |
| US11355477B2 (en) | Power semiconductor module and power conversion device | |
| JP6245365B2 (en) | Half-bridge power semiconductor module and manufacturing method thereof | |
| JP5277579B2 (en) | Semiconductor device | |
| Ikeda et al. | Investigation on wirebond-less power module structure with high-density packaging and high reliability | |
| Robles et al. | The role of power device technology in the electric vehicle powertrain | |
| CN108074917B (en) | Multi-chip parallel half-bridge IGBT module | |
| Hinata et al. | Full SiC power module with advanced structure and its solar inverter application | |
| US9324645B2 (en) | Method and system for co-packaging vertical gallium nitride power devices | |
| US11605613B2 (en) | Semiconductor device | |
| JP2013045974A (en) | Semiconductor module | |
| Marcinkowski | Dual-sided cooling of power semiconductor modules | |
| CN208739041U (en) | A kind of the three phase full bridge circuit and intelligent power module of gallium nitride chip | |
| US12074129B2 (en) | Semiconductor device and fabrication method of the semiconductor device | |
| CN104659025A (en) | Method and system for interleaved boost converter with co-packaged gallium nitride power devices | |
| Wang et al. | Status and trend of power semiconductor module packaging for electric vehicles | |
| CN213878088U (en) | Semiconductor device structure and electronic equipment | |
| Hille et al. | Failure mechanism and improvement potential of IGBT's short circuit operation | |
| Chen et al. | 3.3 kV Low-Inductance Full SiC Power Module | |
| CN112864141A (en) | Semiconductor device structure, preparation method and electronic equipment | |
| Friedrichs | SiC power devices as enabler for high power density-aspects and prospects | |
| CN111969054A (en) | Reverse conducting SiC GTO semiconductor device and preparation method thereof | |
| Mermet-Guyennet et al. | 3D integration of power semiconductor devices based on surface bump technology | |
| CN216849941U (en) | Novel reverse-conducting gallium nitride power device | |
| Christmann et al. | Design considerations for next generation traction drive IGBT based power modules |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |