CN112802528A - Bit line switch circuit of NAND flash memory - Google Patents
Bit line switch circuit of NAND flash memory Download PDFInfo
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- CN112802528A CN112802528A CN202010053803.9A CN202010053803A CN112802528A CN 112802528 A CN112802528 A CN 112802528A CN 202010053803 A CN202010053803 A CN 202010053803A CN 112802528 A CN112802528 A CN 112802528A
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- voltage transistor
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- 238000005520 cutting process Methods 0.000 claims abstract description 3
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- 101100048260 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) UBX2 gene Proteins 0.000 description 8
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- 238000010586 diagram Methods 0.000 description 4
- 101100422768 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) SUL2 gene Proteins 0.000 description 3
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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Abstract
The present invention relates to a bit line switch circuit of a NAND flash memory, which comprises: a selection part including a low voltage transistor to select a bit line when a read mode and a discharge; and a cut-off section between the selection section and the cell array to select one of the pair of bit lines for cutting off the output terminal from being affected by a high voltage applied to the bit line in the erase mode.
Description
Technical Field
The present invention relates to a bit line switch circuit of a NAND flash memory, and more particularly, to a bit line switch circuit of a NAND flash memory capable of improving an integration level by reducing the number of high voltage elements.
Background
In general, a flash memory is a non-volatile memory that retains data after power is turned off. It is commonly used as a portable storage device because of its small size, portability, and better resistance to mechanical shock, direct light, high temperature, and moisture compared to a branched medium or an optical medium.
Flash memories are roughly classified into NAND-type flash memories and NOR-type flash memories. The address lines are provided in units of blocks in the NAND type flash memory, and in units of cells (cells) in the NOR type flash memory.
Therefore, although the NAND flash memory has a disadvantage of being only accessible in blocks, the NAND flash memory has an advantage of being capable of significantly reducing the number of wirings as compared with the NOR flash memory, and realizing high density (high capacity).
Due to these characteristics of the NAND-type flash memory, the NAND-type flash memory is mainly used as a portable storage device.
The operation modes of the flash memory may be divided into a program mode in which electrons are filled in a floating gate (floating gate), an erase (erase) mode in which electrons are removed, and a read mode in which data is read.
The program mode is a process of tunneling or injecting (injection) electrons in a channel region into a floating gate by applying a high voltage to a control gate as a word line. In contrast, the erase mode is a process of moving electrons in the floating gate back into the channel region (substrate) by applying a high voltage to the substrate.
Flash memory is typically not over-writable, so an erase mode must first be performed before new data can be written.
In the read mode, data is determined by reading a change in a Threshold voltage (Threshold voltage) value according to an electronic state in the floating gate.
As described above, in the read mode, data is extracted through the bit lines, and in the erase mode, a high voltage is applied through the bit lines.
Accordingly, the flash memory includes a bit line switch to read data through a bit line or apply a high voltage, releasing a bit line voltage that is raised due to capacitive coupling in an erase mode.
Fig. 1 is a circuit diagram of a bit line switch of a conventional flash memory.
As shown in fig. 1, a conventional flash memory bit line switching circuit 100 includes: a first high voltage transistor HVT1 and a second high voltage transistor HVT2 for selecting one of a pair of bit lines BL1 and BL 2; and a third and a fourth high voltage transistor HVT3, 4 for selectively releasing the voltages of the bit lines BL1, BL2 after an erase operation.
The first and second high voltage transistors HVT1 and HVT2 each have one end connected to an input terminal of the latch section 200 for outputting data and the other end connected to the bit lines BL1 and BL2, respectively, so as to be selectively turned on according to bit line selection signals BL _ SEL1 and BL _ SEL2 to select one of a pair of bit lines BL1 and BL2 to read data.
Further, the erase control section 400 performs an erase operation by applying a high voltage to one of the pair of bit lines BL1, BL2, the applied high voltage causing the voltages of the bit lines BL1, BL2 to rise.
The third and fourth high voltage transistors HVT3 and HVT4 of the bit line switch circuit 100 are selectively turned on according to the discharge select signals DSC _ SEL1, DSC _ SEL2 to release the bit line voltage.
The conventional bit line switch circuit 100 configured as described above includes four high voltage transistors to cut off a high voltage applied when the erase control part 400 performs an erase operation, so that it does not affect the latch part 200, which is a data output terminal.
It is known that a high-voltage transistor is formed in a larger area than a low-voltage transistor, and thus the integration degree is lower.
Fig. 1 shows a bit line switch circuit 100 for a pair of bit lines, and in order to implement the bit line switch circuit 100 in the entire flash memory, a sufficient area needs to be provided, so that there is a problem in that the integration degree is lowered.
Disclosure of Invention
Technical problem
The present invention is directed to a bit line switch circuit capable of reducing the number of high voltage transistors.
Technical scheme
In order to solve the above problems, a bit line switch circuit of a NAND flash memory of the present invention includes: a selection part including a low voltage transistor to select a bit line when a read mode and a discharge; and a cut-off part between the selection part and the cell array to select one of the pair of bit lines to cut off the output terminal from being affected by a high voltage applied to the bit line in the erase mode.
In an embodiment of the present invention, the selection part may include: the first low-voltage transistor and the second low-voltage transistor are respectively connected with the output end at one end and different bit lines at the other end; and a third low voltage transistor and a fourth low voltage transistor having one ends respectively connected to different bit lines and the other ends connected to each other to form a discharging terminal.
In an embodiment of the present invention, the cut-off part may include a first high voltage transistor and a second high voltage transistor that are respectively connected in series to different bit lines of a pair of bit lines.
Advantageous effects
According to the present invention, even if the number of high voltage transistors is reduced, it is possible to prevent the high voltage in the erase mode from affecting the output terminal, and to stably discharge the bit line voltage raised at the time of the erase operation, thereby having an effect that the integration can be improved.
Drawings
FIG. 1 is a circuit diagram of a bit line switch of a conventional NAND flash memory;
FIG. 2 is a circuit diagram of a bit line switch of the NAND flash memory of the present invention.
[ description of reference numerals ]
10 bit line switch circuit; 11, a selection part; 12, a cutting part.
Detailed Description
Hereinafter, a bit line switch circuit of a NAND flash memory of the present invention will be described in detail with reference to the accompanying drawings.
The embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art, and the embodiments described below may be modified into other various forms, and the scope of the present invention is not limited to the following embodiments. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.
The terminology used in the description is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification, the singular includes the plural unless an exception is explicitly stated. Furthermore, the use of "comprising" and/or "comprising" in this specification is intended to specify the presence of stated shapes, integers, steps, operations, elements, components, and/or combinations thereof, but does not preclude the presence or addition of one or more other shapes, integers, operations, elements, components, and/or combinations thereof. As used in this specification, the term "and/or" includes any and all combinations of one or more of the enumerated items.
The terms first, second, etc. are used in this specification to describe various elements, regions and/or sections, but it should be understood that these elements, components, regions, layers and/or sections are not limited by these terms. These terms do not imply any particular order, context, or relative merits and are only used to distinguish one element, region, or location from another element, region, or location. Thus, a first element, region or section discussed below could be termed a second element, region or section without departing from the teachings of the present invention.
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings, which schematically illustrate embodiments of the invention. Variations from the shapes of the illustrations as a function, for example, of manufacturing techniques and/or tolerances, are to be expected in the drawings. Therefore, it is to be understood that embodiments of the present invention are not limited to the particular shapes of regions illustrated in the present specification, but are intended to include changes in shapes that result, for example, from manufacturing.
Fig. 2 is a circuit diagram of a bit line switch of a NAND flash memory according to a preferred embodiment of the present invention.
As shown in fig. 2, a bit line switch circuit 10 of a NAND flash memory according to a preferred embodiment of the present invention includes: a selection part 11 including low voltage transistors T1, T2, T3, and T4 to select the bit lines BL1, BL2 when a read mode and discharge; and a cut-off section 12 for selecting the bit lines BL1, BL2 between the selection section 11 and the cell array 30 to cut off the output terminal from being affected by a high voltage applied to the bit lines in the erase mode.
The selection unit 11 includes: a first low-voltage transistor T1 and a second low-voltage transistor T2, each having one end connected to the latch unit 20 and the other end connected to different bit lines BL1 and BL2, respectively; and a third low voltage transistor T3 and a fourth low voltage transistor T4, one ends of which are connected to different bit lines BL1 and BL2, respectively, and the other ends of which are connected to each other to form a discharging terminal.
The cut-off portion 12 includes a first high voltage transistor HVT1 and a second high voltage transistor HVT2, the first high voltage transistor HVT1 and the second high voltage transistor HVT2 being connected in series to different ones of a pair of bit lines BL1, BL2, respectively.
Hereinafter, with respect to the bit line switch circuit of the NAND flash memory according to the preferred embodiment of the present invention structured as described above, the structure and action thereof will be described in more detail.
First, unlike the conventional switching circuit, the bit line switching circuit 10 of the NAND flash memory of the present invention includes two high voltage transistors and four low voltage transistors.
Although the number of low voltage transistors is increased and the total number of transistors is increased compared to the related art, it is known that one high voltage transistor requires a larger formation area than two low voltage transistors.
In a read operation, the bit line BL1 may be selected by the first low-voltage transistor T1 turned on according to the bit line select signal BL _ SEL1 and the first high-voltage transistor HVT1 turned on according to the select signal SEL 1.
At this time, the bit line select signal BL _ SEL1 and the select signal SEL1 are select signals having different voltage levels but the same waveform.
Except for the first low voltage transistor T1 and the first high voltage transistor HVT1, which are turned on, the other transistors are in an off (turn off) state.
Data in a memory cell selected by a word line (not shown) is read through a bit line BL1, and the read data is output from the latch section 20 at the output terminal.
The selection part 11 selects one of the bit lines BL1 and BL2 through the first and second low-voltage transistors T1 and T2 so that data of the cell array 30 can be read in a read mode in which the first and second low-voltage transistors T1 and T2 are controlled to be turned on or off according to the bit line selection signals BL _ SEL1 and BL _ SEL 2.
The selector 11 can select the bit lines BL1 and BL2 to be discharged.
After the erase operation, the voltages of the bit lines BL1 and BL2, i.e., the bit line voltages, are raised, and the bit line voltages are discharged to the discharge terminal by the third and fourth low-voltage transistors T3 and T4 controlled to be turned on/off according to the discharge selection signals DSC _ SEL1 and DSC _ SEL 2.
At this time, the first high voltage transistor HVT1 or the second high voltage transistor HVT2 located in the bit line selected to be the discharge mode is turned on, so that the selected bit line voltage can be released. In this case, the third low voltage transistor T3 or the fourth low voltage transistor T4 is turned on/off by the discharge selection signals DSC _ SEL1 and DSC _ SEL2, and the bit line of the discharge mode is selected by the third low voltage transistor T3 or the fourth low voltage transistor T4.
As such, the low voltage operation without using the high voltage transistor is performed in the read mode and the discharge mode, in which the bit lines BL1, BL2 are selected by using four low voltage transistors in the present invention.
In the read mode and the discharge mode, the first high-voltage transistor HVT1 and the second high-voltage transistor HVT2 of the cut-off section 12 are used only to control the connection of the selection section 11 to the bit lines BL1, BL 2.
In the erase mode, the erase control section 40 selects one of the pair of bit lines BL1 and BL2 to apply a high voltage necessary for erasing, at which time the high voltage applied to the bit line through the cut-off section 12 is cut off from affecting the output terminal.
That is, both the first high-voltage transistor HVT1 and the second high-voltage transistor HVT2 of the cutoff unit 12 are in an off state, and the output terminal is influenced by the high voltage required for the cutoff erasing due to the characteristics of the high-voltage transistors.
Therefore, the present invention can stably perform the writing, reading and discharging modes while reducing the number of high voltage transistors, and can prevent the high voltage in the erasing mode from affecting the output terminal.
The present invention realizes a reduction in a formation area by reducing the number of high voltage transistors even in the case where the number of low voltage transistors is increased, thereby having an effect that an integration degree can be improved.
It will be apparent to those skilled in the art that the present invention is not limited to the above embodiments, and that the present invention can be implemented by various modifications and variations within a scope not departing from the technical spirit of the present invention.
Claims (3)
1. A bit line switch circuit for a NAND flash memory, comprising:
a selection part including a low voltage transistor to select a bit line when a read mode and a discharge; and
and a cut-off part between the selection part and the cell array to select one of the pair of bit lines for cutting off the output terminal from being affected by a high voltage applied to the bit line in the erase mode.
2. The bit line switch circuit of the NAND flash memory according to claim 1,
the selection section includes:
the first low-voltage transistor and the second low-voltage transistor are respectively connected with the output end at one end and are respectively connected with different bit lines at the other end; and
and a third low voltage transistor and a fourth low voltage transistor each having one end connected to a different bit line and the other end connected to each other to form a discharge terminal.
3. The bit line switch circuit of the NAND flash memory according to claim 1,
the cut-off portion includes a first high-voltage transistor and a second high-voltage transistor, which are respectively connected in series to different bit lines of a pair of bit lines.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-2019-0145195 | 2019-11-13 | ||
| KR1020190145195A KR20210059081A (en) | 2019-11-13 | 2019-11-13 | Bit-line switch circuit for NAND-flash memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112802528A true CN112802528A (en) | 2021-05-14 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010053803.9A Pending CN112802528A (en) | 2019-11-13 | 2020-01-17 | Bit line switch circuit of NAND flash memory |
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| KR (1) | KR20210059081A (en) |
| CN (1) | CN112802528A (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020050366A (en) * | 2000-12-21 | 2002-06-27 | 박종섭 | Operating circuit for bitline in a flash memory device |
| CN1674158A (en) * | 2004-03-25 | 2005-09-28 | 三星电子株式会社 | Semiconductor device for reducing coupling noise |
| CN101038922A (en) * | 2006-02-17 | 2007-09-19 | 三星电子株式会社 | Nonvolatile memory device and operation method of device |
| KR20080029302A (en) * | 2006-09-28 | 2008-04-03 | 주식회사 하이닉스반도체 | Flash memory device |
| JP5883494B1 (en) * | 2014-11-19 | 2016-03-15 | ウィンボンド エレクトロニクス コーポレーション | Nonvolatile semiconductor memory device |
| CN105989886A (en) * | 2015-02-16 | 2016-10-05 | 华邦电子股份有限公司 | Nonvolatile semiconductor memory device |
| CN106158037A (en) * | 2014-12-08 | 2016-11-23 | 华邦电子股份有限公司 | Reading method of NAND flash memory and NAND flash memory |
| CN108630254A (en) * | 2017-03-22 | 2018-10-09 | 三星电子株式会社 | The non-volatile memory device of the data linear load reduced is provided |
-
2019
- 2019-11-13 KR KR1020190145195A patent/KR20210059081A/en unknown
-
2020
- 2020-01-17 CN CN202010053803.9A patent/CN112802528A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020050366A (en) * | 2000-12-21 | 2002-06-27 | 박종섭 | Operating circuit for bitline in a flash memory device |
| CN1674158A (en) * | 2004-03-25 | 2005-09-28 | 三星电子株式会社 | Semiconductor device for reducing coupling noise |
| CN101038922A (en) * | 2006-02-17 | 2007-09-19 | 三星电子株式会社 | Nonvolatile memory device and operation method of device |
| KR20080029302A (en) * | 2006-09-28 | 2008-04-03 | 주식회사 하이닉스반도체 | Flash memory device |
| JP5883494B1 (en) * | 2014-11-19 | 2016-03-15 | ウィンボンド エレクトロニクス コーポレーション | Nonvolatile semiconductor memory device |
| CN106158037A (en) * | 2014-12-08 | 2016-11-23 | 华邦电子股份有限公司 | Reading method of NAND flash memory and NAND flash memory |
| CN105989886A (en) * | 2015-02-16 | 2016-10-05 | 华邦电子股份有限公司 | Nonvolatile semiconductor memory device |
| CN108630254A (en) * | 2017-03-22 | 2018-10-09 | 三星电子株式会社 | The non-volatile memory device of the data linear load reduced is provided |
Non-Patent Citations (1)
| Title |
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| HENRY OM’MANI;MANDANA TADAYONI;NITYA THOTA;IAN YUE;NHAN DO;: "用分离栅极闪存单元实现可编程逻辑阵列", 中国集成电路, no. 12, 5 December 2014 (2014-12-05) * |
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| KR20210059081A (en) | 2021-05-25 |
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