CN112787633B - Duty ratio calibration circuit, high-speed interface circuit, processor and electronic equipment - Google Patents
Duty ratio calibration circuit, high-speed interface circuit, processor and electronic equipment Download PDFInfo
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- CN112787633B CN112787633B CN202011557434.3A CN202011557434A CN112787633B CN 112787633 B CN112787633 B CN 112787633B CN 202011557434 A CN202011557434 A CN 202011557434A CN 112787633 B CN112787633 B CN 112787633B
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Abstract
The embodiment of the application provides a duty cycle calibration circuit, high-speed interface circuit, treater and electronic equipment, wherein, this duty cycle calibration circuit includes: the circuit comprises an oscillator, a frequency divider, a data selector, a driver, a filter, a comparator, a finite state machine, an enhancement module, an alternating current coupling capacitor and a pre-driver; the oscillator is connected with the frequency divider; the frequency divider is connected with the first input end of the data selector; the pre-driver is connected with the second input end of the data selector; the output end of the data selector is connected with the driver; the driver is connected with the filter; the filter is connected with the first input end of the comparator; the output end of the comparator is connected with the finite-state machine; the finite state machine is connected with a first end of the enhancement module, a second end of the enhancement module is connected with a first end of the driver, the enhancement module is connected with one end of the alternating current coupling capacitor, the other end of the alternating current coupling capacitor is connected with the driver, and the enhancement module and the alternating current coupling capacitor are used for controlling the switching of signal rising or falling.
Description
Technical Field
The application relates to the technical field of chip design, in particular to a duty ratio calibration circuit, a high-speed interface circuit, a processor and electronic equipment.
Background
The quality of an output signal of a high-speed interface circuit influences the working rate of the high-speed interface circuit (SerDes), and the quality of an input signal and an output signal of the high-speed interface circuit can be influenced by the mismatch of the output duty ratio of an input interface and an output interface. However, in the current prior art, the output signal of the high-speed input/output circuit may be affected by the structure in the circuit, which may cause the duty ratio mismatch of the output signal.
Disclosure of Invention
An object of the present application is to provide a duty ratio calibration circuit, a high-speed interface circuit, a processor, and an electronic device, which can solve the problem of output signal mismatch caused by the high-speed interface circuit.
In a first aspect, an embodiment of the present application provides a duty ratio calibration circuit, including: the circuit comprises an oscillator, a frequency divider, a data selector, a driver, a filter, a comparator, a finite state machine, an enhancement module, an alternating current coupling capacitor and a pre-driver;
the oscillator is connected with the first end of the frequency divider;
the second end of the frequency divider is connected with the first input end of the data selector;
the pre-driver is connected with the second input end of the data selector;
the output end of the data selector is connected with the first end of the driver;
the second end of the driver is connected with the first end of the filter;
the second end of the filter is connected with the first input end of the comparator;
the output end of the comparator is connected with the first end of the finite-state machine;
the second end of the finite-state machine is connected with the first end of the enhancement module, the second end of the enhancement module is connected with the first end of the driver, the third end of the enhancement module is connected with the first end of the alternating-current coupling capacitor, the second end of the alternating-current coupling capacitor is connected with the second end of the driver, and the enhancement module and the alternating-current coupling capacitor are used for controlling the switching of signal rising or falling.
In an alternative embodiment, the enhancement module comprises: an ascending enhancement module and a descending enhancement module;
the ascent enhancement module includes: a first adjustable buffer and a first transistor;
the droop enhancing module includes: a second adjustable buffer and a second transistor;
the first control end of the first adjustable buffer and the first control end of the second adjustable buffer are used as the first end of the enhancement module and are connected with the second end of the finite-state machine;
the second control end of the first adjustable buffer and the second control end of the second adjustable buffer are used as the second end of the enhancement module and are connected with the first end of the driver;
the output end of the first adjustable buffer is connected with the first transistor;
the output end of the second adjustable buffer is connected with the second transistor;
and the output ends of the first transistor and the second transistor are used as the third end of the enhancement module and are connected with the first end of the alternating current coupling capacitor.
In this embodiment, the rising enhancement module and the falling enhancement module are respectively used for controlling the switching time of the rising edge and the switching time of the falling edge, the duty ratio of the signal is adjusted by changing the switching time of the rising edge or the falling edge, and the signal quality can be improved by adjusting the output duty ratio of the signal input/output signal.
In an alternative embodiment, the first adjustable buffer comprises: a first transistor array, a second transistor array, a third transistor, and a fourth transistor;
the grid electrode of each transistor in the first transistor array and the grid electrode of each transistor in the second transistor array are used as first control ends of the first adjustable buffer and connected with the second end of the finite-state machine;
the grid electrode of the third transistor and the grid electrode of the fourth transistor are used as second control ends of the enhancement modules and connected with the first end of the driver;
the drain of the third transistor and the drain of the fourth transistor are connected to the first transistor as the output of the first adjustable buffer.
In this embodiment, the adjustable buffer in the above configuration can enhance the first transistor, and after the first transistor is enhanced, the rising of the input/output signal is switched by the ac coupling capacitor, so that the rising width can be reduced, and the input/output signal can be adjusted.
In an alternative embodiment, each of the transistors in the first transistor array and the third transistor is a PMOS transistor;
and each transistor and the fourth transistor in the second transistor array are NMOS transistors.
In an alternative embodiment, the filter comprises: the control switch, the first resistor and the first capacitor are connected;
a first end of the control switch is used as a first end of the filter and is connected with a second end of the driver, the other end of the control switch is connected with a first end of the first resistor, a second end of the first resistor is connected with a first end of the first capacitor, and a second end of the first capacitor is grounded;
the second end of the first resistor is connected as the second end of the filter with the first input end of the comparator.
In the present embodiment, the accuracy of the duty ratio adjustment can be improved by filtering the waveform with a filter.
In an alternative embodiment, the driver comprises: a fifth transistor and a sixth transistor;
the grid electrode of the fifth transistor and the grid electrode of the sixth transistor are used as first ends of the drivers and are connected with the output end of the data selector;
the drain electrode of the fifth transistor and the drain electrode of the sixth transistor are used as second ends of the drivers and are connected with the first end of the filter;
the source electrode of the fifth transistor is connected with a power supply;
the source of the sixth transistor is grounded.
In an alternative embodiment, the frequency divider is a divide-by-two divider.
In an optional embodiment, the method further comprises: a second resistor;
a first end of the second resistor is connected between the filter and the driver;
and the second end of the second resistor is grounded.
In an optional embodiment, the method further comprises: a first diode and a second diode;
the anode of the first diode is connected with a power supply;
the cathode of the first diode is connected with the anode of the second diode and connected between the second resistor and the filter;
and the cathode of the second diode is grounded.
In this embodiment, the first diode and the second diode are added to form a protection tube for electrostatic discharge, thereby improving the safety of the circuit.
In an optional embodiment, the method further comprises: a third resistor;
one end of the third resistor is connected between the alternating current coupling capacitor and the driver, and the other end of the third resistor is grounded;
or one end of the third resistor is connected between the cathode of the first diode and the anode of the second diode, and the other end of the third resistor is grounded.
In this embodiment, the third resistor is provided, so that impedance matching can be improved and the quality of a signal can be improved.
In a second aspect, an embodiment of the present application provides a high-speed interface circuit, including: the device comprises a clock module, a sending module and a receiving module;
the sending module comprises: the serializer is connected with the pre-driver of the duty ratio calibration circuit.
In a third aspect, an embodiment of the present application provides a processor, including: the high-speed interface circuit is described above.
In a fourth aspect, an embodiment of the present application provides an electronic device, including:
the processor described above;
a memory storing machine readable instructions executable by the processor.
The beneficial effects of the embodiment of the application are that: the correction circuit structure capable of adjusting the duty ratio of the signal is additionally arranged at the driver, the duty ratio is changed by changing the slew rate of the output stage and the strength of the alternating current coupling capacitor, so that the mismatch of the rising edge and the falling edge of the transistor of the driver is corrected, and the working rate of input and output can be improved.
Drawings
To more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and those skilled in the art can also obtain other related drawings based on the drawings without inventive efforts.
Fig. 1 is a circuit schematic diagram of a duty cycle calibration circuit according to an embodiment of the present application.
Fig. 2 is a signal waveform diagram of a filter calibration signal of a duty ratio calibration circuit according to an embodiment of the present disclosure.
Fig. 3 is another circuit schematic diagram of a duty cycle calibration circuit according to an embodiment of the present disclosure.
Fig. 4 is a circuit schematic diagram of a first adjustable buffer of a duty cycle calibration circuit according to an embodiment of the present disclosure.
Fig. 5 is a circuit diagram of a high-speed interface circuit according to an embodiment of the present disclosure.
Description of the main element symbols: 100-duty cycle calibration circuit; 110-a voltage controlled oscillator; 130-frequency divider; 140-a driver; 150-a filter; 160-a comparator; 170-a finite state machine; 180-predriver; 190-an enhancement module; k1-control switch; r1-a first resistor; r2-a second resistor; r3-a third resistor; c1-a first capacitor; C2-AC coupling capacitance; d1-a first diode; d2-a second diode; m1-a first transistor; m2-a second transistor; MS1 — first transistor array; MS2 — second transistor array; m3-a third transistor; m4-a fourth transistor; m5-a fifth transistor; m6-a sixth transistor; UP 1-first adjustable buffer; DP 1-a second adjustable buffer; 210-a phase-locked loop; 220-duty cycle calibrator; 300-a sending module; 400-a receiving module; 310-a serializer; 410-an analog front end of a receiver; 420-a sampler; 430-clock phase adjuster; 440-deserializer.
Detailed Description
The technical solution in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
Currently, the mismatch of the duty cycle of the signal output of a general high-speed interface circuit may be caused by the following reasons: clock duty cycle mismatch. The clock duty mismatch may be corrected with a clock duty cycle corrector (clock duty cycle corrector).
However, even if the input clock is already at 50% duty cycle, there are other reasons that the rising/falling (Tr/Tf) of the output signal of the interface does not match, resulting in the final output duty cycle of the input-output interface deteriorating.
Through research, the mismatch of the sizes of the pipes of the pre-driver 180 and the driver 140 of the high-speed interface circuit can cause the mismatch of the rise/fall (Tr/Tf) of the input/output signal, and the duty ratio of the output signal is affected, and finally the quality of the output signal of the input/output interface is affected. Based on this research, the embodiments of the present application provide a duty cycle calibration circuit, a high speed interface circuit, a processor, and an electronic device. This is described below by means of several examples.
Example one
An embodiment of the present application provides a duty ratio calibration circuit, as shown in fig. 1, the duty ratio calibration circuit 100 may include: an Oscillator (OSC), a frequency divider 130, a data selector (DC), a Driver 140 (Driver), a Filter 150 (Filter), a Comparator 160 (Comparator), a finite state machine 170 (FSM), an enhancement module 190, an ac coupling capacitor C2 (accumulator), and a Pre-Driver 180 (Pre-Driver).
In this embodiment, an oscillator is connected to the first end of the frequency divider 130; the second terminal of the frequency divider 130 is connected to the first input terminal of the data selector. Illustratively, the oscillator and the frequency divider 130 may be combined into a circuit capable of frequency division.
The oscillator may be a voltage controlled oscillator 110.
Illustratively, the pre-driver 180 is connected to a second input of the data selector; the output terminal of the data selector is connected to the first terminal of the driver 140; a second end of the driver 140 is connected to a first end of the filter 150; a second terminal of the filter 150 is connected to a first input terminal of the comparator 160; the output of the comparator 160 is connected to a first terminal of the finite state machine 170; a second terminal of the finite state machine 170 is connected to the first terminal of the boost module 190, a second terminal of the boost module 190 is connected to the first terminal of the driver 140, a third terminal of the boost module 190 is connected to the first terminal of the ac coupling capacitor C2, and a second terminal of the ac coupling capacitor C2 is connected to the second terminal of the driver 140.
In this embodiment, the boost module 190 and the ac coupling capacitor C2 are used to control the switching of the rising or falling of the signal.
Illustratively, one end of the boost module 190 may be connected to a power source, and the other end of the boost module 190 may be grounded.
In this embodiment, the filter 150 is used for filtering the received signal. The filter 150 can effectively filter the frequency point of the specific frequency or frequencies other than the frequency point to obtain a power signal of the specific frequency, or eliminate the power signal of the specific frequency. Filter 150 may pass certain frequency components of the signal while substantially attenuating other frequency components. By using the frequency-selective action of the filter 150, it is possible to filter out interference noise or perform spectral analysis.
Illustratively, as shown in fig. 2, when the length of the rising segment of the input/output signal is greater than the length of the falling segment, that is, the duty ratio of the input/output signal is less than 50%, the filtered voltage of the filter 150 is less than VDD/4. As shown in the left diagram of fig. 2, the filtered waveform is below the reference line VDD/4. When the length of the rising segment of the input/output signal is smaller than the length of the falling segment, that is, the duty ratio of the input/output signal is greater than 50%, the filtered voltage through the filter 150 is greater than VDD/4. As shown in the right diagram of fig. 2, the filtered waveform is above the reference line VDD/4.
In this embodiment, the comparator 160 is configured to compare the voltage filtered by the filter 150 with a reference voltage k × vref. In the example shown in fig. 1, the comparator 160 compares the filtered voltage of the filter 150 with a reference voltage vref/4. In this embodiment, the voltage vref is VDD. The comparator 160 is used for comparing the voltages of the two input terminals, wherein the magnitude relationship between the two input voltages is represented by the high or low level of the output voltage. When the voltage at the non-inverting input terminal (+) is higher than the voltage at the inverting input terminal (-), the output terminal of the comparator 160 is at a high level; when the voltage at the non-inverting input terminal (+) is lower than the inverting input terminal (-), the output terminal of the comparator 160 is at a low level.
In this embodiment, the filter 150 may be connected to the non-inverting input terminal of the comparator 160, or may be connected to the inverting input terminal of the comparator 160, specifically according to actual requirements.
For example, in the example shown in fig. 1, the filter 150 is connected to the inverting input of the comparator 160. In this example, when the length of the rising segment of the input/output signal is smaller than that of the falling segment, the filtered voltage of the filter 150 is greater than VDD/4, and the voltage at the non-inverting input terminal (+) of the comparator 160 is lower than that at the inverting input terminal (-) at this time, the output of the comparator 160 is low. When the length of the rising segment of the input/output signal is greater than the length of the falling segment, that is, the duty ratio of the input/output signal is less than 50%, the filtered voltage of the filter 150 is less than VDD/4, and the (+) voltage of the non-inverting input terminal of the comparator 160 is higher than the (-) voltage of the inverting input terminal, the output of the comparator 160 is at a high level.
For another example, the filter 150 may also be connected to the non-inverting input of the comparator 160. In this example, when the length of the rising segment of the input/output signal is smaller than that of the falling segment, and the filtered voltage of the filter 150 is greater than VDD/4, the voltage at the non-inverting input terminal (+) of the comparator 160 is higher than that at the inverting input terminal (-) and the output of the comparator 160 is high. When the length of the rising segment of the input/output signal is greater than the length of the falling segment, that is, the duty ratio of the input/output signal is less than 50%, the filtered voltage of the filter 150 is less than VDD/4, and the voltage of the non-inverting input terminal (+) of the comparator 160 is lower than the voltage of the inverting input terminal (-) at this time, the output terminal of the comparator 160 is at a low level.
Alternatively, the filtered voltage of the filter 150 may have other values, but the voltage value input to the input terminal of the comparator 160 corresponding to the input reference voltage is different. Illustratively, the voltage value input to the input of the comparator 160 for inputting the reference voltage is equal to the filtered voltage threshold of the filter 150. The threshold value may be VDD/4 as described in the above example.
In this embodiment, the finite state machine 170 is preset with a finite number of states, and the finite state machine 170 switches among the finite number of states.
Illustratively, as shown in fig. 2, the enhancement module 190 includes: an ascending enhancement module 190 and a descending enhancement module 190.
Optionally, the boost enhancement module 190 includes: a first adjustable buffer UP1 and a first transistor M1.
Optionally, the droop enhancement module 190 includes: a second adjustable buffer DP1 and a second transistor M2.
Illustratively, a first control terminal of the first adjustable buffer UP1 and a first control terminal of the second adjustable buffer DP1 are used as a first terminal of the enhancement module 190, and are connected to a second terminal of the finite state machine 170; the second control terminal of the first adjustable buffer UP1 and the second control terminal of the second adjustable buffer DP1 are used as the second terminal of the enhancement module 190, and are connected to the first terminal of the driver 140; the output terminal of the first adjustable buffer UP1 is connected to the first transistor M1; the output terminal of the second adjustable buffer DP1 is connected to the second transistor M2; the output terminals of the first transistor M1 and the second transistor M2 are used as the third terminal of the boost module 190, and are connected to the first terminal of the ac coupling capacitor C2.
Illustratively, the output terminal of the first adjustable buffer UP1 is connected to the gate of the first transistor M1. The output terminal of the second adjustable buffer DP1 is connected to the gate of the second transistor M2.
In one embodiment, as shown in fig. 3, the filter 150 may include: the control switch K1, the first resistor R1 and the first capacitor C1.
Illustratively, a first terminal of the control switch K1 is connected to a second terminal of the driver 140 as a first terminal of the filter 150, a second terminal of the control switch is connected to a first terminal of the first resistor R1, a second terminal of the first resistor R1 is connected to a first terminal of the first capacitor C1, and a second terminal of the first capacitor C1 is grounded; a second terminal of the first resistor R1 is connected as a second terminal of the filter 150 to a first input terminal of the comparator 160.
Illustratively, the opening or closing of the control switch K1 is used as a basis for a data selector selection signal. When the control switch K1 is closed, the selection terminal of the data selector selects the signal input by the high-level input terminal, and when the control switch is open, the selection terminal of the data selector selects the signal input by the low-level input terminal.
Optionally, the driver 140 comprises: a fifth transistor M5 and a sixth transistor M6.
Illustratively, the gate of the fifth transistor M5 and the gate of the sixth transistor M6 are used as the first end of the driver 140, and are connected to the output end of the data selector; the drain of the fifth transistor M5 and the drain of the sixth transistor M6 are used as the second end of the driver 140, and are connected to the first end of the filter 150; the source of the fifth transistor M5 is connected to a power supply; the source of the sixth transistor M6 is grounded.
Alternatively, the fifth transistor M5 may be a PMOS transistor, and the sixth transistor M6 may be an NMOS transistor.
For example, when the driving capability ratios of the fifth transistor M5 and the sixth transistor M6 of the driver 140 are not balanced, the lengths of the rising segment and the falling segment of the output signal of the input/output interface are not equal, and the duty ratio mismatch of the output signal of the input/output interface may be caused.
In this embodiment, in order to solve the problem that the duty ratio of the output signal of the input/output interface may be mismatched when the driving capability ratios of the fifth transistor M5 and the sixth transistor M6 are unbalanced, the length of the rising section or the length of the falling section of the signal may be reduced through the effect of the enhancing module 190 and the ac coupling capacitor C2.
Optionally, the frequency divider 130 is a divide-by-two frequency divider 130. Illustratively, the divide-by-two divider 130 is used to reduce the frequency of the single frequency signal to 1/2 of the original frequency, so as to implement the divide-by-two.
Illustratively, the data selector may be a 1-out-of-2 data selector. The first input terminal of the data selector may be a high level input terminal, and the second input terminal of the data selector may be a low level input terminal.
Illustratively, when the data selector selects low level 0 input by the low level input terminal, the output terminal of the data selector will output the input signal on I0; on the contrary, when the data selector selects the high level 1 input by the high level input terminal, the output terminal of the data selector will output the input signal on I1.
In one embodiment, as shown in fig. 4, the first adjustable buffer UP1 includes: a first transistor array, a second transistor array, a third transistor M3, and a fourth transistor M4.
Illustratively, the gates of the transistors in the first transistor array MS1 and the gates of the transistors in the second transistor array MS2 are connected to the second terminal of the finite state machine 170 as the first control terminal of the first adjustable buffer UP 1.
The gate of the third transistor M3 and the gate of the fourth transistor M4 are connected to the first terminal of the driver 140 as the second control terminal of the boost module 190.
The drain of the third transistor M3 and the drain of the fourth transistor M4 are connected to the gate of the first transistor M1 as the output terminal of the first adjustable buffer UP 1.
Optionally, each transistor in the first transistor array MS1 and the third transistor M3 are PMOS transistors.
Optionally, each transistor in the second transistor array MS2 and the fourth transistor M4 are NMOS transistors.
In this embodiment, the PMOS transistors in the first transistor array MS1 can be arranged in parallel. The source electrode of each PMOS tube is connected with a power supply; the drains of the PMOS transistors are sequentially connected to each other and to the source of the third transistor M3.
In this embodiment, the NMOS transistors in the second transistor array MS2 may be arranged in parallel. The source electrode of each NMOS tube is connected and grounded; the drain electrodes of the respective NMOS transistors are sequentially connected to each other and to the source electrode of the fourth transistor M4.
In one embodiment, the second adjustable buffer DP1 comprises: a third transistor array, a fourth transistor array, a seventh transistor, and an eighth transistor.
The structure of this second adjustable buffer DP1 may be similar to the structure of the first adjustable buffer UP1 shown in fig. 4, for example.
Illustratively, the gates of the transistors in the third transistor array and the gates of the transistors in the fourth transistor array are connected to the second terminal of the finite state machine 170 as the first control terminal of the second adjustable buffer DP1.
The gate of the seventh transistor and the gate of the eighth transistor are connected to the first terminal of the driver 140 as the second control terminal of the boost module 190.
The drain of the seventh transistor and the drain of the eighth transistor are connected to the second transistor M2 as the output of the second adjustable buffer DP1.
Optionally, each transistor in the third transistor array and the seventh transistor are PMOS transistors.
Optionally, each transistor in the fourth transistor array and the eighth transistor are NMOS transistors.
In this embodiment, the plurality of PMOS transistors in the third transistor array may be arranged in parallel. The source electrode of each PMOS tube is connected with a power supply; and the drain electrodes of the PMOS tubes are sequentially connected with each other and are connected with the source electrode of the seventh transistor.
In this embodiment, the plurality of NMOS transistors in the fourth transistor array may be arranged in parallel. The source electrode of each NMOS tube is connected and grounded; and the drain electrodes of the NMOS tubes are sequentially connected with each other and are connected with the source electrode of the eighth transistor.
In the example shown in fig. 2, the finite state machine 170 described above may include a plurality of states, including: when the voltage of the waveform filtered by the filter 150 is less than VDD/4, i.e. the output of the comparator 160 is high, the finite state machine 170 acts accordingly to enhance the first adjustable buffer UP1; when the voltage of the filtered waveform of the filter 150 is greater than VDD/4, i.e. the output of the comparator 160 is low, the finite state machine 170 is activated accordingly to enhance the second adjustable buffer DP1.
Optionally, the duty ratio calibration circuit 100 further includes: and a second resistor R2.
Illustratively, a first end of the second resistor R2 is connected between the filter 150 and the driver 140, and a second end of the second resistor R2 is connected to ground.
Optionally, the duty ratio calibration circuit 100 may further include: a first diode D1 and a second diode D2.
Illustratively, the anode of the first diode D1 is connected to a power supply; the cathode of the first diode D1 is connected to the anode of the second diode D2, and is connected between the second resistor R2 and the filter 150; the cathode of the second diode D2 is grounded.
In this embodiment, the first diode D1 and the second diode D2 are electrostatic discharge (ESD) protection tubes of the high-speed interface circuit sending module 300 where the duty ratio calibration circuit is located.
Illustratively, a first diode D1 and a second diode D2 are connected in parallel in a duty ratio calibration circuit, when the duty ratio calibration circuit works normally, the first diode D1 and the second diode D2 are in a cut-off state (high-resistance state) and do not affect the normal work of a line, when the duty ratio calibration circuit generates abnormal overvoltage and reaches the breakdown voltage of the duty ratio calibration circuit, the first diode D1 and the second diode D2 are changed from the high-resistance state to the low-resistance state, a low-resistance conduction path is provided for instant current, and meanwhile, the abnormal high voltage is clamped within a safety level, so that the protected duty ratio calibration circuit is protected; when the abnormal overvoltage disappears, the abnormal overvoltage is recovered to a high-resistance state, and the duty ratio calibration circuit works normally.
In this embodiment, the duty calibration circuit further includes a third resistor R3.
In one embodiment, one end of the third resistor R3 is connected between the ac coupling capacitor C2 and the driver 140, and the other end of the third resistor R3 is grounded.
In another embodiment, one end of the third resistor R3 is connected between the cathode of the first diode D1 and the anode of the second diode D2, and the other end of the third resistor R3 is grounded.
Illustratively, the third resistor R3 may be a termination resistor.
In one example, the third resistor R3 may have a resistance of 50 ohms.
The operation principle of adjusting the duty ratio of the output signal is described below by way of an example.
First, when the calibration duty ratio is required, the calibration enable signal (calibration enable) may be turned on by controlling the switch K1 to enable the data selector to select a high level signal input from the oscillator and frequency divider 130. In this embodiment, the calibration enable signal is enabled by closing control switch K1 in filter 150.
Then, the comparator 160 compares the voltage level of the signal after passing through the filter 150 with VDD/4.
When the length of the rising segment of the signal is greater than the length of the falling segment, that is, the rising edge of the signal is slow, and the voltage of the waveform filtered by the filter 150 is less than VDD/4, the comparator 160 controls the finite state machine 170, and strengthens the first adjustable buffer UP1, so that the first transistor M1 is strengthened, and after passing through the ac coupling capacitor C2, the rising switching of the signal is accelerated, thereby reducing the length of the rising segment.
When the length of the rising segment of the signal is smaller than that of the falling segment, that is, the falling edge of the signal is slow, and the voltage of the waveform filtered by the filter 150 is greater than VDD/4, the comparator 160 controls the finite state machine 170, and strengthens the second adjustable buffer DP1, so that the second transistor M2 is strengthened, and after passing through the ac coupling capacitor C2, the falling switching of the signal is accelerated, thereby reducing the length of the falling segment.
In the above example, the rising and falling segments are corrected to within an acceptable difference range by the finite state machine 170, and the duty cycle of the output signal is corrected to around 50%.
The duty ratio calibration circuit provided by the embodiment of the application can correct the output signal duty ratio mismatch caused by the rising or falling mismatch of the signal of the transistor of the driver 140, and improve the work rate of the input/output interface. Further, the finite-state machine 170, the comparator 160 and other correction circuits for correcting the duty ratio, which are used in the duty ratio calibration circuit, may be shared with the resistance correction of the terminal resistor in a time-sharing manner, so that the increase of circuit modules may also be reduced.
Example two
An embodiment of the present application provides a high-speed interface circuit, as shown in fig. 5, the high-speed interface circuit includes: a clock module, a transmit module 300 (Transmitter) and a receive module 400 (Receiver).
Optionally, the clock module comprises: a phase locked loop 210 (PLL for short).
The pll 210 is a negative feedback control system that detunes an oscillator to generate a target frequency by using a voltage generated in phase synchronization. The phase-locked loop 210 is a typical feedback control circuit, which uses an externally input reference signal to control the frequency and phase of an internal oscillation signal of a loop, so as to realize automatic tracking of the frequency of an output signal to the frequency of an input signal, and is generally used for a closed-loop tracking circuit.
Illustratively, the transmitting module 300 includes: serializer 310 (serializer), duty cycle calibration circuit 100.
The duty cycle calibration circuit in this embodiment is similar to the duty cycle calibration circuit in the first embodiment, and other details about the duty cycle calibration circuit in this embodiment can also refer to the description in the first embodiment, and are not described again here.
Illustratively, the receiving module 400 includes: an analog front end 410 (receiverAFE) of the receiver, a sampler 420 (sampler), a clock phase adjuster 430 (clock phase adjuster), and a deserializer 440 (De-serializer). Here, the AFE represents an analog front end (analog front).
Illustratively, high speed interface circuits are commonly used for interconnecting different chips. The first high-speed interface circuit SerDes1 inputs slow parallel Nbit (N may be 4/8/10/16) input data (input data) to be converted into high-speed serial data through the serializer 310, and the high-speed serial data is sent out of the chip through the pre-driver 180 and the driver 140 via the input/output pin. The signal is transmitted to the analog front end 410 of the receiver of the second high-speed interface circuit SerDes2 through other off-chip media, such as a cable/PCB/package substrate, the analog front end 410 of the receiver shapes the received signal (improves the signal quality), and then the signal is sampled by the sampler 420, and the sampling clock of the sampler 420 is derived from the clock phase adjuster 430. The high-speed signal correctly sampled by the sampler 420 passes through the deserializer 440 and is then converted into a parallel slow-speed clock, and then Nbit output data (output data) is output and sent to the digital module of the second high-speed interface circuit SerDes2 for subsequent processing.
Illustratively, the length of the data input by the first high-speed interface circuit SerDes1 depends on the standard of the first high-speed interface circuit SerDes1, and is not described in detail herein.
Illustratively, the clock phase adjuster 430 may be a Clock Data Recovery (CDR) or other circuit.
In this embodiment, in order to ensure that the link error rate (linkbierrorratito) of the high-speed interface circuit is low, the eye opening (eyeopening) of the signal output by the input/output interface of the high-speed interface circuit needs to be larger. The size of the eye opening depends on the output clock of the phase-locked loop 210 of the sending module 300, the duty ratio of the output signal of the input/output interface caused by mismatching (mismatch) of the transistors of the pre-driver 180 and the driver 140, the medium of chip interconnection, power supply and ground noise, and other factors.
In the high-speed interface circuit of the present embodiment, if the clock duty of the selection signal (data _ sel) is not good, the output waveform duty of the serializer 310 is deteriorated accordingly. Therefore, the output clock of the phase locked loop 210 of the high-speed interface circuit in the embodiment of the present application may have a duty ratio calibrator 220 (duty cycle calibrator) to calibrate the signal output by the phase locked loop 210.
In the prior art, the input clock of the serializer 310 is 50% duty cycle, but the mismatch of transistors in the pre-driver 180 and the driver 140 included in the transmitting module 300 may also cause the mismatch of the rise/fall (Tr/Tf) of the output signal of the input/output interface. In the embodiment of the application, the rising/falling adjustment of the signal can be realized through components in the duty ratio calibration circuit, so that the calibration of the duty ratio of the output signal is realized.
EXAMPLE III
Embodiments of the present application also provide a processor that includes a processing core and a high speed interface circuit.
Wherein the processing core may be configured to process the fetched instructions.
The high-speed interface circuit in this embodiment may be similar to the high-speed interface circuit provided in the second embodiment, and for other details of the high-speed interface circuit in this embodiment, reference may be made to the description in the second embodiment, and details are not repeated here.
Example four
The embodiment of the application also provides the electronic equipment. The electronic device in this embodiment may include a memory and a processor.
The various elements of the memory and processor described above are electrically coupled to each other, directly or indirectly, to enable data transfer or interaction. For example, the components may be electrically connected to each other via one or more communication buses or signal lines. The processor described above is used to execute executable modules stored in the memory.
The Memory may be, but is not limited to, a Random Access Memory (RAM), a Read Only Memory (ROM), a Programmable Read-Only Memory (PROM), an Erasable Read-Only Memory (EPROM), an electrically Erasable Read-Only Memory (EEPROM), and the like. The memory is used for storing a computer program, and the processor executes the computer program after receiving the execution instruction.
The processor in this embodiment is similar to the processor provided in the third embodiment, and other details regarding the processor in this embodiment may refer to the description in the third embodiment, and are not described herein again.
The electronic device in this embodiment may further include other components according to different requirements of the electronic device.
For example, the electronic device may be a notebook. The electronic device in this embodiment may further include an input-output unit for providing input data to the user. The input/output unit may be, but is not limited to, a mouse, a keyboard, and the like.
As another example, the electronic device may be an advertisement player. The electronic device in this embodiment may further include the display unit described above to provide an interactive interface (e.g., a user operation interface) between the electronic device and a user or to display image data for reference by the user. In this embodiment, the display unit may be a liquid crystal display or a touch display. In the case of a touch display, the display can be a capacitive touch screen or a resistive touch screen, which supports single-point and multi-point touch operations. Supporting single-point and multi-point touch operations means that the touch display can sense touch operations simultaneously generated from one or more positions on the touch display, and the sensed touch operations are sent to the processor for calculation and processing.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present application shall be included in the protection scope of the present application. It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (13)
1. A duty cycle calibration circuit, comprising: the circuit comprises an oscillator, a frequency divider, a data selector, a driver, a filter, a comparator, a finite state machine, an enhancement module, an alternating current coupling capacitor and a pre-driver;
the oscillator is connected with the first end of the frequency divider;
the second end of the frequency divider is connected with the first input end of the data selector;
the pre-driver is connected with the second input end of the data selector;
the output end of the data selector is connected with the first end of the driver;
the second end of the driver is connected with the first end of the filter;
the second end of the filter is connected with the first input end of the comparator;
the output end of the comparator is connected with the first end of the finite-state machine;
the second end of the finite-state machine is connected with the first end of the enhancement module, the second end of the enhancement module is connected with the first end of the driver, the third end of the enhancement module is connected with the first end of the alternating-current coupling capacitor, the second end of the alternating-current coupling capacitor is connected with the second end of the driver, and the enhancement module and the alternating-current coupling capacitor are used for controlling the switching of signal rising or falling.
2. The duty cycle calibration circuit of claim 1, wherein the boost module comprises: an ascending enhancement module and a descending enhancement module;
the ascent enhancement module includes: a first adjustable buffer and a first transistor;
the droop enhancing module includes: a second adjustable buffer and a second transistor;
a first control end of the first adjustable buffer and a first control end of the second adjustable buffer are used as first ends of the enhancement module and are connected with a second end of the finite-state machine;
the second control end of the first adjustable buffer and the second control end of the second adjustable buffer are used as the second end of the enhancement module and are connected with the first end of the driver;
the output end of the first adjustable buffer is connected with the first transistor;
the output end of the second adjustable buffer is connected with the second transistor;
and the output ends of the first transistor and the second transistor are used as the third end of the enhancement module and are connected with the first end of the alternating current coupling capacitor.
3. The duty cycle calibration circuit of claim 2, wherein the first adjustable buffer comprises: a first transistor array, a second transistor array, a third transistor, and a fourth transistor;
the grid electrode of each transistor in the first transistor array and the grid electrode of each transistor in the second transistor array are used as a first control end of the first adjustable buffer and connected with a second end of the finite-state machine;
the grid electrode of the third transistor and the grid electrode of the fourth transistor are used as second control ends of the enhancement modules and connected with the first end of the driver;
a drain of the third transistor and a drain of a fourth transistor are connected to the first transistor as an output of the first adjustable buffer.
4. The duty cycle calibration circuit of claim 3, wherein each transistor in the first transistor array and the third transistor are PMOS transistors;
and each transistor and the fourth transistor in the second transistor array are NMOS transistors.
5. The duty cycle calibration circuit of claim 1, wherein the filter comprises: the control switch, the first resistor and the first capacitor are connected;
a first end of the control switch is used as a first end of the filter and is connected with a second end of the driver, a second end of the control switch is connected with a first end of the first resistor, a second end of the first resistor is connected with a first end of the first capacitor, and a second end of the first capacitor is grounded;
the second end of the first resistor is connected as the second end of the filter with the first input end of the comparator.
6. The duty cycle calibration circuit of claim 1, wherein the driver comprises: a fifth transistor and a sixth transistor;
the grid electrode of the fifth transistor and the grid electrode of the sixth transistor are used as first ends of the drivers and are connected with the output end of the data selector;
the drain electrode of the fifth transistor and the drain electrode of the sixth transistor are used as second ends of the drivers and are connected with the first end of the filter;
the source electrode of the fifth transistor is connected with a power supply;
the source of the sixth transistor is grounded.
7. The duty cycle calibration circuit of claim 1, wherein the frequency divider is a divide-by-two frequency divider.
8. The duty cycle calibration circuit of claim 1, further comprising: a second resistor;
a first end of the second resistor is connected between the filter and the driver;
and the second end of the second resistor is grounded.
9. The duty cycle calibration circuit of claim 8, further comprising: a first diode and a second diode;
the anode of the first diode is connected with a power supply;
the cathode of the first diode is connected with the anode of the second diode and is connected between the second resistor and the filter;
and the cathode of the second diode is grounded.
10. The duty cycle calibration circuit of claim 9, further comprising: a third resistor;
one end of the third resistor is connected between the alternating current coupling capacitor and the driver, and the other end of the third resistor is grounded;
or one end of the third resistor is connected between the cathode of the first diode and the anode of the second diode, and the other end of the third resistor is grounded.
11. A high-speed interface circuit, comprising: the device comprises a clock module, a sending module and a receiving module;
the sending module comprises: a serializer and the duty cycle calibration circuit of any one of claims 1-10, the serializer pre-connected to the pre-driver of the duty cycle calibration circuit.
12. A processor, comprising: a high speed interface circuit as recited in claim 11.
13. An electronic device, comprising:
the processor of claim 12;
a memory storing machine readable instructions executable by the processor.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011557434.3A CN112787633B (en) | 2020-12-24 | 2020-12-24 | Duty ratio calibration circuit, high-speed interface circuit, processor and electronic equipment |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011557434.3A CN112787633B (en) | 2020-12-24 | 2020-12-24 | Duty ratio calibration circuit, high-speed interface circuit, processor and electronic equipment |
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| CN112787633B true CN112787633B (en) | 2023-02-03 |
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| CN1209875C (en) * | 2002-10-30 | 2005-07-06 | 威盛电子股份有限公司 | Buffer capable of regulating work period and its operation method |
| US9143121B2 (en) * | 2012-08-29 | 2015-09-22 | Qualcomm Incorporated | System and method of adjusting a clock signal |
| CN104539286B (en) * | 2014-12-10 | 2017-12-01 | 深圳市国微电子有限公司 | Base frequency clock generation circuit |
| CN105958971A (en) * | 2016-06-02 | 2016-09-21 | 泰凌微电子（上海）有限公司 | Clock duty ratio calibration circuit |
| CN108134602B (en) * | 2017-12-21 | 2021-08-24 | 长鑫存储技术有限公司 | Duty ratio calibration circuit and semiconductor memory |
| US11115177B2 (en) * | 2018-01-11 | 2021-09-07 | Intel Corporation | Methods and apparatus for performing clock and data duty cycle correction in a high-speed link |
| US10547298B1 (en) * | 2018-09-07 | 2020-01-28 | Cadence Design Systems, Inc. | Duty cycle correction system and method |
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