CN112768510A - Method for forming low-resistance ohmic contact at normal temperature and semiconductor device - Google Patents
Method for forming low-resistance ohmic contact at normal temperature and semiconductor device Download PDFInfo
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- CN112768510A CN112768510A CN202110088892.5A CN202110088892A CN112768510A CN 112768510 A CN112768510 A CN 112768510A CN 202110088892 A CN202110088892 A CN 202110088892A CN 112768510 A CN112768510 A CN 112768510A
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- 238000000034 method Methods 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 claims abstract description 73
- 239000002184 metal Substances 0.000 claims abstract description 73
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 64
- 150000002500 ions Chemical class 0.000 claims abstract description 57
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 47
- 238000000137 annealing Methods 0.000 claims abstract description 16
- 230000003213 activating effect Effects 0.000 claims abstract description 8
- 238000000151 deposition Methods 0.000 claims abstract description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 41
- 239000010936 titanium Substances 0.000 claims description 30
- 238000005468 ion implantation Methods 0.000 claims description 29
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 27
- 229910052719 titanium Inorganic materials 0.000 claims description 27
- 229910052759 nickel Inorganic materials 0.000 claims description 19
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims description 17
- 238000000407 epitaxy Methods 0.000 claims description 13
- 229910052757 nitrogen Inorganic materials 0.000 claims description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 9
- -1 nitrogen ions Chemical class 0.000 claims description 9
- 238000009826 distribution Methods 0.000 claims description 5
- 238000005224 laser annealing Methods 0.000 abstract description 5
- 210000004027 cell Anatomy 0.000 description 5
- 210000002858 crystal cell Anatomy 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
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- Microelectronics & Electronic Packaging (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
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Abstract
The invention relates to a method for forming low-resistance ohmic contact at normal temperature and a semiconductor device, comprising the following steps of: injecting N-type ions into the surface of the silicon carbide to form degenerate silicon carbide; activating the injected N-type ions by using high-temperature annealing so as to repair the damage to the unit cell when the N-type ions are injected; and depositing double-layer metal on the surface of the implanted N-type ions to form ohmic contact. According to the scheme, degenerate silicon carbide is formed on the surface of the silicon carbide, so that the aim of directly forming N-type ohmic contact on metal (Ti/Ni) without high temperature or laser annealing at normal temperature is fulfilled. Because the common silicon carbide ohmic contact high-temperature annealing is avoided, the problem of forming cavities on the surface of the ohmic contact is solved, and the electrical characteristics and the reliability of key parts of devices such as Schottky contact, MOS interfaces and the like of the semiconductor device are obviously improved.
Description
Technical Field
The invention relates to the technical field of semiconductor processes, in particular to a method for forming low-resistance ohmic contact at normal temperature and a semiconductor device.
Background
When a semiconductor is in contact with a metal, a barrier layer is often formed, but when the doping concentration of the semiconductor is high, electrons can tunnel through the barrier, thereby forming a low resistance ohmic contact. Ohmic contact is very important for semiconductor devices, and good ohmic contact is formed to facilitate input and output of current.
Referring to fig. 1 and 2, a silicon carbide diode or a field effect transistor generally requires annealing at about 1000 ℃ (high temperature) or laser annealing on a deposited metal electrode on a surface where metal reacts with silicon carbide 1 to form a low-resistance ohmic contact. The annealing process is a chemical reaction between metal and silicon carbide, which is easy to form a cavity at the ohmic contact interface and reduces the contact reliability. High temperature returns or laser anneals are typically performed at the end of the wafer fabrication process, which can degrade the electrical characteristics of the critical portions of previously formed devices such as schottky contacts, MOS interfaces, etc., and thus reduce reliability.
Disclosure of Invention
The invention aims to solve the problem that voids are formed at an ohmic contact interface when deposited metal electrodes are annealed at about 1000 ℃ (high temperature) or laser annealed in the prior art, and provides a method for forming low-resistance ohmic contact at normal temperature and a semiconductor device.
In order to achieve the above object, the embodiments of the present invention provide the following technical solutions:
a method of forming a low resistance ohmic contact at ambient temperature comprising the steps of:
step S1: injecting N-type ions into the surface of the silicon carbide to form degenerate silicon carbide;
step S2: activating the injected N-type ions by using high-temperature annealing so as to repair the damage to the unit cell when the N-type ions are injected;
step S3: and depositing double-layer metal on the surface of the implanted N-type ions to form ohmic contact.
In the scheme, degenerate silicon carbide is formed on the surface of the silicon carbide so as to realize the purpose of directly forming N-type ohmic contact on metal (Ti/Ni) without high temperature or laser annealing at normal temperature.
Further, in the step S1, the implanted N-type ions are nitrogen ions.
Further, the concentration of the implanted nitrogen ions is 5 × 1019cm-3Or more.
Further, the silicon carbide in step S1 includes a single crystal silicon carbide epitaxy, N-type ions are implanted in a surface of the single crystal silicon carbide epitaxy, and an ion implantation layer tail silicon carbide having a lower concentration than the N-type ions is formed between the single crystal silicon carbide epitaxy and the N-type ions due to gaussian distribution.
In the scheme, an ion implantation layer is formed by implanting N-type ions on the epitaxial surface of the single crystal silicon carbide, and the implanted N-type ions form a tail layer under the ion implantation layer due to the tail effect of Gaussian distribution, namely, low-concentration ion implantation layer tail silicon carbide is formed between the single crystal silicon carbide epitaxy and the high-concentration ion implantation layer.
In the step S2, the high temperature range used for activating the implanted N-type ions is 1400-1600 ℃.
In the above scheme, the unit cell refers to the most basic repeating unit in the semiconductor crystal structure, the high energy of the N-type ion implantation process can disturb the originally ordered unit cell structure, the high temperature annealing is used for repairing the unit cell structure by atomic thermal motion, and the high temperature annealing is used in the step without involving ohmic contact or other purposes.
Further, in step S3, the double-layer metal deposited on the surface of the N-type ion is metal titanium and metal nickel, and the metal titanium is first deposited on the surface of the N-type ion, and then the metal nickel is deposited on the surface of the metal titanium.
Further, the thickness of the metal titanium deposited on the surface of the N-type ions is 30 nm; the thickness of the nickel metal deposited on the titanium surface was 100 nm.
A semiconductor device for forming a low-resistance ohmic contact at normal temperature, comprising: silicon carbide, an ion implantation region, a double-layer metal region, wherein the ion implantation region covers the surface of the silicon carbide, the double-layer metal region covers the surface of the ion implantation region, and the double-layer metal region covers the surface of the ion implantation region,
n-type ions are implanted into the ion implantation area to form degenerate silicon carbide, and the implanted N-type ions are activated by using high-temperature annealing;
the double-layer metal area comprises metal titanium and metal nickel, wherein the metal titanium is deposited on the surface of the N-type ions, and the metal nickel is deposited on the surface of the metal titanium.
Preferably, the N-type ions implanted into the ion implantation region are nitrogen ions and have a concentration of 5 × 1019cm-3Or more.
Preferably, the thickness of the metallic titanium is 30 nm; the thickness of the metal nickel is 100 nm.
Compared with the prior art, the invention has the beneficial effects that:
according to the scheme, degenerate silicon carbide is formed on the surface of the silicon carbide, so that the aim of directly forming N-type ohmic contact on metal (Ti/Ni) without high temperature or laser annealing at normal temperature is fulfilled. Because the common silicon carbide ohmic contact high-temperature annealing is avoided, the problem of forming cavities on the surface of the ohmic contact is solved, and the electrical characteristics and the reliability of key parts of devices such as Schottky contact, MOS interfaces and the like of the semiconductor device are obviously improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
FIG. 1 is a schematic diagram of a prior art semiconductor structure for forming ohmic contacts;
FIG. 2 is a simplified diagram of a prior art semiconductor structure for forming ohmic contacts;
FIG. 3 is a schematic view of a semiconductor structure with ohmic contacts formed according to an embodiment of the invention;
FIG. 4 is a simplified diagram of a semiconductor structure for forming ohmic contacts according to an embodiment of the present invention.
Description of the main elements
The silicon carbide at the tail part of the ion implantation layer 1, the single crystal silicon carbide epitaxy 2, the metal and silicon carbide reaction layer 3, the ion implantation area (i.e. implanted N-type ions) 4, the metal titanium 5 and the metal nickel 6.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The components of embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present invention without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
The invention is realized by the following technical scheme, as shown in figure 1, a method for forming low-resistance ohmic contact at normal temperature comprises the following steps:
step S1: and injecting N-type ions into the surface of the silicon carbide to form degenerate silicon carbide.
Silicon carbide in a semiconductor device such as a silicon carbide diode or a field effect transistor generally includes a single crystal silicon carbide epitaxial layer 2, N-type ions are implanted into the surface of the single crystal silicon carbide epitaxial layer 2, and an ion implantation layer tail portion silicon carbide 1 having a lower concentration than the N-type ions is formed between the single crystal silicon carbide epitaxial layer 2 and the N-type ions due to gaussian distribution. In order to reduce the roughness of silicon carbide, the epitaxial surface of silicon carbide is polished so that the roughness is controlled to 0.5nm or less.
The scheme is shown in the table of the single crystal silicon carbide epitaxy 2Surface implanting N-type ions 4, preferably nitrogen ions, at a concentration of 5 x 10 to form degenerate silicon carbide on the surface of the single crystal silicon carbide epitaxy 219cm-3Or more.
In addition, after many experiments, when the concentration of nitrogen ions is 5X 1019cm-3Or above, the degenerate silicon carbide formed is relatively good.
Step S2: and activating the implanted N-type ions by using high-temperature annealing, thereby repairing the damage to the unit cell caused by the implantation of the N-type ions.
The crystal cell refers to the most basic repeating unit in a semiconductor crystal structure, the original ordered crystal cell structure is disturbed by the high energy of an N-type ion implantation process, the high-temperature annealing aims to repair the self crystal cell structure through atomic thermal motion, and the high-temperature annealing is used in the step and does not relate to ohmic contact or other purposes.
Preferably, the high temperature range used for activating the implanted N-type ions is 1400-1600 ℃.
Step S3: and depositing double-layer metal on the surface of the implanted N-type ions to form ohmic contact.
Then double-layer metal is deposited on the surface area of the injected N-type ions, the deposited double-layer metal is metal titanium 5 and metal nickel 6, metal titanium 5 with the thickness of 30nm is deposited on the surface area of the N-type ions, and metal nickel 6 with the thickness of 100nm is deposited on the surface of the metal titanium 5, so that the N-type low-resistance ohmic contact is directly formed.
In this embodiment, the double-layer metal is not limited to titanium and nickel, and the thickness is not limited, and when the semiconductor device is shipped, an appropriate thickness can be designed according to the actual metal to form an ohmic contact.
According to the scheme, degenerate silicon carbide is formed on the surface of the silicon carbide, so that the aim of directly forming N-type ohmic contact on metal (Ti/Ni) without high temperature or laser annealing at normal temperature is fulfilled. Because the common silicon carbide ohmic contact high-temperature annealing is avoided, the problem of forming cavities on the surface of the ohmic contact is solved, and the electrical characteristics and the reliability of key parts of devices such as Schottky contact, MOS interfaces and the like of the semiconductor device are obviously improved.
The present invention also provides a semiconductor device for forming a low resistance ohmic contact at normal temperature, please refer to fig. 3 and 4, which includes: silicon carbide, an ion implantation region, a double-layer metal region, wherein the ion implantation region covers the surface of the silicon carbide, the double-layer metal region covers the surface of the ion implantation region, and the double-layer metal region covers the surface of the ion implantation region,
the silicon carbide comprises a single crystal silicon carbide epitaxy 2, N-type ions 4 are implanted into the surface of the single crystal silicon carbide epitaxy 2, and due to Gaussian distribution, an ion implantation layer tail silicon carbide 1 with concentration lower than that of the N-type ions 4 is formed between the single crystal silicon carbide epitaxy 2 and the N-type ions 4.
The ion implantation region 1 is implanted with N-type ions to form degenerate silicon carbide, the implanted N-type ions are nitrogen ions with a concentration of 5 × 1019cm-3Or above; activating the injected N-type ions by high-temperature annealing; the high temperature range of the use is 1400-1600 ℃.
The double-layer metal area comprises metal titanium 5 and metal nickel 6, wherein the metal titanium is deposited on the surface of the N-type ions, and the metal nickel is deposited on the surface of the metal titanium; the thickness of the metal titanium is 30nm, and the thickness of the metal nickel is 100 nm.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A method for forming a low resistance ohmic contact at ambient temperature, comprising: the method comprises the following steps:
step S1: injecting N-type ions into the surface of the silicon carbide to form degenerate silicon carbide;
step S2: activating the injected N-type ions by using high-temperature annealing so as to repair the damage to the unit cell when the N-type ions are injected;
step S3: and depositing double-layer metal on the surface of the implanted N-type ions to form ohmic contact.
2. The method of claim 1, wherein the method comprises: in step S1, the implanted N-type ions are nitrogen ions.
3. The method of claim 2, wherein the method comprises: the concentration of the implanted nitrogen ions is 5 x 1019cm-3Or more.
4. The method of claim 1, wherein the method comprises: the silicon carbide in step S1 includes a single crystal silicon carbide epitaxy, N-type ions are implanted into a surface of the single crystal silicon carbide epitaxy, and silicon carbide at a tail of an ion implantation layer having a lower concentration than the N-type ions is formed between the single crystal silicon carbide epitaxy and the N-type ions due to gaussian distribution.
5. The method of claim 1, wherein the method comprises: in the step S2, the high temperature range used for activating the implanted N-type ions is 1400-1600 ℃.
6. The method of claim 1, wherein the method comprises: in step S3, the double-layer metal deposited on the surface of the N-type ion is metal titanium and metal nickel, and the metal titanium is first deposited on the surface of the N-type ion, and then the metal nickel is deposited on the surface of the metal titanium.
7. The method of claim 6, wherein the ohmic contact is formed by: the thickness of the metal titanium deposited on the surface of the N-type ions is 30 nm; the thickness of the nickel metal deposited on the titanium surface was 100 nm.
8. A semiconductor device for forming a low-resistance ohmic contact at normal temperature, characterized in that: the method comprises the following steps: silicon carbide, an ion implantation region, a double-layer metal region, wherein the ion implantation region covers the surface of the silicon carbide, the double-layer metal region covers the surface of the ion implantation region, and the double-layer metal region covers the surface of the ion implantation region,
n-type ions are implanted into the ion implantation area to form degenerate silicon carbide, and the implanted N-type ions are activated by using high-temperature annealing;
the double-layer metal area comprises metal titanium and metal nickel, wherein the metal titanium is deposited on the surface of the N-type ions, and the metal nickel is deposited on the surface of the metal titanium.
9. A semiconductor device for forming a low resistance ohmic contact at normal temperature according to claim 8, wherein: the N-type ions implanted into the ion implantation region are nitrogen ions with a concentration of 5 × 1019cm-3Or more.
10. A semiconductor device for forming a low resistance ohmic contact at normal temperature according to claim 8, wherein: the thickness of the metal titanium is 30 nm; the thickness of the metal nickel is 100 nm.
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| CN202110088892.5A CN112768510A (en) | 2021-01-22 | 2021-01-22 | Method for forming low-resistance ohmic contact at normal temperature and semiconductor device |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1579008A (en) * | 2001-10-31 | 2005-02-09 | 克里公司 | Low temperature formation of backside ohmic contacts for vertical devices |
| CN102507704A (en) * | 2011-10-18 | 2012-06-20 | 重庆邮电大学 | Schottky barrier diode oxygen sensor based on silicon carbide and manufacturing method thereof |
| CN104704611A (en) * | 2013-10-08 | 2015-06-10 | 新电元工业株式会社 | Silicon carbide semiconductor device manufacturing method |
| US10192970B1 (en) * | 2013-09-27 | 2019-01-29 | The United States Of America As Represented By The Administrator Of National Aeronautics And Space Administration | Simultaneous ohmic contact to silicon carbide |
| CN109524298A (en) * | 2018-11-21 | 2019-03-26 | 中国电子科技集团公司第十三研究所 | The production method and silicon carbide device of the non-alloyed Ohmic contact of silicon carbide device |
| US20190371893A1 (en) * | 2018-05-29 | 2019-12-05 | Fuji Electric Co., Ltd. | Silicon carbide semiconductor device and method for manufacturing the same |
| US20200066528A1 (en) * | 2018-08-27 | 2020-02-27 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
-
2021
- 2021-01-22 CN CN202110088892.5A patent/CN112768510A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1579008A (en) * | 2001-10-31 | 2005-02-09 | 克里公司 | Low temperature formation of backside ohmic contacts for vertical devices |
| CN102507704A (en) * | 2011-10-18 | 2012-06-20 | 重庆邮电大学 | Schottky barrier diode oxygen sensor based on silicon carbide and manufacturing method thereof |
| US10192970B1 (en) * | 2013-09-27 | 2019-01-29 | The United States Of America As Represented By The Administrator Of National Aeronautics And Space Administration | Simultaneous ohmic contact to silicon carbide |
| CN104704611A (en) * | 2013-10-08 | 2015-06-10 | 新电元工业株式会社 | Silicon carbide semiconductor device manufacturing method |
| US20190371893A1 (en) * | 2018-05-29 | 2019-12-05 | Fuji Electric Co., Ltd. | Silicon carbide semiconductor device and method for manufacturing the same |
| US20200066528A1 (en) * | 2018-08-27 | 2020-02-27 | Fuji Electric Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
| CN109524298A (en) * | 2018-11-21 | 2019-03-26 | 中国电子科技集团公司第十三研究所 | The production method and silicon carbide device of the non-alloyed Ohmic contact of silicon carbide device |
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