CN112768366B - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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- CN112768366B CN112768366B CN202110087124.8A CN202110087124A CN112768366B CN 112768366 B CN112768366 B CN 112768366B CN 202110087124 A CN202110087124 A CN 202110087124A CN 112768366 B CN112768366 B CN 112768366B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 46
- 238000002360 preparation method Methods 0.000 title abstract description 6
- 238000012360 testing method Methods 0.000 claims abstract description 268
- 239000000758 substrate Substances 0.000 claims abstract description 91
- 238000002955 isolation Methods 0.000 claims abstract description 90
- 230000000149 penetrating effect Effects 0.000 claims description 22
- 239000000463 material Substances 0.000 claims description 16
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 14
- 239000004020 conductor Substances 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 239000011810 insulating material Substances 0.000 claims description 9
- 230000000903 blocking effect Effects 0.000 claims description 6
- 238000005530 etching Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 5
- 239000002184 metal Substances 0.000 abstract description 25
- 230000004888 barrier function Effects 0.000 description 6
- 230000008021 deposition Effects 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 230000000007 visual effect Effects 0.000 description 4
- 238000001514 detection method Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 238000011165 process development Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000003313 weakening effect Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Integrated Circuits (AREA)
- Element Separation (AREA)
Abstract
The invention provides a semiconductor structure and a preparation method thereof, comprising the following steps: the semiconductor structure provided by the invention has the advantages that the test parts are arranged on the insulating layer above the longitudinal projection of each circuit block, and the two of the test parts are applied with the test voltage, so that the substrate voltages in the corresponding two circuit blocks have a difference value, and the existence of metal residues on the isolation structure can be judged by detecting the magnitude of leakage current between the two circuit blocks.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof.
Background
During integrated circuit fabrication, reliability evaluation of components in integrated circuits is an important part of process development, and isolation structures are important components in each integrated circuit, such as TSI (Through Silicon Isolation ) structures used to electrically isolate well regions of integrated circuits to prevent well leakage.
However, under the existing process flow, there is no effective detection method for detecting whether there is a metal residue on the isolation structure in the semiconductor structure, and thus, it is unavoidable that the problem that the device performance of the semiconductor structure is invalid due to the presence of the metal residue on the isolation structure occurs.
Disclosure of Invention
The invention provides a semiconductor structure and a preparation method thereof, which effectively solve the problem that no effective detection method is available in the prior art for detecting whether metal residues exist on an isolation structure in the semiconductor structure.
In order to solve the above-mentioned problems, the present invention provides a semiconductor structure including:
a substrate including a plurality of circuit blocks and having opposite first and second surfaces;
at least one isolation structure penetrating the substrate to electrically isolate the plurality of circuit blocks;
an insulating layer disposed on the first surface of the substrate;
the test parts are arranged on the insulating layer and are respectively positioned above the longitudinal projection of a corresponding circuit block;
two of the plurality of test components are used for being applied with test voltages so that the substrate voltages in the corresponding two circuit blocks have a difference value.
Further preferably, the isolation structure has a first length in a first lateral direction, and the test component has a second length in the first lateral direction, wherein the first length is not greater than the second length.
Further preferably, the plurality of test components includes a first test component and a second test component disposed on the same insulating layer, wherein:
a first vertical distance is formed between the first test component and the first surface of the corresponding first circuit block, and a first test voltage is applied to the first test component;
a second vertical distance is formed between the second test part and the first surface of the corresponding second circuit block, and a second test voltage is applied to the second test part;
and wherein the first vertical distance is equal to the second vertical distance, and the first test voltage is not equal to the second test voltage.
Further preferably, the plurality of test components includes a first test component and a second test component disposed on the same insulating layer, wherein:
a first vertical distance is formed between the first test component and the first surface of the corresponding first circuit block, and a first test voltage is applied to the first test component;
a second vertical distance is formed between the second test part and the first surface of the corresponding second circuit block, and a second test voltage is applied to the second test part;
and wherein the first vertical distance is unequal to the second vertical distance, and the first test voltage is equal to the second test voltage.
Further preferably, the plurality of test components includes a first test component and a second test component, wherein:
the first test component is arranged on the first insulating layer, a first vertical distance is arranged between the first test component and the first surface of the corresponding first circuit block, a first test voltage is applied to the first test component, and the first insulating layer has a first relative dielectric constant;
the second test part is arranged on the second insulating layer, a second vertical distance is arranged between the second test part and the first surface of the corresponding second circuit block, a second test voltage is applied to the second test part, and the second insulating layer has a second relative dielectric constant;
and wherein the first vertical distance is equal to the second vertical distance, the first test voltage is equal to the second test voltage, and the first relative permittivity is not equal to the second relative permittivity.
Further preferably, a first connection structure and a second connection structure are further formed in the insulating layer, the plurality of test components include a first test component and a second test component, the first connection structure is electrically connected with the first test component and a corresponding first circuit block, the second connection structure is electrically connected with the second test component and a corresponding second circuit block, wherein the first test component is applied with a first test voltage, the second test component is applied with a second test voltage, and the first test voltage is unequal to the second test voltage.
It is further preferred that both of said test components to which said test voltages are applied are located above the longitudinal projection of both sides of the same said isolation structure.
In another aspect, the present invention further provides a method for preparing a semiconductor structure, where the method includes:
providing a substrate, wherein the substrate comprises a plurality of circuit blocks and is provided with a first surface and a second surface which are opposite;
forming at least one isolation structure penetrating the substrate, the isolation structure electrically isolating the plurality of circuit blocks;
forming an insulating layer on the first surface of the substrate;
forming a plurality of test components on the insulating layer, wherein each test component is positioned above a longitudinal projection of a corresponding circuit block;
two of the plurality of test components are used for being applied with test voltages so that the substrate voltages in the corresponding two circuit blocks have a difference value.
Further preferably, the step of forming at least one isolation structure penetrating through the substrate specifically includes:
forming at least one isolation trench penetrating through the substrate and forming a plurality of through silicon trenches penetrating through the substrate;
filling an insulating material in the isolation groove to form the isolation structure, and filling the same insulating material in the silicon penetrating groove to form an insulating inner wall;
sequentially filling a blocking material and a conductive material into the silicon-penetrating groove to form a silicon-penetrating structure;
and etching to remove the blocking material and the conductive material remained on the first surface of the substrate.
The beneficial effects of the invention are as follows: the invention provides a semiconductor structure, comprising: the semiconductor structure provided by the invention has the advantages that the test components are arranged on the insulating layer above the longitudinal projection of each circuit block, and the two of the test components are applied with the test voltage, so that the substrate voltages in the corresponding two circuit blocks have a difference value, and whether the metal residues exist on the isolation structure can be detected by detecting whether the leakage current between the corresponding two circuit blocks is larger than a preset value.
Drawings
In order to more clearly illustrate the technical solutions of the present invention, the drawings that are needed in the description of the embodiments according to the present invention will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic cross-sectional view of a semiconductor structure according to a first embodiment of the present invention.
Fig. 2 is a flow chart of a method for manufacturing a semiconductor structure according to a first embodiment of the present invention.
Fig. 3 is a further flow chart of a method for fabricating a semiconductor structure according to a first embodiment of the present invention.
Fig. 4 is a schematic cross-sectional view of a semiconductor structure according to a second embodiment of the present invention.
Fig. 5 is a schematic cross-sectional view of a semiconductor structure according to a third embodiment of the present invention.
Fig. 6 is a schematic cross-sectional view of a semiconductor structure according to a fourth embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more of the described features. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically connected, electrically connected or can be communicated with each other; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
In the present invention, unless expressly stated or limited otherwise, a first feature "above" or "below" a second feature may include both the first and second features being in direct contact, as well as the first and second features not being in direct contact but being in contact with each other through additional features therebetween. Moreover, a first feature being "above," "over" and "on" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicating that the first feature is higher in level than the second feature. The first feature being "under", "below" and "beneath" the second feature includes the first feature being directly under and obliquely below the second feature, or simply means that the first feature is less level than the second feature.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. In order to simplify the present disclosure, components and arrangements of specific examples are described below. They are, of course, merely examples and are not intended to limit the invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples, which are for the purpose of brevity and clarity, and which do not themselves indicate the relationship between the various embodiments and/or arrangements discussed. In addition, the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the application of other processes and/or the use of other materials.
The invention aims at solving the problem that the performance of a device of a semiconductor structure is invalid due to the existence of metal residues on the isolation structure because no effective detection method is used for detecting whether the metal residues exist on the isolation structure in the semiconductor structure in the existing semiconductor preparation process.
Referring to fig. 1, fig. 1 is a schematic cross-sectional structure of a semiconductor structure 100 according to a first embodiment of the present invention, and the components of the first embodiment of the present invention and the relative positional relationship of the components can be seen in a visual manner.
As shown in fig. 1, the semiconductor structure 100 includes a substrate 110, a plurality of isolation structures 120, an insulating layer 130, and a plurality of test features 140, wherein:
the substrate 110 includes a plurality of circuit blocks 111, and the substrate 110 has opposite first surfaces S 1 And a second surface S 2 ；
The isolation structure 120 penetrates the substrate 110 to electrically isolate the plurality of circuit blocks 111;
insulation ofLayer 130 is disposed on the first surface S of the substrate 110 1 Applying;
the plurality of test components 140 are disposed on the insulating layer 130, and each of the test components is located above a longitudinal projection of a corresponding one of the plurality of circuit blocks 111;
wherein two of the plurality of test members 140 (the first test member 140 shown in FIG. 1) a Second test part 140 b ) For being applied with test voltages to make corresponding two circuit blocks, such as the first circuit block 111 shown in FIG. 1 a Second circuit block 111 b Has a difference in substrate voltage.
It should be noted that, in the present embodiment, the isolation structure 120 may be a TSI (Through Silicon Isolation ) structure for electrically isolating two adjacent circuit blocks 111 a And 111 b When metal residues are present on the isolation structure 120, the isolation structure 120 is not effectively located on both circuit blocks 111 on both sides thereof a And 111 b Electrically isolated, with the result that the two circuit blocks 111 a And 111 b Leakage current occurs between the two circuit blocks 111 a And 111 b The devices in (a) cannot operate normally, and when the two circuit blocks 111 a And 111 b The isolation structure 120 may even break down if the leakage current therebetween is excessive.
It will be readily appreciated that in the present embodiment, by disposing the test members 140 on the insulating layer 130 above the longitudinal projection of each circuit block 111, and for two of them, the first test member 140 a Second test part 140 b A test voltage is applied to two test components 140 to which the test voltage is applied a And 140 b Corresponding two circuit blocks (first circuit block 111 a Second circuit block 111 b ) Has a difference in substrate voltages so that the corresponding two circuit blocks 111 can be detected a And 111 b The magnitude of the leakage current therebetween determines whether the isolation structure 120 has metal residues thereon. In particularWhen the first circuit block 111 a Second circuit block 111 b When there is no leakage current or the leakage current is smaller than a predetermined value, the first circuit block 111 can be determined a Second circuit block 111 b No metal residue is left on the isolation structure 120 between the first circuit block 111 a Second circuit block 111 b When the leakage current between the first circuit block 111 and the second circuit block is greater than the preset value, the first circuit block is determined a Second circuit block 111 b With metal residues on the isolation structures 120 therebetween.
Specifically, in the case of the first test part 140 a Second test part 140 b When the test voltage is applied, the test can be performed by adopting a mode of gradually increasing the voltage from zero to the test voltage, or by directly applying the proper test voltage. Further, an exemplary material of the test part 140 may be a metal of a three-layer structure of ti+tin/Al/ti+tin, and an exemplary material of the isolation structure 120 may be silicon dioxide.
It should be noted that, in the present embodiment, the isolation structure 120 has a first length along a first lateral direction X parallel to the substrate 110, and the test component 140 has a second length along the first lateral direction X, it should be understood that, to ensure accuracy of the test result, the first length of the isolation structure 120 is not greater than the second length of the test component 140. In another possible modification of the present invention, a plurality of test components 140 may be disposed on the insulating layer 130 above the longitudinal projection of each circuit block 111, and the test component 140 closest to the same isolation structure 120 in vertical distance is used for being tested by applying a test voltage, where only the second length of two test components 140 closest to the same isolation structure 120 in vertical distance is required to be ensured to be greater than the first length of the isolation structure 120.
Further, in the present embodiment, the first circuit block 111 is tested a Second circuit block 111 b The first test part 140 is contacted with the metal residue on the isolation structure 120 a Second test part 140 b A test voltage is applied.
It should be noted that because of the first test part 140 a Second test part 140 b Disposed on the same insulating layer 130, so that the first test part 140 a And the first circuit block 111 a And a second test part 140 b And a second circuit block 111 b The relative permittivity of the medium therebetween is equal (i.e., the medium is for the first test part 140 a And the first circuit block 111 a And a second test part 140 b And a second circuit block 111 b The degree of weakening of the electric field is the same between them); at the same time, due to the first test part 140 a And the first circuit block 111 a Is a first surface S of 1 The first vertical distance therebetween is equal to the second test part 140 b And a second circuit block 111 b Is a first surface S of 1 A second vertical distance therebetween, so that, in the case of the first test part 140 a Applying a first test voltage to the second test part 140 b When the second test voltage is applied for testing, the first test voltage should not be equal to the second test voltage, so that the first circuit block 111 will a Second circuit block 111 b The coupled potentials are not equal, thereby making the first circuit block 111 a Second circuit block 111 b Has a difference in substrate voltage so that the first circuit block 111 can be detected a Second circuit block 111 b The magnitude of the leakage current therebetween determines whether there is a metal residue on the isolation structure 120 therebetween.
It should be understood that in the present embodiment, two test parts 140 to which a test voltage is applied a And 140 b Two test parts 140 to which test voltages are applied are located above the longitudinal projections on both sides of the same isolation structure 120, but since there are also cases where a plurality of adjacent isolation structures 120 each have metal residues thereon a And 140 b Or above the longitudinal projection of the sides of the different isolation structures 120, indicating the two test elements 140 when the leakage current is greater than a predetermined value a And 140 b The plurality of isolation structures 120 therebetween are provided withThere is a metal residue.
Further, referring to fig. 1, in the present embodiment, the semiconductor structure 100 further includes a through silicon structure 150 disposed in each circuit block 111 and penetrating through the substrate 110, wherein the isolation structure 120 has a first width L1 along a second lateral direction Y parallel to the substrate 110, the through silicon structure 150 has a second width L2 along the second lateral direction Y, the first width L1 of the isolation structure 120 is smaller than the second width L2 of the through silicon structure 150, and the second lateral direction Y forms an included angle with the first lateral direction X.
Referring to fig. 2, fig. 2 is a flow chart illustrating a method for fabricating a semiconductor structure 100 according to a first embodiment of the present invention.
As shown in fig. 2, and please refer to fig. 1 for reference numerals for various components constituting the semiconductor structure 100, the method specifically includes:
substrate providing step S101: providing a substrate 110, the substrate 110 comprising a plurality of circuit blocks 111 having opposite first surfaces S 1 And a second surface S 2 ；
Isolation structure forming step S102: forming a plurality of isolation structures 120 penetrating the substrate 110, the isolation structures 120 electrically isolating the plurality of circuit blocks 111;
insulating layer formation step S103: on the first surface S of the substrate 110 1 Forming an insulating layer 130 thereon;
test part forming step S104: a plurality of test elements 140 are formed on the insulating layer 130, and each of the plurality of test elements 140 is located above a longitudinal projection of a corresponding circuit block 111, wherein two of the plurality of test elements 140 are used to apply a test voltage such that the substrate voltages in the corresponding two circuit blocks 111 have a difference.
It should be noted that, referring to fig. 3, fig. 3 is a further flowchart illustrating a method for manufacturing the semiconductor structure 100 according to the first embodiment of the present invention, and as shown in fig. 3, the isolation structure forming step S102 may specifically include:
a groove forming step S1021: forming a plurality of isolation trenches (not shown) through the substrate 110, and forming a plurality of through-silicon trenches (not shown) through the substrate 110;
first deposition step S1022: filling the isolation trench with an insulating material to form an isolation structure 120, and filling the silicon-penetrating trench with the same insulating material to form an insulating inner wall (not shown);
second deposition step S1023: sequentially filling barrier materials and conductive materials into the silicon-penetrating grooves to form a silicon-penetrating structure 150;
etching step S1024: etching to remove the first surface S of the substrate 110 1 And a barrier material and a conductive material remaining thereon.
It should be noted that, since the first width of the isolation structure 120 is smaller than the second width of the through silicon structure 150, the isolation structure 120 and the insulating inner wall of the through silicon structure 150 are generally prepared at the same time in the first deposition step S1022, it is easy to understand that if the isolation trench is not sufficiently filled with the insulating material in the first deposition step S1022, the isolation structure 120 and the surface of the substrate 110 will have a recess, and then in the second deposition step S1023, the barrier material and the conductive material will be filled into the recess when the barrier material and the conductive material continue to be sequentially filled into the through silicon trench, and since the etching step S1024 only can etch to remove the barrier material and the conductive material remained on the surface of the substrate 110, but cannot etch to remove the barrier material and the conductive material in the recess, so that finally, the metal residue exists on the isolation structure 120.
Unlike the prior art, the present invention provides a semiconductor structure 100 comprising: a substrate 110 having a plurality of circuit blocks 111, the substrate 110 having opposite first surfaces S 1 And a second surface S 2 A plurality of isolation structures 120 penetrating the substrate 110 to electrically isolate the plurality of circuit blocks 111, disposed on the first surface S of the substrate 110 1 An insulating layer 130 thereon, and a plurality of test elements 140 disposed on the insulating layer 130, the plurality of test elements 140 each being located above a longitudinal projection of a corresponding circuit block 111, wherein a first test element 140 of the plurality of test elements 140 a Second test part 140 b Disposed on the same insulating layer 130, and a first test part 140 a And the first circuit block 111 a Is a first surface S of 1 The first vertical distance therebetween is equal to the second test part 140 b And a second circuit block 111 b Is a first surface S of 1 A second vertical distance therebetween, and wherein the first test part 140 a Second test part 140 b A first circuit block 111 for applying a first test voltage and a second test voltage with different voltage values a Second circuit block 111 b Has a difference in substrate voltage so that the first circuit block 111 can be detected a Second circuit block 111 b Whether the leakage current is greater than a predetermined value or not is detected to determine whether the isolation structure 120 therebetween has a metal residue.
Referring to fig. 4, fig. 4 is a schematic cross-sectional structure of a semiconductor structure 200 according to a second embodiment of the present invention, and the components of the second embodiment of the present invention and the relative positional relationship of the components can be seen in a visual manner.
As shown in fig. 4, this second embodiment is substantially the same in structure as the first embodiment, in which the substrate 210 in the second embodiment has the same function and arrangement position as the substrate 110 in the first embodiment; the isolation structure 220 in the second embodiment has the same function and arrangement position as the isolation structure 120 in the first embodiment; the insulating layer 230 in the second embodiment has the same function and arrangement position as the insulating layer 130 in the first embodiment; the test component 240 in the second embodiment (including the first test component 240 disposed on the same insulating layer 230) a Second test part 240 b ) The same as the test part 140 of the first embodiment (including the first test part 140 disposed on the same insulating layer 130 a Second test part 140 b ) The function and the setting position are the same.
The difference is that in this embodiment, the first test part 240 a And the first circuit block 211 a Is a first surface S of 1 The first vertical distance therebetween is smaller than the second test part 240 b And a second circuit block 211 b Is a first surface S of 1 A second vertical distance therebetween, and a first test part 240 a Second test part 240 b A first test voltage and a second test voltage with the same voltage value are respectively applied to the first circuit block 211 a Coupled to a potential greater than that of the second circuit block 211 b Coupled to an electric potential, thereby causing the first circuit block 211 a Second circuit block 211 b Has a difference in substrate voltage so that the first circuit block 211 can be detected a Second circuit block 211 b The magnitude of the leakage current therebetween determines whether there is a metal residue on the isolation structure 220 therebetween.
Unlike the prior art, the present invention provides a semiconductor structure 200 comprising: a substrate 210 having a plurality of circuit blocks 211, and the substrate 210 has a first surface S opposite to the first surface S 1 And a second surface S 2 A plurality of isolation structures 220 penetrating the substrate 210 to electrically isolate the circuit blocks 211, disposed on the first surface S of the substrate 210 1 An insulating layer 230 thereon, and a plurality of test elements 240 disposed on the insulating layer 230, the plurality of test elements 240 each being located above a longitudinal projection of a corresponding circuit block 211, wherein a first test element 240 of the plurality of test elements 240 a Second test part 240 b Disposed on the same insulating layer 230, and a first test part 240 a And the first circuit block 211 a Is a first surface S of 1 The first vertical distance therebetween is smaller than the second test part 240 b And a second circuit block 211 b Is a first surface S of 1 A second vertical distance therebetween, and wherein the first test part 240 a Second test part 240 b A first circuit block 211 for applying a first test voltage and a second test voltage with the same voltage value a Second circuit block 211 b Has a difference in substrate voltage so that the first circuit block 211 can be detected a Second circuit block 211 b Whether or not to leak current betweenAbove a predetermined value, it is detected whether there is a metal residue on the isolation structure 220 therebetween.
Referring to fig. 5, fig. 5 is a schematic cross-sectional structure of a semiconductor structure 300 according to a third embodiment of the present invention, and the components of the third embodiment of the present invention and the relative positional relationship of the components can be seen in a visual manner.
As shown in fig. 5, the third embodiment is substantially the same as the first embodiment in that the substrate 310 in the third embodiment has the same function and arrangement position as the substrate 110 in the first embodiment; the isolation structure 320 in the third embodiment has the same function and arrangement position as the isolation structure 120 in the first embodiment; the insulating layer 330 in the third embodiment functions as the insulating layer 130 in the first embodiment and is disposed at the same position; the test part 340 in the third embodiment (and wherein the first test part 340 a And the first circuit block 311 a Is a first surface S of 1 The first vertical distance therebetween is equal to the second test part 340 b And the second circuit block 311 b Is a first surface S of 1 A second vertical distance therebetween) is the same as the function and arrangement position of the test member 140 in the first embodiment (and wherein the first test member 140 a And the first circuit block 111 a Is a first surface S of 1 The first vertical distance therebetween is equal to the second test part 140 b And a second circuit block 111 b Is a first surface S of 1 A second vertical distance therebetween).
The difference is that in this embodiment, the first test part 340 a Is arranged on the first insulating layer 330 a On the first insulating layer 330 a Having a first relative permittivity, a second test part 340 b Is arranged on the second insulating layer 330 b On the second insulating layer 330 b Has a second relative permittivity, wherein the first relative permittivity is not equal to the second relative permittivity, and the first test part 340 a Second test part 340 b A first test voltage and a second test voltage with the same voltage value are respectively applied, thus, due to the first test part 340 a Second test part 340 b Are respectively disposed on the first insulating layers 330 having different relative dielectric constants a Second insulating layer 330 b Therefore, when the first test part 340 a Second test part 340 b When the first test voltage and the second test voltage with the same voltage value are applied, the first insulating layer 330 a Second insulating layer 330 b Respectively to the first test parts 340 a And the first circuit block 311 a And a second test part 340 b And the second circuit block 311 b The electric field is weakened differently, so that the first circuit block 311 a Second circuit block 311 b The coupled potentials are not equal, thereby making the first circuit block 311 a Second circuit block 311 b Has a difference in substrate voltage so that the first circuit block 311 can be detected a Second circuit block 311 b The magnitude of the leakage current therebetween determines whether there is a metal residue on the isolation structure 320 therebetween.
Unlike the prior art, the present invention provides a semiconductor structure 300 comprising: a substrate 310 having a plurality of circuit blocks 311, and the substrate 310 has opposite first surfaces S 1 And a second surface S 2 A plurality of isolation structures 320 penetrating the substrate 310 to electrically isolate the circuit blocks 311, and disposed on the first surface S of the substrate 310 1 An upper insulating layer 330 comprising a first insulating layer 330 a And a second insulating layer 330 b And a plurality of test elements 340 disposed on the insulating layer 330, the plurality of test elements 340 being disposed above a longitudinal projection of a corresponding circuit block 311, wherein a first test element 340 of the plurality of test elements 340 a Is arranged on the first insulating layer 330 a On the second test part 340 b Is arranged on the second insulating layer 330 b On the first insulating layer 330 a Having a different insulating layer 330 from the second insulating layer b Relative dielectric constant of (2)Number, first test part 340 a And the first circuit block 311 a Is a first surface S of 1 The first vertical distance therebetween is equal to the second test part 340 b And the second circuit block 311 b Is a first surface S of 1 A second vertical distance therebetween, and wherein the first test part 340 a Second test part 340 b A first circuit block 311 for applying a first test voltage and a second test voltage with equal voltage values a Second circuit block 311 b Has a difference in substrate voltage so that the first circuit block 311 can be detected a Second circuit block 311 b Whether the leakage current is greater than a predetermined value or not is detected to determine whether the isolation structure 320 therebetween has a metal residue.
Referring to fig. 6, fig. 6 is a schematic cross-sectional structure of a semiconductor structure 400 according to a fourth embodiment of the present invention, and the components of the fourth embodiment of the present invention and the relative positional relationship of the components can be seen in a visual manner.
As shown in fig. 6, the fourth embodiment is substantially the same as the first embodiment in that the substrate 410 in the fourth embodiment has the same function and arrangement position as the substrate 110 in the first embodiment; the isolation structure 420 in the fourth embodiment has the same function and arrangement position as the isolation structure 120 in the first embodiment; the insulating layer 430 in the fourth embodiment has the same function and arrangement position as the insulating layer 130 in the first embodiment; the test member 440 in the fourth embodiment is the same as the test member 140 in the first embodiment in function and arrangement position.
The difference is that in the present embodiment, a first connection structure 450 is further formed in the insulating layer 430 a And a second connection structure 450 b First test part 440 to which different test voltages are applied a Second test part 440 b Respectively by the first connection structures 450 a And a second connection structure 450 b Electrically connected to the first circuit block 411 a Second circuit block 311 b Thus, the first circuit block 411 a Second circuit block 411 b The voltages in (a) are not equal, so that the first circuit block 411 can be detected a Second circuit block 411 b The magnitude of the leakage current therebetween determines whether there is a metal residue on the isolation structure 420 therebetween.
Unlike the prior art, the present invention provides a semiconductor structure 400 comprising: a substrate 410 having a plurality of circuit blocks 411, and the substrate 410 has opposite first surfaces S 1 And a second surface S 2 A plurality of isolation structures 420 penetrating the substrate 410 to electrically isolate the circuit blocks 411, and disposed on the first surface S of the substrate 410 1 An insulating layer 430 on the upper surface, and a plurality of test units 440 disposed on the insulating layer 430, the plurality of test units 440 being each located above a longitudinal projection of a corresponding circuit block 411, wherein a first test unit 440 of the plurality of test units 440 a Second test part 440 b Respectively by the first connection structures 450 a And a second connection structure 450 b Electrically connected to the first circuit block 411 a Second circuit block 411 b And a first test part 440 a Second test part 440 b The first circuit block 411 is correspondingly provided with a first test voltage and a second test voltage with different voltage values a Second circuit block 411 b Has a difference value so that the first circuit block 411 can be detected a Second circuit block 411 b Whether the leakage current is greater than a predetermined value or not is detected to determine whether the isolation structure 420 therebetween has a metal residue.
It should be understood that, in other variations of the present invention, the two test components for performing the test may be different from each other (i.e., the two test voltages are different, the two vertical distances are different, and the two relative dielectric constants are different) or the same (i.e., one of the two test voltages, the two vertical distances, and the two relative dielectric constants are the same, and the other two are different), so long as the substrate voltages in the corresponding circuit blocks are different, it is possible to determine whether the isolation structure between them has metal residues.
In addition to the embodiments described above, other embodiments of the invention are possible. All technical schemes adopting equivalent replacement or equivalent replacement fall within the protection scope of the invention.
In summary, although the preferred embodiments of the present invention have been described above, the above preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various modifications and adaptations without departing from the spirit and scope of the present invention, so that the scope of the present invention is defined by the claims.
Claims (10)
1. A semiconductor structure, the semiconductor structure comprising:
a substrate including a plurality of circuit blocks and having opposite first and second surfaces;
at least one isolation structure penetrating the substrate to electrically isolate the plurality of circuit blocks;
an insulating layer disposed on the first surface of the substrate;
the test parts are arranged on the insulating layer and are respectively positioned above the longitudinal projection of a corresponding circuit block;
wherein two of the plurality of test components are used for being applied with test voltages so that the substrate voltages in the corresponding two circuit blocks have a difference value;
the plurality of test components includes a first test component and a second test component disposed on the same insulating layer, wherein:
a first vertical distance is formed between the first test component and the first surface of the corresponding first circuit block, and a first test voltage is applied to the first test component;
a second vertical distance is formed between the second test part and the first surface of the corresponding second circuit block, and a second test voltage is applied to the second test part;
and wherein the first vertical distance is unequal to the second vertical distance, and the first test voltage is equal to the second test voltage.
2. The semiconductor structure of claim 1, wherein the isolation structure has a first length along a first lateral direction, and the test feature has a second length along the first lateral direction, wherein the first length is not greater than the second length.
3. The semiconductor structure of claim 1, wherein two of the test components to which the test voltage is applied are located above a longitudinal projection of both sides of the same isolation structure.
4. A semiconductor structure, the semiconductor structure comprising:
a substrate including a plurality of circuit blocks and having opposite first and second surfaces;
at least one isolation structure penetrating the substrate to electrically isolate the plurality of circuit blocks;
an insulating layer disposed on the first surface of the substrate;
the test parts are arranged on the insulating layer and are respectively positioned above the longitudinal projection of a corresponding circuit block;
wherein two of the plurality of test components are used for being applied with test voltages so that the substrate voltages in the corresponding two circuit blocks have a difference value;
the plurality of test components includes a first test component and a second test component, wherein:
the first test component is arranged on the first insulating layer, a first vertical distance is arranged between the first test component and the first surface of the corresponding first circuit block, a first test voltage is applied to the first test component, and the first insulating layer has a first relative dielectric constant;
the second test part is arranged on the second insulating layer, a second vertical distance is arranged between the second test part and the first surface of the corresponding second circuit block, a second test voltage is applied to the second test part, and the second insulating layer has a second relative dielectric constant;
and wherein the first vertical distance is equal to the second vertical distance, the first test voltage is equal to the second test voltage, and the first relative permittivity is not equal to the second relative permittivity.
5. The semiconductor structure of claim 4, wherein the isolation structure has a first length along a first lateral direction, and the test feature has a second length along the first lateral direction, wherein the first length is not greater than the second length.
6. The semiconductor structure of claim 4, wherein two of the test components to which the test voltage is applied are located above a longitudinal projection of both sides of the same isolation structure.
7. A method of fabricating a semiconductor structure, the method comprising:
providing a substrate, wherein the substrate comprises a plurality of circuit blocks and is provided with a first surface and a second surface which are opposite;
forming at least one isolation structure penetrating the substrate, the isolation structure electrically isolating the plurality of circuit blocks;
forming an insulating layer on the first surface of the substrate;
forming a plurality of test components on the insulating layer, wherein each test component is positioned above a longitudinal projection of a corresponding circuit block;
wherein two of the plurality of test components are used for being applied with test voltages so that the substrate voltages in the corresponding two circuit blocks have a difference value;
the plurality of test components includes a first test component and a second test component disposed on the same insulating layer, wherein:
a first vertical distance is formed between the first test component and the first surface of the corresponding first circuit block, and a first test voltage is applied to the first test component;
a second vertical distance is formed between the second test part and the first surface of the corresponding second circuit block, and a second test voltage is applied to the second test part;
and wherein the first vertical distance is unequal to the second vertical distance, and the first test voltage is equal to the second test voltage.
8. The method of claim 7, wherein the step of forming at least one isolation structure through the substrate comprises:
forming at least one isolation trench penetrating through the substrate and forming a plurality of through silicon trenches penetrating through the substrate;
filling an insulating material in the isolation groove to form the isolation structure, and filling the same insulating material in the silicon penetrating groove to form an insulating inner wall;
sequentially filling a blocking material and a conductive material into the silicon-penetrating groove to form a silicon-penetrating structure;
and etching to remove the blocking material and the conductive material remained on the first surface of the substrate.
9. A method of fabricating a semiconductor structure, the method comprising:
providing a substrate, wherein the substrate comprises a plurality of circuit blocks and is provided with a first surface and a second surface which are opposite;
forming at least one isolation structure penetrating the substrate, the isolation structure electrically isolating the plurality of circuit blocks;
forming an insulating layer on the first surface of the substrate;
forming a plurality of test components on the insulating layer, wherein each test component is positioned above a longitudinal projection of a corresponding circuit block;
wherein two of the plurality of test components are used for being applied with test voltages so that the substrate voltages in the corresponding two circuit blocks have a difference value;
the plurality of test components includes a first test component and a second test component, wherein:
the first test component is arranged on the first insulating layer, a first vertical distance is arranged between the first test component and the first surface of the corresponding first circuit block, a first test voltage is applied to the first test component, and the first insulating layer has a first relative dielectric constant;
the second test part is arranged on the second insulating layer, a second vertical distance is arranged between the second test part and the first surface of the corresponding second circuit block, a second test voltage is applied to the second test part, and the second insulating layer has a second relative dielectric constant;
and wherein the first vertical distance is equal to the second vertical distance, the first test voltage is equal to the second test voltage, and the first relative permittivity is not equal to the second relative permittivity.
10. The method of claim 9, wherein the step of forming at least one isolation structure through the substrate comprises:
forming at least one isolation trench penetrating through the substrate and forming a plurality of through silicon trenches penetrating through the substrate;
filling an insulating material in the isolation groove to form the isolation structure, and filling the same insulating material in the silicon penetrating groove to form an insulating inner wall;
sequentially filling a blocking material and a conductive material into the silicon-penetrating groove to form a silicon-penetrating structure;
and etching to remove the blocking material and the conductive material remained on the first surface of the substrate.
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