CN112765926B - Layout method and device of SRAM - Google Patents

Abstract

The invention provides a layout method and device of SRAM, the method includes: determining the positions of a virtual word line module, a virtual bit line module and a dummy module in an SRAM data path; determining a corresponding first layout strategy based on the number of target bits of the SRAM and the number of target multiplexers; determining a corresponding second layout strategy based on the number of the target words and the number of the target multiplexers; performing layout on the layout of the SRAM based on the first layout strategy and the second layout strategy; therefore, when the number of words, bits and mux of the SRAM changes, the corresponding layout strategy can be automatically determined according to the number of words, the number of bits and the number of multiplexers, independent customization of SRAM memory compilers with different capacities is not needed, automatic splicing and expansion of layout of the memory compilers can be efficiently realized, and the design efficiency of the memory compilers is improved.

Description

Layout method and device of SRAM

Technical Field

The present invention relates to the field of semiconductor technologies, and in particular, to a layout method and apparatus for an SRAM.

Background

Along with the improvement of integrated circuit industry technology, the product has higher intelligence, higher internal core processing frequency and stronger functions. In microprocessors and On-Chip processing Systems (SOC), the Chip area occupied by Static Random-Access Memory (SRAM) is continuously increasing, which causes the Memory delay and power consumption to correspondingly increase, and high-speed low-power consumption has become a trend of future integrated circuits. Therefore, research on the high-speed low-power-consumption SRAM technology is of great importance to the development of integrated circuits.

For SRAM Memory compilers (Memory compilers), users typically generate the required Memory from the generator of the Memory Compiler. The area, power consumption, and speed of the resulting memory are all very important to the user. In order to realize the SRAM with small area, low power consumption and high speed, the SRAM data path needs to be optimized, and then the layout method of the SRAM data path is very important.

The method adopted in the prior art generally carries out layout custom design aiming at SRAM with single capacity, but when the number of words, bits and multiplexing mux (multiplexer) is changed, the layout of SRAM with different capacities needs to be redesigned each time, so that the layout flow is complicated, and the layout efficiency cannot be ensured.

Disclosure of Invention

Aiming at the problems existing in the prior art, the embodiment of the invention provides a layout method and device of SRAM, which are used for solving the technical problems that the layout flow of the SRAM is complicated and the layout efficiency is not ensured because the SRAM with different capacities needs to be independently customized independently in the prior art.

The invention provides a layout method of SRAM, comprising the following steps:

determining the positions of a virtual word line module, a virtual bit line module and a dummy module in a data path of a Static Random Access Memory (SRAM);

Acquiring the number of target bits, the number of target words and the number of target multiplexers of the SRAM, and determining a corresponding first layout strategy based on the number of target bits and the number of target multiplexers; determining a corresponding second layout strategy based on the target word number and the target multiplexer number;

And laying out the layout of the SRAM based on the first layout strategy and the second layout strategy.

In the above scheme, the method further comprises:

when the ports of the SRAM are dual-port, determining the dummy word line module includes: a first virtual sub-line module and a second virtual word line module; the dummy bit line module includes: a first dummy bit line module and a second dummy bit line module; the dummy module includes: the first dummy module and the second dummy module; wherein,

The first virtual word line module and the second virtual word line module each include: a first word line module, a second word line module, and a third word line module; the first word line module, the second word line module and the third word line module comprise three rows and four columns of memory cells; the word lines in the first word line module are in a connection state, the word lines of the second word line module and the third word line module are in a disconnection state, and the word line disconnection positions of the second word line module and the third word line module are different.

In the above solution, the determining the corresponding first layout policy based on the number of target bits and the number of target multiplexers includes:

When the number of target bits M is even, M/2 is even, and the number of target multiplexers mux=4, the layout strategy corresponding to the first virtual word line module includes: sequentially laying out M/4 first word line modules, 1 second word line module and (M/4) -1 first word line module based on the positions of the first virtual word line modules in the data path;

When the target bit number M is even, M/2 is odd, and mux=4, the first layout policy corresponding to the first virtual word line module includes: sequentially laying out [ (M/2) -1]/2 first word line modules, 1 third word line module and [ (M/2) -1]/2 first word line modules based on the positions of the first virtual word line modules in the data path;

When the target bit number M is an odd number, (M-1)/2 is an even number, and the mux=4, the first layout strategy corresponding to the first virtual word line module includes: sequentially laying out (M-1)/4 first word line modules, 1 third word line module and (M-1)/4 first word line modules based on the positions of the first virtual word line modules in the data path;

when the target bit number M is an even number, (M-1)/2 is an odd number, and the mux=4, the first layout policy corresponding to the first virtual word line module includes: based on the position of the first virtual word line module in the data path, (M+1)/4 first word line modules, 1 second word line module and [ (M+1)/4 ] -1 first word line module are sequentially arranged.

In the above scheme, determining the corresponding first layout strategy based on the target bit number and the target multiplexer number includes:

When the number of target bits is even and the number mux=8 or 16, the first layout strategy corresponding to the first virtual word line module includes: sequentially laying out (mux x M)/16 first word line modules, 1 second word line module and [ (mux x M)/16 ] -1 first word line module based on the positions of the first virtual word line modules in the data path;

When the target bit number M is an odd number and the mux=8 or 16, the first layout policy corresponding to the first virtual word line module includes: sequentially laying out [ mux (m+1) ]/16 first word line modules, 1 second word line module and [ mux (m+1)/16 ] -1 first word line module based on the positions of the first virtual word line modules in the data path.

In the above scheme, determining the corresponding first layout strategy based on the target bit number and the target multiplexer number includes:

When the number of the target bits M is even, M/2 is even, and the number of the target multiplexers mux=4, the first layout strategy corresponding to the second virtual word line module includes: sequentially laying out M/4 first word line modules, 1 second word line module and (M/4) -1 first word line module based on the position of the second virtual word line module in the data path;

when the target bit number M is even, M/2 is odd, and mux=4, the first layout strategy corresponding to the second virtual word line module includes: sequentially laying out [ (M/2) -1]/2 first word line modules, 1 third word line module and [ (M/2) -1]/2 first word line modules based on the positions of the second virtual word line modules in the data path;

When the target bit number M is an odd number, (M-1)/2 is an even number, and the mux=4, the first layout strategy corresponding to the second virtual word line module includes: sequentially laying out (M-1)/4 first word line modules, 1 third word line module, and [ (M-1)/4 ] -1 first word line module based on the position of the second virtual word line module in the data path;

When the target bit number M is an odd number except 3, (M-1)/2 is an odd number, and the mux=4, the first layout strategy corresponding to the second virtual word line module includes: sequentially laying out [ (M-1)/2+1 ]/2 the first word line modules, 1 of the second word line modules, [ (M-1)/2 ] - [ (M-1)/2+1 ]/2-1 of the first word line modules, based on the positions of the second virtual word line modules in the data path;

When the target bit number M is 3 and the mux=4, the first layout strategy corresponding to the second virtual word line module includes: 1 of the first word line modules is laid out based on the position of the second virtual word line module in the data path.

In the above scheme, determining the corresponding first layout strategy based on the target bit number and the target multiplexer number includes:

When the target number of bits M is even and the target number of multiplexers mux=8 or 16, the first layout strategy corresponding to the second virtual word line module includes: sequentially laying out (mux x M)/16 first word line modules, 1 second word line module and [ (mux x M)/16 ] -1 first word line module based on the position of the second virtual word line module in the data path;

When the target number of bits M is an odd number except 3 and the mux=8 or 16, the first layout strategy corresponding to the second virtual word line module includes: sequentially laying out [ mux (m+1) ]/16 first word line modules, 1 second word line module, and mux (M-1)/8-mux (m+1)/16-1 first word line modules based on the positions of the second virtual word line modules in the data path;

When the target bit number M is 3 and the mux=8 or 16, the first layout strategy corresponding to the second virtual word line module includes: sequentially laying out [ mux (m+1) ]/16 first word line modules based on the positions of the second virtual word line modules in the data path.

In the above scheme, determining the corresponding second layout strategy based on the target word number and the target multiplexer number includes:

For a first virtual bit line module and a second virtual bit line module, determining the number of memory cell structures included in the first virtual bit line module and the second virtual bit line module according to N/(2 x mux), where the memory cell structures include: two rows and one column of memory cells;

sequentially laying out the memory cell structures according to a preset layout direction based on the positions of the first virtual bit line module and the second virtual bit line module in the data path; wherein,

The N is the target word number, the mux is the target multiplexer number, and word lines of the first virtual bit line module and the second virtual bit line module are connected with a common ground terminal VSS; a first bit line of each memory cell in the first virtual bit line module is connected with a first virtual bit line, and a second bit line of each memory cell in the first virtual bit line module is connected with a power supply VDD; the first bit line of each memory cell in the second virtual bit line module is connected to the VDD, and the second bit line of each memory cell in the second virtual bit line module is connected to the second virtual bit line.

In the above scheme, determining the corresponding second layout strategy based on the target word number and the target multiplexer number includes:

For a second dummy module, determining the number of the second dummy modules according to N/(2 x mux); the number of the first dummy modules comprises 1; the first dummy module comprises three rows and one column of storage units; wherein,

The N is the target word number, the mux is the target multiplexer number, the first dummy module is spliced with the first virtual word line module, and a bit line of the second dummy module is connected with a power supply VDD.

The invention also provides a layout device of the SRAM, which comprises:

the first determining unit is used for determining the positions of the virtual word line module, the virtual bit line module and the dummy module in a data path of the SRAM;

the second determining unit is used for obtaining the number of target bits, the number of target words and the number of target multiplexers of the SRAM, and determining a corresponding first layout strategy based on the number of target bits and the number of target multiplexers; determining a corresponding second layout strategy based on the target word number and the target multiplexer number;

and the layout unit is used for carrying out layout on the layout of the SRAM based on the first layout strategy and the second layout strategy.

In the above solution, the first determining unit is specifically further configured to:

When the ports of the SRAM are dual-port, determining the dummy word line module includes: a first virtual word line module and a second virtual word line module; the dummy bit line module includes: a first dummy bit line module and a second dummy bit line module; the dummy module includes: the first dummy module and the second dummy module; wherein,

The first virtual word line module and the second virtual word line module each include: a first word line module, a second word line module, and a third word line module; the first word line module, the second word line module and the third word line module are three rows and four columns of memory cells; the word lines in the first word line module are in a connection state, the word lines of the second word line module and the third word line module are in a disconnection state, and the word line disconnection positions of the second word line module and the third word line module are different.

The invention provides a layout method and device of SRAM, the method includes: determining the positions of a virtual word line module, a virtual bit line module and a dummy module in an SRAM data path; acquiring the number of target bits, the number of target words and the number of target multiplexers of the SRAM, and determining a corresponding first layout strategy based on the number of target bits and the number of target multiplexers; determining a corresponding second layout strategy based on the target word number and the target multiplexer number; designing the layout of the SRAM based on the first layout strategy and the second layout strategy; therefore, when the number of the word, the bit and the target multiplexer mux of the SRAM changes, the corresponding layout strategy can be automatically determined according to the number of the word, the bit and the mux, independent customization of SRAMs with different capacities is not needed, automatic design and expansion of the layout of the SRAM can be efficiently realized, and further the design efficiency of the layout of the SRAM can be improved.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to designate like parts throughout the figures. In the drawings:

FIG. 1 is a schematic diagram of a layout method of an SRAM according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a first word line module according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a second word line module according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a third word line module according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a layout structure of a dual-port SRAM according to an embodiment of the present invention;

FIG. 6 is a schematic diagram illustrating the positions of a first dummy bit line module, a first dummy word line module and a first dummy module according to an embodiment of the present invention;

FIG. 7 is a schematic diagram illustrating the positions of a second dummy bit line module, a second dummy word line module and a second dummy module according to an embodiment of the present invention;

fig. 8 is a schematic diagram of a layout corresponding to a first virtual word line module when the number of target bits M is even, M/2 is even, and mux=4 according to an embodiment of the present invention;

Fig. 9 is a schematic diagram of a layout corresponding to a first virtual word line module when the number of target bits M provided in the embodiment of the present invention is even, M/2 is odd, and mux=4;

Fig. 10 is a schematic diagram of a layout corresponding to a first virtual word line module when the number of target bits M provided in the embodiment of the present invention is an odd number, (M-1)/2 is an even number, and mux=4;

FIG. 11 is a schematic diagram of a layout corresponding to a first virtual word line module when the number of bits M of interest provided in the embodiment of the present invention is an odd number, (M-1)/2 is an odd number, and mux=4;

fig. 12 is a schematic diagram of a layout corresponding to a first virtual word line module when the number M of target bits provided in the embodiment of the present invention is even and mux=8 or 16;

fig. 13 is a schematic diagram of a layout corresponding to a first virtual word line module when the number of target bits M provided in the embodiment of the present invention is an odd number and mux=8 or 16;

fig. 14 is a layout diagram corresponding to a second virtual word line module when the number of target bits M provided in the embodiment of the present invention is an odd number, (M-1)/2 is an even number, and mux=4;

FIG. 15 is a schematic diagram of a layout corresponding to a second dummy word line module when the number M of target bits provided in the embodiment of the present invention is an odd number except 3, (M-1)/2 is an odd number, and mux=4;

Fig. 16 is a schematic diagram of a layout corresponding to a second virtual word line module when the number M of target bits provided in the embodiment of the present invention is 3 and mux=4;

Fig. 17 is a schematic diagram of a layout corresponding to a second virtual word line module when the number M of target bits provided in the embodiment of the present invention is even and mux=8 or 16;

fig. 18 is a schematic diagram of a layout corresponding to a second virtual word line module when the number M of target bits provided in the embodiment of the present invention is an odd number except 3 and mux=8 or 16;

Fig. 19 is a schematic diagram of a layout corresponding to a second virtual word line module when the number M of target bits provided in the embodiment of the present invention is 3 and mux=8 or 16;

FIG. 20 is a schematic diagram of a layout corresponding to a first dummy bit line module according to an embodiment of the present invention;

FIG. 21 is a schematic diagram of a layout corresponding to a second dummy bit line module according to an embodiment of the present invention;

FIG. 22 is a schematic diagram of a layout corresponding to a first dummy module and a second dummy module according to an embodiment of the present invention;

FIG. 23 is a schematic diagram of a layout device of an SRAM according to an embodiment of the present invention.

Detailed Description

In order to solve the technical problems that in the prior art, when layout is carried out on SRAM with different capacities, independent customization is needed for SRAM with corresponding capacities, so that the layout flow of the SRAM is complicated, and the layout efficiency cannot be ensured. The invention provides a layout method and device of SRAM.

In order to better understand the technical solutions described above, the technical solutions of the embodiments of the present specification are described in detail below through the accompanying drawings and the specific embodiments, and it should be understood that the specific features of the embodiments of the present specification and the specific features of the embodiments of the present specification are detailed descriptions of the technical solutions of the embodiments of the present specification, and not limit the technical solutions of the present specification, and the technical features of the embodiments of the present specification may be combined without conflict.

The embodiment provides a layout method of an SRAM, which is applied to a storage compiler, as shown in fig. 1, and comprises the following steps:

S110, determining positions of a virtual word line module, a virtual bit line module and a dummy module in an SRAM data path;

Here, a storage compiler can be understood as an application tool for generating SRAM of different capacities. The method provided by the embodiment of the invention can not only perform layout expansion on the SRAM with the existing capacity, but also perform layout for a new SRAM independently.

Because the SRAM in this embodiment is dual-ported, i.e. the ports are divided into two paths, before determining the positions of the dummy word line module, the dummy bit line module, and the dummy module in the SRAM data path, the method further includes:

When the SRAM is dual-ported (i.e., each memory cell is a dual-ported memory cell), determining the dummy word line module includes: a first virtual sub-line module and a second virtual word line module; the dummy bit line module includes: a first dummy bit line module and a second dummy bit line module; the dummy module includes: the first dummy module and the second dummy module; wherein, the first virtual word line module and the second virtual word line module all include: a first word line module, a second word line module, and a third word line module; the first word line module, the second word line module and the third word line module comprise three rows and four columns of memory cells; the word lines in the first word line module are in a connection state, the word lines of the second word line module and the third word line module are in a disconnection state, and the word line disconnection positions of the second word line module and the third word line module are different.

It should be noted that each SRAM includes a dummy word line module, a dummy bit line module, and a dummy module. For example, assuming that ports include port a and port B, each SRAM includes: word line WLA for port A, bit line BLA for port A; word line WLB for port B, bit line BLB for port B. Because the bit lines are typically present in pairs, port A also includes bit line BLA_ corresponding to bit line BLA, and port B also includes bit line BLB_ corresponding to bit line BLB.

Specifically, the structure of the first word line module may refer to fig. 2, the structure of the second word line module may refer to fig. 3, and the structure of the third word line module may refer to fig. 4. As can be seen from fig. 2, WLA of the first row of Memory cells (Memory cells) comprised by the first word line module is connected to the common ground terminal VSS, and WLB is also connected to VSS; WLA and WLB of the second and third rows of memory cells are connected to VSS or to dummy bit lines, depending on the location.

As can be seen from fig. 3, the open position of the second word line module is at row 2, column 1 and column 3, column 1; WLA of the 2 nd row and 1 st column memory cells and the 3 rd row and 1 st column memory cells are connected with a virtual word line MWLA, WLB of the 2 nd row and 1 st column memory cells and the 3 rd row and 1 st column memory cells are connected with a virtual word line MWLB; WLA and WLB of other memory cells are connected to VSS, respectively. That is, in fig. 3, the word lines of the memory cells at the left side portion of the off position of the second word line module are connected to the corresponding dummy word lines, and the right side portion serves as a load.

As can be seen from fig. 4, the open position of the third word line module is at the 2 nd row, 2 nd column, and 3 rd row, 3 rd column positions; WLA of the memory cells of the 2 nd row, the 1 st column, the 2 nd row, the 2 nd column, the 2 nd row, the 3 rd row, the 1 st column, the 3 rd row, the 2 nd column and the 3 rd row, and the 3 rd column are connected with a virtual word line MWLA, and WLB and MWLB of the memory cells of the 3 rd row and the 3 rd column are connected; WLA and WLB of other memory cells are connected to VSS, respectively. That is, in fig. 4, the word lines of the memory cells at the left side portion of the off position of the third word line module are connected to the corresponding dummy word lines, and the right side portion serves as a load.

Here, when expanding the layout of the SRAM with a certain capacity, in order to simulate the external clock to generate the on-chip clock signal GTP, in this embodiment, a dummy word line and a dummy bit line are expanded in the original memory array of the SRAM, and then the dummy word line includes: a first virtual word line MWLA of port a and a second virtual word line MWLB of port B; the dummy bit line includes: the first dummy bit line MBLA of port A and the second dummy bit line MBLB of port B.

Then, the positions of the dummy word line module, the dummy bit line module and the dummy module in the SRAM data path need to be determined.

Referring to fig. 5, the layout of the dual port SRAM includes a data path layout, a clock control layout, and a decoding layout. In this embodiment, the virtual word line module, the virtual bit line module, and the dummy module are all located in the data path layout; wherein the data path comprises: first data path dp_xr_right and second data path dp_xl_left. The first data path is located on the right side of the clocking and decoding layout and the second data path is located on the left side of the clocking and decoding layout.

Referring to fig. 6, after expanding the SRAM layout, in the first data path, the first dummy bit line module is located on the left side of the right memory array, the first dummy word line module is located above the right memory array, the first dummy module is located on the right side of the right memory array, and the column strobe, sense amplifier and IO circuit are further connected below the right memory array. As can be seen from FIG. 6, the first dummy bit line module, the first dummy word line module, and the first dummy module have the identifier R0, which indicates that the first dummy bit line module, the first dummy word line module, and the first dummy module do not need to be flipped in the layout.

Referring to fig. 7, after expanding the SRAM layout, in the second data path, the second dummy bit line module is located on the right side of the left side memory array, the second dummy word line module is located above the left side memory array, and the second dummy module is located on the left side of the left side memory array, and the column strobe, sense amplifier and IO circuit are further connected below the left side memory array. The second virtual word line module, the second virtual bit line module and the second dummy module are turned over along the Y axis and then are distributed in the layout in consideration of the overall symmetrical layout. As can be seen from FIG. 7, the second dummy bit line module, the second dummy word line module, and the second dummy module have the marks MY, which indicate that the second dummy bit line module, the second dummy word line module, and the second dummy module need to be turned over along the Y-axis in the layout so as to be symmetrically laid out in the layout and reduce the routing distance.

It should be noted that, the dummy word line module is located at the position farthest from the word line driving circuit in the layout, and then the feedback circuit will automatically include the influence of the metal connection on the bit line delay, so as to realize self-timing. The self-timing strategy can more accurately cut off the word line gating, stop the bit line discharging and reduce the amplitude of the bit line, thereby being more beneficial to reducing the power consumption of the SRAM.

S111, acquiring the number of target bits, the number of target words and the number of target multiplexers of the SRAM, and determining a corresponding first layout strategy based on the number of target bits and the number of target multiplexers; determining a corresponding second layout strategy based on the target word number and the target multiplexer number;

It should be noted that the target number of bits M is the number of data paths; the relationship between the target bit number M and the target bit line BL is: bl=m×mux, and the target bit line BL is the column number of the total memory cell.

The relationship between the target word line WL and the target word N is: wl=n/mux, the target word line WL is the row number of memory cells.

Thus, after the number of target word lines WL, target bit lines BL, and target multiplexers is determined, the target bit number M and the target word number N can be determined.

The layout expansion of the first virtual word line module and the second virtual word line module is influenced by the bit M and mux, and when M is an even number, the first virtual word line module and the second virtual word line module are symmetrical, and the layout modes are the same; and when M is an odd number, the first virtual word line module and the second virtual word line module are asymmetric, and the layout modes are different.

Therefore, after the positions of the virtual word line module, the virtual bit line module and the dummy module in the data path of the SRAM are determined, the target bit number M, the target word number N and the target multiplexer number mux of the SRAM are obtained, the corresponding first layout policy target word number N and the corresponding second layout policy are determined based on the target bit number M and the target multiplexer number mux. It should be noted that, in the embodiment of the present invention, the number of target bits M is at least 2, and the number of target words N is at least 128.

As an alternative embodiment, determining the corresponding first layout strategy based on the number of target bits and the number of target multiplexers includes:

when the number of target bits M is even, M/2 is even, and mux=4, the layout strategy corresponding to the first virtual word line module includes: in the front view of the layout, M/4 first word line modules, 1 second word line module and (M/4) -1 first word line module are sequentially arranged from left to right based on the position of the first virtual word line module in the first data path. The layout of this case can be seen with reference to fig. 8.

For example, when m=4, the corresponding layout strategies include: 1 first word line module and 1 second word line module are sequentially arranged from left to right.

When the number of target bits M is even, M/2 is odd, and mux=4, the first layout strategy corresponding to the first virtual word line module includes: in the front view of the layout, [ (M/2) -1]/2 first word line modules, 1 third word line module and [ (M/2) -1]/2 first word line modules are sequentially arranged from left to right based on the positions of the first virtual word line modules in the first data path. The layout of this case can be seen with reference to fig. 9.

For example, when M is 6, 1 first word line module, 1 third word line module, and 1 first word line module are laid out in order from left to right.

When the target bit number M is an odd number, (M-1)/2 is an even number, and mux=4, the first layout strategy corresponding to the first virtual word line module includes: sequentially laying out (M-1)/4 first word line modules, 1 third word line module and (M-1)/4 first word line modules based on the positions of the first virtual word line modules in the first data path; the layout of this case can be seen with reference to fig. 10.

For example, when M is 5, 1 first word line module, 1 third word line module, and 1 first word line module are laid out in order from left to right.

When the number of target bits M is even, (M-1)/2 is odd, and mux=4, the first layout strategy corresponding to the first virtual word line module includes: sequentially laying out (M+1)/4 first word line modules, 1 second word line module and [ (M+1)/4 ] -1 first word line module based on the position of the first virtual word line module in the first data path; the layout of this case can be seen with reference to fig. 11.

For example, when M is 7, 2 first word line modules, 1 third word line module, and 1 first word line module are laid out in order from left to right.

As an alternative embodiment, when the target number of bits M is an even number and mux=8 or 16, the first layout policy corresponding to the first virtual word line module includes: sequentially laying out (mux x M)/16 first word line modules, 1 second word line module and [ (mux x M)/16 ] -1 first word line module based on the position of the first virtual word line module in the first data path; the layout of this case can be seen with reference to fig. 12.

For example, when M is 2 and mux is 8, 1 first word line module and 1 second word line module are sequentially laid out from left to right.

When the target number of bits M is an odd number and mux=8 or 16, the first layout strategy corresponding to the first virtual word line module includes: sequentially arranging [ mux (M+1) ]/16 first word line modules, 1 second word line module and [ mux (M+1)/16 ] -1 first word line modules from left to right based on the position of the first virtual word line module in the first data path; the layout of this case can be seen with reference to fig. 13.

For example, when M is 3 and mux is 8, 2 first word line modules, 1 second word line module, and 1 first word line module are sequentially laid out from left to right.

Similarly, for the second virtual word line module, determining a corresponding first layout strategy based on the target number of bits and the target number of multiplexers includes:

When the number of target bits M is even, M/2 is even, and mux=4, the first layout strategy corresponding to the second virtual word line module includes: sequentially laying out M/4 first word line modules, 1 second word line module and (M/4) -1 first word line module from left to right based on the position of the second virtual word line module in the second data path; the layout is the same as the layout of the first dummy word line module, and the layout can refer to fig. 8, which is not described here again.

When the number of target bits M is even, M/2 is odd, and mux=4, the first layout strategy corresponding to the second virtual word line module includes: sequentially arranging [ (M/2) -1]/2 first word line modules, 1 third word line module and [ (M/2) -1]/2 first word line modules from left to right based on the position of the second virtual word line module in the second data path; the layout is the same as the layout of the first dummy word line module, and the layout can refer to fig. 9, which is not described herein.

When the target bit number M is an odd number, (M-1)/2 is an even number, and mux=4, the first layout strategy corresponding to the second virtual word line module includes: sequentially arranging (M-1)/4 first word line modules, 1 third word line module and [ (M-1)/4 ] -1 first word line module from left to right based on the position of the second virtual word line module in the second data path; the layout of this case can be seen with reference to fig. 14.

For example, when M is 5, 1 first word line module and 1 third word line module are laid out in order from left to right.

When the target bit number M is an odd number except 3, (M-1)/2 is an odd number, and mux=4, the first layout strategy corresponding to the second virtual word line module includes: sequentially arranging [ (M-1)/2+1 ]/2 first word line modules, 1 second word line module and [ (M-1)/2 ] - [ (M-1)/2+1 ]/2-1 first word line modules based on the position of the second virtual word line module in the second data path; the layout of this case can be seen with reference to fig. 15.

For example, when M is 7, 2 first word line modules and 1 second word line module are laid out in order from left to right.

When the target bit number M is 3 and mux=4, the first layout strategy corresponding to the second virtual word line module includes: laying out 1 first word line module based on the position of the second virtual word line module in the second data path; the layout of this case can be seen with reference to fig. 16.

When mux=8 or 16, as an alternative embodiment, determining the corresponding first layout policy based on the target number of bits and the target number of multiplexers includes:

when the target number of bits M is even and mux=8 or 16, the first layout strategy corresponding to the second virtual word line module includes: sequentially laying out (mux M)/16 first word line modules, 1 second word line module and [ (mux M)/16 ] -1 first word line module from left to right based on the position of the second virtual word line module in the second data path; the layout of this case can be seen with reference to fig. 17.

For example, when M is 2 and mux is 8, 1 first word line module and 1 second word line module are laid out in order from left to right.

When the target number of bits M is an odd number except 3 and mux=8 or 16, the first layout strategy corresponding to the second virtual word line module includes: sequentially laying out [ mux (m+1) ]/16 first word line modules, 1 second word line module, and [ mux (M-1)/8-mux (m+1)/16-1 ] first word line modules based on the positions of the second virtual word line modules in the second data path; the layout of this case can be seen with reference to fig. 18.

For example, when M is 5 and mux is 8, 3 first word line modules and 1 second word line module are laid out in order from left to right.

When the target bit number M is 3 and mux=8 or 16, the first layout strategy corresponding to the second virtual word line module includes: sequentially laying out [ mux (m+1) ]/16 first word line modules based on the positions of the second virtual word line modules in the second data path; the layout of this case can be referred to in fig. 19.

After the first layout strategy corresponding to the first virtual word line module and the second virtual word line module is determined, the second layout strategy corresponding to the first virtual bit line module, the second virtual bit line module, the first dummy module and the second dummy module is also determined.

As an alternative embodiment, determining the corresponding second layout strategy based on the target word number and the target multiplexer number includes:

For the first virtual bit line module and the second virtual bit line module, determining the number of memory cell structures included in the first virtual bit line module and the second virtual bit line module according to N/(2 x mux), where the memory cell structures include: two rows and one column of memory cells;

sequentially laying out the memory cell structures according to a preset layout direction based on the positions of the first virtual bit line module and the second virtual bit line module in the corresponding data paths; wherein,

The word line of the first virtual bit line module and the word line of the second virtual bit line module are connected with a common ground terminal VSS; a first bit line of each memory cell in the first virtual bit line module is connected with the first virtual bit line, and a second bit line of each memory cell in the first virtual bit line module is connected with a power supply VDD; the first bit line of each memory cell in the second dummy bit line module is connected to VDD, and the second bit line of each memory cell in the second dummy bit line module is connected to the second dummy bit line. Word lines of each memory cell in the first virtual module and the second virtual module are connected with VSS. Wherein, the first bit line may be the bit line BLA of the port A, and the second bit line may be the bit line BLB of the port B; the first dummy bit line is MBLA and the second dummy bit line is MBLB. The layout corresponding to the first dummy bit line module may refer to fig. 20, and the layout corresponding to the second dummy bit line module may refer to fig. 21.

As an alternative embodiment, determining the corresponding second layout strategy based on the target word number and the target multiplexer number includes:

Determining the number of the second dummy modules according to N/(2 x mux) for the second dummy modules; the number of the first dummy modules comprises 1; the first dummy module comprises three rows and one column of storage units; wherein,

The first dummy module is spliced with the first virtual word line module, a bit line of the second dummy module is connected with the power supply VDD, and the second dummy module is mainly used for providing load. The layout of the first dummy module and the second dummy module may refer to fig. 22.

Thus, the layout strategies corresponding to the virtual word line module, the virtual bit line module and the dummy module can be determined.

In all the drawings in this embodiment, the memory cell is the same. For any memory cell, if the mark R0 exists, the memory cell is not required to be flipped; if the mark R180 exists and if the mark MX exists, the storage unit needs to be turned over along the X axis; if the marker MY is present, this indicates that the memory cell needs to be flipped along the Y-axis.

S112, designing the layout of the SRAM based on the first layout strategy and the second layout strategy.

After the layout strategies of the virtual word line module, the virtual bit line module and the dummy module are determined, the layout of the SRAM is designed based on the first layout strategy and the second layout strategy. Therefore, the corresponding layout strategy can be automatically determined according to the number of word lines, the number of bit lines and the number of mux, independent customization of SRAM with different capacities is not needed, automatic splicing and expansion of the layout of the storage compiler can be efficiently realized, and the design efficiency of the storage compiler can be improved.

In addition, in this embodiment, the external clock CLK can be simulated to generate the on-chip clock signal GTP, which generates the dummy word line signal MWL, the dummy bit line signal is discharged by the dummy word line signal, and after the discharge is completed, the reset signal RST is triggered to reset the GTP signal to 0. In the whole feedback loop, the discharging process of the virtual word line to the virtual bit line can be quickened, so that the RST signal is advanced, the word line is promoted to be turned off in advance, the discharging time and the swing amplitude on the bit line are controlled within the required range, and the power consumption is reduced.

It should be noted that the external clock includes CLKA and CLKB, and the external clock CLKA can be simulated to generate the on-chip clock signal GTPA, which generates the virtual word line signal MWLA in the present embodiment; the analog external clock CLKB generates the on-chip clock signal GTPB, and the virtual word line signal MWLB.

Based on the same inventive concept as the previous embodiment, the embodiment of the present invention further provides a layout device of an SRAM, as shown in fig. 23, where the device includes:

A first determining unit 21, configured to determine positions of the dummy word line module, the dummy bit line module, and the dummy module in a data path of the SRAM;

A second determining unit 22, configured to obtain a target bit number, a target word number, and a target multiplexer number of the SRAM, and determine a corresponding first layout policy based on the target bit number and the target multiplexer number; determining a corresponding second layout strategy based on the target word number and the target multiplexer number;

And a layout unit 23, configured to layout the layout of the SRAM based on the first layout policy and the second layout policy.

The first determining unit 21 is specifically configured to:

When the ports of the SRAM are dual-port, determining the dummy word line module includes: a first virtual sub-line module and a second virtual word line module; the dummy bit line module includes: a first dummy bit line module and a second dummy bit line module; the dummy module includes: the first dummy module and the second dummy module; wherein the first virtual word line module and the second virtual word line module each comprise: a first word line module, a second word line module, and a third word line module; the first word line module, the second word line module and the third word line module are three rows and four columns of memory cells; the word lines in the first word line module are in a connection state, the word lines of the second word line module and the third word line module are in a disconnection state, and the word line disconnection positions of the second word line module and the third word line module are different.

Here, the second determining unit 22 determines the positions of the dummy word line module, the dummy bit line module, and the dummy module in the data path of the SRAM as described in detail above, and will not be described again. The third determining unit 23 is configured to obtain the number of SRAM target bits, the number of target words, and the number of target multiplexers mux, and determine a corresponding first layout policy based on the number of target bits and the number of target multiplexers; the implementation of determining the corresponding second layout policy based on the number of target words and the number of target multiplexers is also described in detail above, and will not be described in detail here. The layout unit 24 designs the layout of the SRAM based on the first layout policy and the second layout policy, which are described in detail above, and thus will not be described in detail herein.

The layout method and device of the SRAM provided by the embodiment of the invention have the following beneficial effects:

The invention provides a layout method and device of SRAM, the method includes: determining the positions of a virtual word line module, a virtual bit line module and a dummy module in a data path of the SRAM; acquiring the number of target bits, the number of target words and the number of target multiplexers of the SRAM, and determining a corresponding first layout strategy based on the number of target bits and the number of target multiplexers; determining a corresponding second layout strategy based on the target word number and the target multiplexer number; layout of the SRAM is laid out based on the first layout strategy and the second layout strategy; therefore, when the number of words, bits and the number mux of the target multiplexers of the SRAM changes, the corresponding layout strategy can be automatically determined according to the numbers of the words, bits and mux, independent customization of SRAMs with different capacities is not needed, automatic design and expansion of the layout of the SRAM can be efficiently realized, and the design efficiency of the layout of the stored SRAM can be improved; furthermore, the design efficiency of the storage compiler can be improved, and the generation efficiency of the SRAM is also improved; in addition, the embodiment of the invention adds a virtual word line beside the memory array through a word line copying technology, matches the load of the word line, combines with a bit line copying technology to simulate the delay of an actual signal path, ensures that detection enable arrives when the amplitude of the bit line reaches an expected value, further accelerates the access process, reduces the amplitude of the bit line, and achieves the effect of reducing power consumption.

The above description is not intended to limit the scope of the invention, but is intended to cover any modifications, equivalents, and improvements within the spirit and principles of the invention.

Claims (10)

1. The layout method of the SRAM is characterized by comprising the following steps:

Determining the positions of a virtual word line module, a virtual bit line module and a dummy module in an SRAM data path of a static random access memory;

Acquiring the number of target bits, the number of target words and the number of target multiplexers of the SRAM, and determining a corresponding first layout strategy based on the number of target bits and the number of target multiplexers; determining a corresponding second layout strategy based on the target word number and the target multiplexer number;

And laying out the layout of the SRAM based on the first layout strategy and the second layout strategy.

2. The method of claim 1, wherein the method further comprises:

When the ports of the SRAM are dual-port, determining the dummy word line module includes: a first virtual word line module and a second virtual word line module; the dummy bit line module includes: a first dummy bit line module and a second dummy bit line module; the dummy module includes: the first dummy module and the second dummy module; wherein,

The first virtual word line module and the second virtual word line module each include: a first word line module, a second word line module, and a third word line module; the first word line module, the second word line module and the third word line module comprise three rows and four columns of memory cells; the word lines in the first word line module are in a connection state, the word lines of the second word line module and the third word line module are in a disconnection state, and the word line disconnection positions of the second word line module and the third word line module are different.

3. The method of claim 1, wherein determining a corresponding first layout strategy based on the target number of bits and the target number of multiplexers comprises:

When the number of target bits M is even, M/2 is even, and the number of target multiplexers mux=4, the layout strategy corresponding to the first virtual word line module includes: sequentially laying out M/4 first word line modules, 1 second word line module and (M/4) -1 first word line module based on the positions of the first virtual word line modules in the data path;

When the target bit number M is even, M/2 is odd, and mux=4, the first layout policy corresponding to the first virtual word line module includes: sequentially laying out [ (M/2) -1]/2 first word line modules, 1 third word line module and [ (M/2) -1]/2 first word line modules based on the positions of the first virtual word line modules in the data path;

When the target bit number M is an odd number, (M-1)/2 is an even number, and the mux=4, the first layout strategy corresponding to the first virtual word line module includes: sequentially laying out (M-1)/4 first word line modules, 1 third word line module and (M-1)/4 first word line modules based on the positions of the first virtual word line modules in the data path;

when the target bit number M is an even number, (M-1)/2 is an odd number, and the mux=4, the first layout policy corresponding to the first virtual word line module includes: based on the position of the first virtual word line module in the data path, (M+1)/4 first word line modules, 1 second word line module and [ (M+1)/4 ] -1 first word line module are sequentially arranged.

4. The method of claim 1, wherein determining a corresponding first layout strategy based on the target number of bits and the target number of multiplexers comprises:

when the number M of the target bits is even and the number mux=8 or 16 of the target multiplexers, the first layout strategy corresponding to the first virtual word line module includes: sequentially laying out (mux x M)/16 first word line modules, 1 second word line module and [ (mux x M)/16 ] -1 first word line module based on the positions of the first virtual word line modules in the data path;

When the target bit number M is an odd number and the mux=8 or 16, the first layout policy corresponding to the first virtual word line module includes: sequentially laying out [ mux (m+1) ]/16 first word line modules, 1 second word line module and [ mux (m+1)/16 ] -1 first word line module based on the positions of the first virtual word line modules in the data path.

5. The method of claim 1, wherein determining a corresponding first layout strategy based on the target number of bits and the target number of multiplexers comprises:

When the number of the target bits M is even, M/2 is even, and the number of the target multiplexers mux=4, the first layout strategy corresponding to the second virtual word line module includes: sequentially laying out M/4 first word line modules, 1 second word line module and (M/4) -1 first word line module based on the position of the second virtual word line module in the data path;

when the target bit number M is even, M/2 is odd, and mux=4, the first layout strategy corresponding to the second virtual word line module includes: sequentially laying out [ (M/2) -1]/2 first word line modules, 1 third word line module and [ (M/2) -1]/2 first word line modules based on the positions of the second virtual word line modules in the data path;

When the target bit number M is an odd number, (M-1)/2 is an even number, and the mux=4, the first layout strategy corresponding to the second virtual word line module includes: sequentially laying out (M-1)/4 first word line modules, 1 third word line module, and [ (M-1)/4 ] -1 first word line module based on the position of the second virtual word line module in the data path;

When the target bit number M is an odd number except 3, (M-1)/2 is an odd number, and the mux=4, the first layout strategy corresponding to the second virtual word line module includes: sequentially laying out [ (M-1)/2+1 ]/2 the first word line modules, 1 of the second word line modules, [ (M-1)/2 ] - [ (M-1)/2+1 ]/2-1 of the first word line modules, based on the positions of the second virtual word line modules in the data path;

When the target bit number M is 3 and the mux=4, the first layout strategy corresponding to the second virtual word line module includes: 1 of the first word line modules is laid out based on the position of the second virtual word line module in the data path.

6. The method of claim 1, wherein determining a corresponding first layout strategy based on the target number of bits and the target number of multiplexers comprises:

When the number M of the target bits is even and the number mux=8 or 16 of the target multiplexers, the first layout strategy corresponding to the second virtual word line module includes: sequentially laying out (mux x M)/16 first word line modules, 1 second word line module and [ (mux x M)/16 ] -1 first word line module based on the position of the second virtual word line module in the data path;

When the target number of bits M is an odd number except 3 and the mux=8 or 16, the first layout strategy corresponding to the second virtual word line module includes: sequentially laying out [ mux (m+1) ]/16 first word line modules, 1 second word line module, and mux (M-1)/8-mux (m+1)/16-1 first word line modules based on the positions of the second virtual word line modules in the data path;

When the target bit number M is 3 and the mux=8 or 16, the first layout strategy corresponding to the second virtual word line module includes: sequentially laying out [ mux (m+1) ]/16 first word line modules based on the positions of the second virtual word line modules in the data path.

7. The method of claim 1, wherein determining a corresponding second layout strategy based on the target number of words and the target number of multiplexers comprises:

For a first virtual bit line module and a second virtual bit line module, determining the number of memory cell structures included in the first virtual bit line module and the second virtual bit line module according to N/(2 x mux), where the memory cell structures include: two rows and one column of memory cells;

sequentially laying out the memory cell structures according to a preset layout direction based on the positions of the first virtual bit line module and the second virtual bit line module in the data path; wherein,

The N is the target word number, the mux is the target multiplexer number, and word lines of the first virtual bit line module and the second virtual bit line module are connected with a common ground terminal VSS; a first bit line of each memory cell in the first virtual bit line module is connected with a first virtual bit line, and a second bit line of each memory cell in the first virtual bit line module is connected with a power supply VDD; the first bit line of each memory cell in the second virtual bit line module is connected to the VDD, and the second bit line of each memory cell in the second virtual bit line module is connected to the second virtual bit line.

8. The method of claim 1, wherein determining a corresponding second layout strategy based on the target number of words and the target number of multiplexers comprises:

For a second dummy module, determining the number of the second dummy modules according to N/(2 x mux); the number of the first dummy modules comprises 1; the first dummy module comprises three rows and one column of storage units; wherein,

The N is the target word number, the mux is the target multiplexer number, the first dummy module is spliced with the first virtual word line module, and a bit line of the second dummy module is connected with a power supply VDD.

9. A layout device of an SRAM, the device comprising:

The first determining unit is used for determining the positions of the virtual word line module, the virtual bit line module and the dummy module in a data path of the SRAM;

the second determining unit is used for obtaining the number of target bits, the number of target words and the number of target multiplexers of the SRAM, and determining a corresponding first layout strategy based on the number of target bits and the number of target multiplexers; determining a corresponding second layout strategy based on the target word number and the target multiplexer number;

and the layout unit is used for carrying out layout on the layout of the SRAM based on the first layout strategy and the second layout strategy.

10. The apparatus of claim 9, wherein the first determining unit is further to:

When the ports of the SRAM are dual-port, determining the dummy word line module includes: a first virtual word line module and a second virtual word line module; the dummy bit line module includes: a first dummy bit line module and a second dummy bit line module; the dummy module includes: the first dummy module and the second dummy module; wherein,

The first virtual word line module and the second virtual word line module each include: a first word line module, a second word line module, and a third word line module; the first word line module, the second word line module and the third word line module are three rows and four columns of memory cells; the word lines in the first word line module are in a connection state, the word lines of the second word line module and the third word line module are in a disconnection state, and the word line disconnection positions of the second word line module and the third word line module are different.