CN112751393B - Balancing chip of series battery pack and battery management system - Google Patents
Balancing chip of series battery pack and battery management system Download PDFInfo
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- CN112751393B CN112751393B CN202110135445.0A CN202110135445A CN112751393B CN 112751393 B CN112751393 B CN 112751393B CN 202110135445 A CN202110135445 A CN 202110135445A CN 112751393 B CN112751393 B CN 112751393B
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- 238000010586 diagram Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- WHXSMMKQMYFTQS-UHFFFAOYSA-N Lithium Chemical compound [Li] WHXSMMKQMYFTQS-UHFFFAOYSA-N 0.000 description 3
- 229910052744 lithium Inorganic materials 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
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- 238000002485 combustion reaction Methods 0.000 description 1
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- 238000004880 explosion Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0013—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries acting upon several batteries simultaneously or sequentially
- H02J7/0014—Circuits for equalisation of charge between batteries
- H02J7/0019—Circuits for equalisation of charge between batteries using switched or multiplexed charge circuits
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- Charge And Discharge Circuits For Batteries Or The Like (AREA)
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Abstract
The present disclosure provides an equalization chip of a series battery pack, the equalization chip comprising: the first end of the ith control switch of the i control switches is connected with the positive electrode end of the ith battery through an equalizing resistor, and the second end of the ith control switch is connected with the positive electrode end of the i-1 th battery; and i first resistors, a first end of an i first resistor of the i first resistors being connected to a second end of an i control switch, and a second end of the i first resistor being connected to a control end of the i control switch, the i control switch being controlled to: when the current flowing from the positive terminal of the ith battery to the positive terminal of the ith-1 th battery is greater than the current threshold, the ith control switch is turned on based on the voltage generated by the ith first resistor, so that the current flows through the ith control switch to perform current balancing on the ith battery, wherein 1 < i.ltoreq.N. The present disclosure also provides a battery management system.
Description
Technical Field
The present disclosure relates to an equalization chip for a series battery pack and a battery management system.
Background
Rechargeable batteries such as lithium batteries have high charge and discharge requirements, and when overcharge, overdischarge, overcurrent, short-circuit, etc. occur, internal pressure and heat of the lithium batteries are greatly increased, and sparks, combustion, and even explosion are easily generated, so that overcharge and overdischarge protection of the lithium battery pack is necessary.
With the use of batteries, the performance of each battery may be inconsistent, and there may be imbalance problems, such as charging during charge and discharge, for example, some batteries may have been fully charged, some batteries may have not been fully charged, or some batteries may have been overcharged. The same is true of the discharge process.
Due to the inconsistency of the individual cells, necessary equalization measures are required to ensure the safety and stability thereof at the time of charging.
In addition, in the related art, a circuit for equalization control is provided on a printed circuit board, which does not conform to the trend of miniaturization and integration, or the like.
Disclosure of Invention
In order to solve one of the above technical problems, the present disclosure provides an equalization chip and a battery management system for a serial battery pack.
According to one embodiment of the present disclosure, an equalization chip for a series battery pack, the series battery pack comprising N series batteries, where N > 1, the equalization chip comprising:
The first end of the ith control switch of the i control switches is connected with the positive electrode end of the ith battery through an equalizing resistor, and the second end of the ith control switch is connected with the positive electrode end of the i-1 th battery; and
I first resistors, a first end of an i first resistor of the i first resistors is connected with a second end of the i control switch, and a second end of the i first resistor is connected with a control end of the i control switch,
The ith control switch is controlled to: when the current flowing from the positive terminal of the ith battery to the positive terminal of the ith-1 th battery is greater than a current threshold, the ith control switch is turned on based on the voltage generated by the ith first resistor, so that the current flows through the ith control switch to perform current balancing on the ith battery, wherein 1 < i.ltoreq.N.
According to the equalizing chip of at least one embodiment of the present disclosure, the i control switches are NMOS transistors, the first ends of the i control switches are drains, the second ends of the i control switches are sources, and the control ends of the i control switches are gates; or the i control switches are triodes, the first ends of the i control switches are collectors, the second ends of the i control switches are emitters, and the control ends of the i control switches are bases.
The equalization chip according to at least one embodiment of the present disclosure further includes i second resistors, a first end of an i second resistor of the i second resistors is connected to a control end of the i control switch, and a second end of the i second resistor is connected to a second end of the i first resistor.
The equalization chip according to at least one embodiment of the present disclosure further includes i first diodes, an anode of an i first diode of the i first diodes is connected to a first terminal of the i control switch, and a cathode of the i first diode is grounded.
The equalization chip according to at least one embodiment of the present disclosure further comprises i second diodes, wherein an anode of an i second diode of the i second diodes is connected to the second end of the control switch, and a cathode of the i second diode is connected to the control end of the control switch.
The equalization chip according to at least one embodiment of the present disclosure further includes i third diodes, wherein an anode of an i second triode of the i second triodes is connected to a second end of the i+1 first resistor, and a cathode of the i second triode is connected to a second end of the i first resistor.
According to the equalizing chip of at least one embodiment of the present disclosure, the current flowing from the positive terminal of the i-th battery to the positive terminal of the i-1-th battery is controlled by the on and off of the i-th first switch, and when the i-th first switch is on, the current flows from the positive terminal of the i-th battery to the positive terminal of the i-1-th battery.
The equalization chip according to at least one embodiment of the present disclosure, the i first switches are integrated in the equalization chip.
The equalization chip according to at least one embodiment of the present disclosure further includes i current control circuits, a first end of an i current control circuit of the i current control circuits is connected to a second end of an i+1 first resistor, and a second end of the i current control circuit is connected to a second end of the i first resistor.
According to the equalizing chip of at least one embodiment of the present disclosure, the current generated by each of the i-th current control circuits is controlled based on the voltage of the positive terminal of the nth battery and the voltage of the positive terminal of the i-1 th battery.
According to the equalization chip of at least one embodiment of the present disclosure, when equalization control is required for the ith battery, the ith current control circuit operates.
According to an equalizing chip of at least one embodiment of the present disclosure, the i current control circuits respectively include a mirror circuit and a current source generating a current based on a voltage of a positive terminal of an nth battery and generating a current flowing into a second terminal of an ith first resistor via the mirror current.
According to the equalizing chip of at least one embodiment of the present disclosure, the current generated by each of the i-th current control circuits is controlled based on the voltage of the positive terminal of the i-th battery and the voltage of the positive terminal of the i-1 th battery.
According to the equalization chip of at least one embodiment of the present disclosure, when equalization control is required for the ith battery, the ith current control circuit operates.
According to an equalizing chip of at least one embodiment of the present disclosure, the i current control circuits respectively include a mirror circuit and a current source generating a current based on a voltage of a positive terminal of an i-th battery and generating a current flowing into a second terminal of the i-th first resistor via the mirror current.
According to another embodiment of the present disclosure, a battery management system includes:
An equalizing circuit as described above; and
And a battery management chip that measures a voltage of the i-th battery at least via the equalization circuit.
Drawings
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.
Fig. 1 shows a schematic diagram of a battery management system according to one embodiment of the present disclosure.
Fig. 2 shows a schematic diagram of a battery management system according to one embodiment of the present disclosure.
Fig. 3 shows a schematic diagram of a battery management system according to one embodiment of the present disclosure.
Fig. 4 shows a schematic diagram of a battery management system according to one embodiment of the present disclosure.
Fig. 5 shows a schematic diagram of a battery management system according to one embodiment of the present disclosure.
Detailed Description
The present disclosure is described in further detail below with reference to the drawings and the embodiments. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant content and not limiting of the present disclosure. It should be further noted that, for convenience of description, only a portion relevant to the present disclosure is shown in the drawings.
In addition, embodiments of the present disclosure and features of the embodiments may be combined with each other without conflict. The technical aspects of the present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Unless otherwise indicated, the exemplary implementations/embodiments shown are to be understood as providing exemplary features of various details of some ways in which the technical concepts of the present disclosure may be practiced. Thus, unless otherwise indicated, features of the various implementations/embodiments may be additionally combined, separated, interchanged, and/or rearranged without departing from the technical concepts of the present disclosure.
The use of cross-hatching and/or shading in the drawings is typically used to clarify the boundaries between adjacent components. As such, the presence or absence of cross-hatching or shading does not convey or represent any preference or requirement for a particular material, material property, dimension, proportion, commonality between illustrated components, and/or any other characteristic, attribute, property, etc. of a component, unless indicated. In addition, in the drawings, the size and relative sizes of elements may be exaggerated for clarity and/or descriptive purposes. While the exemplary embodiments may be variously implemented, the specific process sequences may be performed in a different order than that described. For example, two consecutively described processes may be performed substantially simultaneously or in reverse order from that described. Moreover, like reference numerals designate like parts.
When an element is referred to as being "on" or "over", "connected to" or "coupled to" another element, it can be directly on, connected or coupled to the other element or intervening elements may be present. However, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element, there are no intervening elements present. For this reason, the term "connected" may refer to physical connections, electrical connections, and the like, with or without intermediate components.
For descriptive purposes, the present disclosure may use spatially relative terms such as "under … …," under … …, "" under … …, "" lower, "" above … …, "" upper, "" above … …, "" upper "and" side (e.g., as in "sidewall") to describe one component's relationship to another (other) component as illustrated in the figures. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use, operation, and/or manufacture. For example, if the device in the figures is turned over, elements described as "under" or "beneath" other elements or features would then be oriented "over" the other elements or features. Thus, the exemplary term "below … …" may encompass both an orientation of "above" and "below". Furthermore, the device may be otherwise positioned (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, when the terms "comprises" and/or "comprising," and variations thereof, are used in the present specification, the presence of stated features, integers, steps, operations, elements, components, and/or groups thereof is described, but the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof is not precluded. It is also noted that, as used herein, the terms "substantially," "about," and other similar terms are used as approximation terms and not as degree terms, and as such, are used to explain the inherent deviations of measured, calculated, and/or provided values that would be recognized by one of ordinary skill in the art.
According to one embodiment of the present disclosure, there is provided an equalization chip of a series battery pack including N series-connected batteries, where N > 1, the equalization chip including: the first end of the ith control switch of the i control switches is connected with the positive electrode end of the ith battery through an equalizing resistor, and the second end of the ith control switch is connected with the positive electrode end of the i-1 th battery; and i first resistors, a first end of an i first resistor of the i first resistors being connected to a second end of an i control switch, and a second end of the i first resistor being connected to a control end of the i control switch, the i control switch being controlled to: when the current flowing from the positive terminal of the ith battery to the positive terminal of the ith-1 th battery is greater than the current threshold, the ith control switch is turned on based on the voltage generated by the ith first resistor, so that the current flows through the ith control switch to perform current balancing on the ith battery, wherein 1 < i.ltoreq.N.
The i control switches are NMOS transistors, the first ends of the i control switches are drain electrodes, the second ends of the i control switches are source electrodes, and the control ends of the i control switches are grid electrodes; or the i control switches are triodes, the first ends of the i control switches are collectors, the second ends of the i control switches are emitters, and the control ends of the i control switches are bases.
The circuit further comprises i second resistors, wherein the first end of the ith second resistor of the i second resistors is connected with the control end of the ith control switch, and the second end of the ith second resistor is connected with the second end of the ith first resistor.
The device further comprises i first diodes, wherein the anode of the ith first diode of the i first diodes is connected to the first end of the ith control switch, and the cathode of the ith first diode is grounded.
The device further comprises i second diodes, wherein the anode of the ith second diode of the i second diodes is connected with the second end of the control switch, and the cathode of the ith second diode is connected with the control end of the control switch.
The device further comprises i third diodes, wherein the anode of the ith second triode of the i second triodes is connected with the second end of the (i+1) th first resistor, and the cathode of the ith second triode is connected with the second end of the ith first resistor.
The current flowing from the positive terminal of the i-th battery to the positive terminal of the i-1 th battery is controlled by the on and off of the i-th first switch of the i-th first switches, and when the i-th first switch is on, the current flows from the positive terminal of the i-th battery to the positive terminal of the i-1 th battery.
I first switches are integrated in the equalization chip.
The circuit further comprises i current control circuits, wherein the first end of the ith current control circuit of the i current control circuits is connected with the second end of the (i+1) th first resistor, and the second end of the ith current control circuit is connected with the second end of the (i) th first resistor.
The current generated by each of the i current control circuits is controlled based on the voltage of the positive terminal of the nth battery and the voltage of the positive terminal of the i-1 th battery.
When the equalization control is required for the ith battery, the ith current control circuit operates.
The i current control circuits respectively comprise a mirror circuit and a current source, wherein the current source generates current based on the voltage of the positive terminal of the Nth battery, and generates current flowing into the second terminal of the i first resistor through the mirror current.
The current generated by each of the i current control circuits is controlled based on the voltage of the positive terminal of the i-th battery and the voltage of the positive terminal of the i-1 th battery.
When the equalization control is required for the ith battery, the ith current control circuit operates.
The i current control circuits respectively comprise a mirror circuit and a current source, wherein the current source generates current based on the voltage of the positive terminal of the i-th battery, and generates current flowing into the second terminal of the i-th first resistor through the mirror current.
The technical scheme of the present disclosure will be described below with reference to the accompanying drawings.
< First embodiment >
Fig. 1 shows an equalization chip according to a first embodiment of the present disclosure. The series battery pack 100 includes N series-connected batteries 101, 102, … …, 10N.
The equalization chip 200 includes: the first end of the i control switch 211, 212 and … … n is connected with the positive electrode end of the i battery through equalizing resistors 401, 402, … … and 40n, and the second end of the i control switch is connected with the positive electrode end of the i-1 battery; and i first resistors 231, 232, … …, 23n, a first end of an i first resistor of the i first resistors being connected to a second end of an i control switch, and the second end of the i first resistor being connected to a control end of the i control switch, the i control switch being controlled to: when the current flowing from the positive terminal of the ith battery to the positive terminal of the ith-1 th battery is greater than the current threshold, the ith control switch is turned on based on the voltage generated by the ith first resistor, so that the current flows through the ith control switch to perform current balancing on the ith battery, wherein 1 < i.ltoreq.N.
The i control switches are NMOS transistors, the first ends of the i control switches are drain electrodes, the second ends of the i control switches are source electrodes, and the control ends of the i control switches are grid electrodes; or the i control switches are triodes, the first ends of the i control switches are collectors, the second ends of the i control switches are emitters, and the control ends of the i control switches are bases.
The following will take the content of the 2 nd battery as an example and set the control switch as an NMOS transistor.
The drain of the NMOS transistor 212 is connected to the positive terminal of the 2 nd battery through the equalizing resistor 402 via a pin, and the source of the NMOS transistor 212 is connected to the positive terminal of the 1 st battery via a pin. The gate of the NMOS transistor 212 is connected to the second resistor 222, and a first resistor 232 is connected between the source of the NMOS transistor 212 and the second resistor 222. In this way, when the battery is unbalanced, a current will be formed from the positive terminal of the battery 102 through the resistor 23n and the resistor 232, the voltage formed by the resistor 222 and the resistor 232 forms the gate-source voltage of the NMOS transistor 212, and when the gate-source voltage is greater than the threshold on voltage, the NMOS transistor 212 will be turned on, and at this time, an equalizing current will flow from the resistor 402 through the NMOS transistor 212, so as to perform equalization on the battery 102. When no current flows, the gate-source voltage of the NMOS transistor 212 is zero, and the NMOS transistor 212 is turned off, and at this time, the equalization control will not be performed.
In addition, the anode of the i first diode of the i first diodes 251, 252, … …, 25n is connected to the first end of the i control switch, and the cathode of the i first diode is grounded. For example, the anode of diode 252 is connected to the drain of control switch 212 and the cathode is grounded for protecting the drain of control switch 212.
The device further comprises i second diodes 241, 242 and … … n, wherein the anode of the i second diode of the i second diodes is connected with the second end of the control switch, and the cathode of the i second diode is connected with the control end of the control switch. For example, the anode of diode 242 is connected to the gate of transistor 212 and the cathode is connected to the source of transistor 212 for protecting the gate oxide of transistor 212.
The circuit further comprises i third diodes 261, 262, … … and 26n, wherein the anode of the ith second triode of the i second triodes is connected with the second end of the (i+1) th first resistor, and the cathode of the ith second triode is connected with the second end of the ith first resistor. For example, diode 262 is connected between resistors 232 and 23n for protecting transistor 212.
The equalization chip 200 is connected to the BMS chip 300 via pins, and the voltage of each battery or the like can be measured by the BMS chip 300, for example.
< Second embodiment >
Fig. 2 shows an equalization chip according to a second embodiment of the present disclosure. The series battery pack 100 includes N series-connected batteries 101, 102, … …, 10N.
The equalization chip 200 includes: the first end of the i control switch 211, 212 and … … n is connected with the positive electrode end of the i battery through equalizing resistors 401, 402, … … and 40n, and the second end of the i control switch is connected with the positive electrode end of the i-1 battery; and i first resistors 231, 232, … …, 23n, a first end of an i first resistor of the i first resistors being connected to a second end of an i control switch, and the second end of the i first resistor being connected to a control end of the i control switch, the i control switch being controlled to: when the current flowing from the positive terminal of the ith battery to the positive terminal of the ith-1 th battery is greater than the current threshold, the ith control switch is turned on based on the voltage generated by the ith first resistor, so that the current flows through the ith control switch to perform current balancing on the ith battery, wherein 1 < i.ltoreq.N.
The i control switches are NMOS transistors, the first ends of the i control switches are drain electrodes, the second ends of the i control switches are source electrodes, and the control ends of the i control switches are grid electrodes; or the i control switches are triodes, the first ends of the i control switches are collectors, the second ends of the i control switches are emitters, and the control ends of the i control switches are bases.
The following will take the content of the 2 nd battery as an example and set the control switch as an NMOS transistor.
The drain of the NMOS transistor 212 is connected to the positive terminal of the 2 nd battery through the equalizing resistor 402 via a pin, and the source of the NMOS transistor 212 is connected to the positive terminal of the 1 st battery via a pin. The gate of the NMOS transistor 212 is connected to the second resistor 222, and a first resistor 232 is connected between the source of the NMOS transistor 212 and the second resistor 222. In this way, when the battery is unbalanced, a current will be formed from the positive terminal of the battery 102 through the resistor 23n and the resistor 232, the voltage formed by the resistor 222 and the resistor 232 forms the gate-source voltage of the NMOS transistor 212, and when the gate-source voltage is greater than the threshold on voltage, the NMOS transistor 212 will be turned on, and at this time, an equalizing current will flow from the resistor 402 through the NMOS transistor 212, so as to perform equalization on the battery 102. When no current flows, the gate-source voltage of the NMOS transistor 212 is zero, and the NMOS transistor 212 is turned off, and at this time, the equalization control will not be performed.
In addition, the anode of the i first diode of the i first diodes 251, 252, … …, 25n is connected to the first end of the i control switch, and the cathode of the i first diode is grounded. For example, the anode of diode 252 is connected to the drain of control switch 212 and the cathode is grounded for protecting the drain of control switch 212.
The device further comprises i second diodes 241, 242 and … … n, wherein the anode of the i second diode of the i second diodes is connected with the second end of the control switch, and the cathode of the i second diode is connected with the control end of the control switch. For example, the anode of diode 242 is connected to the gate of transistor 212 and the cathode is connected to the source of transistor 212 for protecting the gate oxide of transistor 212.
The circuit further comprises i third diodes 261, 262, … … and 26n, wherein the anode of the ith second triode of the i second triodes is connected with the second end of the (i+1) th first resistor, and the cathode of the ith second triode is connected with the second end of the ith first resistor. For example, diode 262 is connected between resistors 232 and 23n for protecting transistor 212.
The second embodiment differs from the first embodiment mainly in that N first switches 311, 312, … …, 31N are added in the second embodiment.
The current flowing from the positive terminal of the i-th battery to the positive terminal of the i-1 th battery is controlled by the on and off of the i-th first switch of the i-th first switches, and when the i-th first switch is on, the current flows from the positive terminal of the i-th battery to the positive terminal of the i-1 th battery.
For example, when equalizing the 2 nd battery 102, the switch 312 is turned on, thereby forming a current, and the transistor 212 is turned on to perform equalization.
As shown in fig. 2, the first switches 311, 312, … …, 31n may be integrated in the BMS chip 300.
The equalization chip 200 is connected to the BMS chip 300 via pins, and the voltage of each battery or the like can be measured by the BMS chip 300, for example.
< Third embodiment >
Fig. 3 shows an equalization chip according to a third embodiment of the present disclosure. The series battery pack 100 includes N series-connected batteries 101, 102, … …, 10N.
The equalization chip 200 includes: the first end of the i control switch 211, 212 and … … n is connected with the positive electrode end of the i battery through equalizing resistors 401, 402, … … and 40n, and the second end of the i control switch is connected with the positive electrode end of the i-1 battery; and i first resistors 231, 232, … …, 23n, a first end of an i first resistor of the i first resistors being connected to a second end of an i control switch, and the second end of the i first resistor being connected to a control end of the i control switch, the i control switch being controlled to: when the current flowing from the positive terminal of the ith battery to the positive terminal of the ith-1 th battery is greater than the current threshold, the ith control switch is turned on based on the voltage generated by the ith first resistor, so that the current flows through the ith control switch to perform current balancing on the ith battery, wherein 1 < i.ltoreq.N.
The i control switches are NMOS transistors, the first ends of the i control switches are drain electrodes, the second ends of the i control switches are source electrodes, and the control ends of the i control switches are grid electrodes; or the i control switches are triodes, the first ends of the i control switches are collectors, the second ends of the i control switches are emitters, and the control ends of the i control switches are bases.
The following will take the content of the 2 nd battery as an example and set the control switch as an NMOS transistor.
The drain of the NMOS transistor 212 is connected to the positive terminal of the 2 nd battery through the equalizing resistor 402 via a pin, and the source of the NMOS transistor 212 is connected to the positive terminal of the 1 st battery via a pin. The gate of the NMOS transistor 212 is connected to the second resistor 222, and a first resistor 232 is connected between the source of the NMOS transistor 212 and the second resistor 222. In this way, when the battery is unbalanced, a current will be formed from the positive terminal of the battery 102 through the resistor 23n and the resistor 232, the voltage formed by the resistor 222 and the resistor 232 forms the gate-source voltage of the NMOS transistor 212, and when the gate-source voltage is greater than the threshold on voltage, the NMOS transistor 212 will be turned on, and at this time, an equalizing current will flow from the resistor 402 through the NMOS transistor 212, so as to perform equalization on the battery 102. When no current flows, the gate-source voltage of the NMOS transistor 212 is zero, and the NMOS transistor 212 is turned off, and at this time, the equalization control will not be performed.
In addition, the anode of the i first diode of the i first diodes 251, 252, … …, 25n is connected to the first end of the i control switch, and the cathode of the i first diode is grounded. For example, the anode of diode 252 is connected to the drain of control switch 212 and the cathode is grounded for protecting the drain of control switch 212.
The device further comprises i second diodes 241, 242 and … … n, wherein the anode of the i second diode of the i second diodes is connected with the second end of the control switch, and the cathode of the i second diode is connected with the control end of the control switch. For example, the anode of diode 242 is connected to the gate of transistor 212 and the cathode is connected to the source of transistor 212 for protecting the gate oxide of transistor 212.
The circuit further comprises i third diodes 261, 262, … … and 26n, wherein the anode of the ith second triode of the i second triodes is connected with the second end of the (i+1) th first resistor, and the cathode of the ith second triode is connected with the second end of the ith first resistor. For example, diode 262 is connected between resistors 232 and 23n for protecting transistor 212.
The third embodiment differs from the second embodiment mainly in that N first switches 311, 312, … …, 31N are integrated in the equalization chip 200.
The current flowing from the positive terminal of the i-th battery to the positive terminal of the i-1 th battery is controlled by the on and off of the i-th first switch of the i-th first switches, and when the i-th first switch is on, the current flows from the positive terminal of the i-th battery to the positive terminal of the i-1 th battery.
For example, when equalizing the 2 nd battery 102, the switch 312 is turned on, thereby forming a current, and the transistor 212 is turned on to perform equalization.
The equalization chip 200 is connected to the BMS chip 300 via pins, and the voltage of each battery or the like can be measured by the BMS chip 300, for example.
< Fourth embodiment >
Fig. 4 shows an equalization chip according to a fourth embodiment of the present disclosure. The series battery pack 100 includes N series-connected batteries 101, 102, … …, 10N.
The equalization chip 200 includes: the first end of the i control switch 211, 212 and … … n is connected with the positive electrode end of the i battery through equalizing resistors 401, 402, … … and 40n, and the second end of the i control switch is connected with the positive electrode end of the i-1 battery; and i first resistors 231, 232, … …, 23n, a first end of an i first resistor of the i first resistors being connected to a second end of an i control switch, and the second end of the i first resistor being connected to a control end of the i control switch, the i control switch being controlled to: when the current flowing from the positive terminal of the ith battery to the positive terminal of the ith-1 th battery is greater than the current threshold, the ith control switch is turned on based on the voltage generated by the ith first resistor, so that the current flows through the ith control switch to perform current balancing on the ith battery, wherein 1 < i.ltoreq.N.
The i control switches are NMOS transistors, the first ends of the i control switches are drain electrodes, the second ends of the i control switches are source electrodes, and the control ends of the i control switches are grid electrodes; or the i control switches are triodes, the first ends of the i control switches are collectors, the second ends of the i control switches are emitters, and the control ends of the i control switches are bases.
The following will take the content of the 2 nd battery as an example and set the control switch as an NMOS transistor.
The drain of the NMOS transistor 212 is connected to the positive terminal of the 2 nd battery through the equalizing resistor 402 via a pin, and the source of the NMOS transistor 212 is connected to the positive terminal of the 1 st battery via a pin. The gate of the NMOS transistor 212 is connected to the second resistor 222, and a first resistor 232 is connected between the source of the NMOS transistor 212 and the second resistor 222. In this way, when the battery is unbalanced, a current will be formed from the positive terminal of the battery 102 through the resistor 23n and the resistor 232, the voltage formed by the resistor 222 and the resistor 232 forms the gate-source voltage of the NMOS transistor 212, and when the gate-source voltage is greater than the threshold on voltage, the NMOS transistor 212 will be turned on, and at this time, an equalizing current will flow from the resistor 402 through the NMOS transistor 212, so as to perform equalization on the battery 102. When no current flows, the gate-source voltage of the NMOS transistor 212 is zero, and the NMOS transistor 212 is turned off, and at this time, the equalization control will not be performed.
In addition, the anode of the i first diode of the i first diodes 251, 252, … …, 25n is connected to the first end of the i control switch, and the cathode of the i first diode is grounded. For example, the anode of diode 252 is connected to the drain of control switch 212 and the cathode is grounded for protecting the drain of control switch 212.
The device further comprises i second diodes 241, 242 and … … n, wherein the anode of the i second diode of the i second diodes is connected with the second end of the control switch, and the cathode of the i second diode is connected with the control end of the control switch. For example, the anode of diode 242 is connected to the gate of transistor 212 and the cathode is connected to the source of transistor 212 for protecting the gate oxide of transistor 212.
As shown in fig. 4, the circuit further includes i current control circuits, wherein a first end of an i current control circuit of the i current control circuits is connected to a second end of the i+1th first resistor, and a second end of the i current control circuit is connected to a second end of the i first resistor. The current generated by each of the i current control circuits is controlled based on the voltage of the positive terminal of the nth battery and the voltage of the positive terminal of the i-1 th battery. When the equalization control is required for the ith battery, the ith current control circuit operates.
The i current control circuits include a mirror circuit and current sources 2831, 2832, … …, 283N, respectively, which generate a current based on the voltage of the positive terminal of the nth battery and generate a current flowing into the second terminal of the ith first resistor via the mirror current. The mirror circuit may include NMOS transistors 2811 and 2821, 2812 and 2822, … …, 281n, and 282n. The current sources are all connected to the highest voltage of the nth battery.
In addition, when i current control circuits are required to operate, the operation can be realized by the conduction of the switches 2841, 2842, … … and 284 n.
For example, the battery 2 is exemplified as the battery 102. Switch 2842 is turned on and current source 2832 generates a first current based on the highest voltage, which likewise generates a first current on the source side of transistor 2812, which will cause transistor 212 to be turned on, thereby equalizing battery 2.
The equalization chip 200 is connected to the BMS chip 300 via pins, and the voltage of each battery or the like can be measured by the BMS chip 300, for example.
< Fifth embodiment >
Fig. 5 shows an equalization chip according to a fifth embodiment of the present disclosure. The series battery pack 100 includes N series-connected batteries 101, 102, … …, 10N.
The equalization chip 200 includes: the first end of the i control switch 211, 212 and … … n is connected with the positive electrode end of the i battery through equalizing resistors 401, 402, … … and 40n, and the second end of the i control switch is connected with the positive electrode end of the i-1 battery; and i first resistors 231, 232, … …, 23n, a first end of an i first resistor of the i first resistors being connected to a second end of an i control switch, and the second end of the i first resistor being connected to a control end of the i control switch, the i control switch being controlled to: when the current flowing from the positive terminal of the ith battery to the positive terminal of the ith-1 th battery is greater than the current threshold, the ith control switch is turned on based on the voltage generated by the ith first resistor, so that the current flows through the ith control switch to perform current balancing on the ith battery, wherein 1 < i.ltoreq.N.
The i control switches are NMOS transistors, the first ends of the i control switches are drain electrodes, the second ends of the i control switches are source electrodes, and the control ends of the i control switches are grid electrodes; or the i control switches are triodes, the first ends of the i control switches are collectors, the second ends of the i control switches are emitters, and the control ends of the i control switches are bases.
The following will take the content of the 2 nd battery as an example and set the control switch as an NMOS transistor.
The drain of the NMOS transistor 212 is connected to the positive terminal of the 2 nd battery through the equalizing resistor 402 via a pin, and the source of the NMOS transistor 212 is connected to the positive terminal of the 1 st battery via a pin. The gate of the NMOS transistor 212 is connected to the second resistor 222, and a first resistor 232 is connected between the source of the NMOS transistor 212 and the second resistor 222. In this way, when the battery is unbalanced, a current will be formed from the positive terminal of the battery 102 through the resistor 23n and the resistor 232, the voltage formed by the resistor 222 and the resistor 232 forms the gate-source voltage of the NMOS transistor 212, and when the gate-source voltage is greater than the threshold on voltage, the NMOS transistor 212 will be turned on, and at this time, an equalizing current will flow from the resistor 402 through the NMOS transistor 212, so as to perform equalization on the battery 102. When no current flows, the gate-source voltage of the NMOS transistor 212 is zero, and the NMOS transistor 212 is turned off, and at this time, the equalization control will not be performed.
In addition, the anode of the i first diode of the i first diodes 251, 252, … …, 25n is connected to the first end of the i control switch, and the cathode of the i first diode is grounded. For example, the anode of diode 252 is connected to the drain of control switch 212 and the cathode is grounded for protecting the drain of control switch 212.
The device further comprises i second diodes 241, 242 and … … n, wherein the anode of the i second diode of the i second diodes is connected with the second end of the control switch, and the cathode of the i second diode is connected with the control end of the control switch. For example, the anode of diode 242 is connected to the gate of transistor 212 and the cathode is connected to the source of transistor 212 for protecting the gate oxide of transistor 212.
As shown in fig. 5, the circuit further includes i current control circuits, wherein a first end of an i current control circuit of the i current control circuits is connected to a second end of the i+1th first resistor, and a second end of the i current control circuit is connected to a second end of the i first resistor. The current generated by each of the i current control circuits is controlled based on the voltage of the positive terminal of the i-th battery and the voltage of the positive terminal of the i-1 th battery. When the equalization control is required for the ith battery, the ith current control circuit operates.
The i current control circuits include a mirror circuit and current sources 2831, 2832, … …, 283n, respectively, which generate currents based on the voltage of the positive terminal of the i-th battery and the voltage of the positive terminal of the i-1-th battery, and generate currents flowing into the second terminal of the i-th first resistor via the mirror currents. The mirror circuit may include NMOS transistors 2811 and 2821, 2812 and 2822, … …, 281n, and 282n.
In addition, when i current control circuits are required to operate, the operation can be realized by the conduction of the switches 2841, 2842, … … and 284 n.
For example, the battery 2 is exemplified as the battery 102. Switch 2842 is turned on and current source 2832 generates a first current based on the positive voltage of battery 2, and the same first current is generated on the source side of transistor 2812, which will cause transistor 212 to be turned on, thereby equalizing battery 2.
This embodiment differs from the embodiment shown in fig. 4 in that each current source for the ith battery is based on the positive terminal voltage of the ith battery itself, thus avoiding the influence of the battery imbalance factor caused by using the highest voltage. Because the highest voltage is the total voltage of each cell, it tends to contain cell imbalance information.
The equalization chip 200 is connected to the BMS chip 300 via pins, and the voltage of each battery or the like can be measured by the BMS chip 300, for example.
In the present disclosure, the equalization control is realized by using the voltages of the positive terminals of the adjacent two batteries, so that a better equalization effect can be obtained, and the current of the other batteries can be not interfered. In the present disclosure, miniaturization and integration can be achieved by integrating the equalization circuit into the semiconductor chip.
In the description of the present specification, reference to the terms "one embodiment/manner," "some embodiments/manner," "example," "a particular example," "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment/manner or example is included in at least one embodiment/manner or example of the application. In this specification, the schematic representations of the above terms are not necessarily for the same embodiment/manner or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments/modes or examples. Furthermore, the various embodiments/modes or examples described in this specification and the features of the various embodiments/modes or examples can be combined and combined by persons skilled in the art without contradiction.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
It will be appreciated by those skilled in the art that the above-described embodiments are merely for clarity of illustration of the disclosure, and are not intended to limit the scope of the disclosure. Other variations or modifications will be apparent to persons skilled in the art from the foregoing disclosure, and such variations or modifications are intended to be within the scope of the present disclosure.
Claims (7)
1. An equalization chip for a series battery pack comprising N series batteries, where N > 1, the equalization chip comprising:
the first end of the ith control switch is connected with the positive electrode end of the ith battery through an equalizing resistor, and the second end of the ith control switch is connected with the positive electrode end of the (i-1) th battery; and
I first resistors, a first end of the i first resistor being connected to a second end of the i control switch, and a second end of the i first resistor being connected to a control end of the i control switch,
The ith control switch is controlled to: when the current flowing from the positive terminal of the ith battery to the positive terminal of the (i-1) th battery is greater than a current threshold, the (i) th control switch is turned on based on the voltage generated by the (i) th first resistor, so that a current flows through the (i) th control switch to perform current balancing on the (i) th battery, wherein 1 < i.ltoreq.N,
The i control switches are NMOS transistors, the first ends of the i control switches are drain electrodes, the second ends of the i control switches are source electrodes, and the control ends of the i control switches are grid electrodes; or the i control switches are triodes, the first ends of the i control switches are collectors, the second ends of the i control switches are emitters, the control ends of the i control switches are bases,
The equalizing chip also comprises i second resistors, the first end of the i second resistor is connected with the control end of the i control switch, the second end of the i second resistor is connected with the second end of the i first resistor,
The equalization chip further comprises i first diodes, the anode of the i first diodes is connected to the first end of the i control switch, the cathode of the i first diodes is grounded,
The equalization chip also comprises i second diodes, the anode of the i second diode is connected with the second end of the control switch, the cathode of the i second diode is connected with the control end of the control switch,
The equalizing chip also comprises i third diodes, the anode of the i third diode is connected with the second end of the (i+1) th first resistor, the cathode of the i third diode is connected with the second end of the (i) th first resistor,
The current flowing from the positive terminal of the ith battery to the positive terminal of the ith-1 th battery is controlled by the on and off of the ith first switch, and when the ith first switch is on, the current flows from the positive terminal of the ith battery to the positive terminal of the ith-1 th battery.
2. The equalization chip of claim 1, wherein the i first switches are integrated in the equalization chip.
3. The equalization chip of claim 1, further comprising i current control circuits, a first terminal of the i current control circuits being coupled to a second terminal of the i+1 first resistors, a second terminal of the i current control circuits being coupled to a second terminal of the i first resistors.
4. The equalization chip of claim 3, wherein the current generated by each of the i current control circuits is controlled based on the voltage at the positive terminal of the i-th cell and the voltage at the positive terminal of the i-1 th cell.
5. The equalization chip of claim 4, wherein the ith current control circuit is operated when equalization control of the ith battery is required.
6. The equalization chip of claim 5, wherein the i current control circuits each comprise a mirror circuit and a current source that generates a current based on a voltage at a positive terminal of the i-th battery and generates a current flowing into a second terminal of the i-th first resistor via the mirror current.
7. A battery management system, comprising:
the equalization chip of any one of claims 1 to 6; and
And a battery management chip that measures the voltage of the i-th battery at least via the equalization chip.
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