CN112749113A - Data interaction method, system, device and medium - Google Patents
Data interaction method, system, device and medium Download PDFInfo
- Publication number
- CN112749113A CN112749113A CN202110057604.XA CN202110057604A CN112749113A CN 112749113 A CN112749113 A CN 112749113A CN 202110057604 A CN202110057604 A CN 202110057604A CN 112749113 A CN112749113 A CN 112749113A
- Authority
- CN
- China
- Prior art keywords
- data
- memory access
- direct memory
- equipment
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000000034 method Methods 0.000 title claims abstract description 40
- 230000003993 interaction Effects 0.000 title claims abstract description 28
- 230000005540 biological transmission Effects 0.000 claims abstract description 73
- 230000004044 response Effects 0.000 claims description 15
- 238000004590 computer program Methods 0.000 claims description 7
- 238000004806 packaging method and process Methods 0.000 claims description 3
- 238000005516 engineering process Methods 0.000 abstract description 4
- 230000009467 reduction Effects 0.000 abstract description 4
- 230000007704 transition Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000012546 transfer Methods 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/32—Handling requests for interconnection or transfer for access to input/output bus using combination of interrupt and burst mode transfer
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
Abstract
The invention discloses a method, a system, equipment and a storage medium for data interaction, wherein the method comprises the following steps: setting an FPGA between the control equipment and the controlled equipment, and judging whether the control equipment has data to be transmitted to the corresponding controlled equipment; responding to the data of the control equipment to be transmitted to the corresponding controlled equipment, and sending a direct memory access transmission request to the FPGA; responding to the FPGA receiving the direct memory access transmission request, transmitting corresponding data to corresponding controlled equipment and analyzing a chip selection signal and a read/write enabling signal of the direct memory access transmission request; and determining an operation instruction according to the read/write enable signal, and sending the operation instruction to the corresponding controlled equipment according to the chip selection signal. The invention solves the problem of performance reduction of the equipment caused by the low-speed equipment by introducing the set FPGA module as the transition of the PCIe bus and the low-speed equipment and combining the FPGA and the PCIe technology.
Description
Technical Field
The present invention relates to the field of data transmission, and more particularly, to a method, a system, a computer device, and a readable medium for data interaction.
Background
PCIe (Peripheral Component Interface Express, bus and Interface standard) has the characteristics of high bandwidth, low latency, simple PCB (Printed circuit board) wiring, and the like, and is a mainstream bus Interface inside the existing instrument. However, the PCIe protocol is complex, a Switch chip is required for connecting more devices, and if a PCIe bus is directly used by a plurality of devices in the whole machine, not only is the Interface circuit of each device complex, but also PCIe bus resources are wasted, but if a low-speed bus such as a conventional SPI (Serial Peripheral Interface) is used, the data transmission speed of the device is seriously affected.
Disclosure of Invention
In view of this, embodiments of the present invention provide a method, a system, a computer device, and a computer readable storage medium for data interaction, in which a set FPGA module is introduced as a transition between a PCIe bus and a low-speed device, and the FPGA and the PCIe technology are combined to solve the problem of device performance degradation caused by the low-speed device.
Based on the above object, an aspect of the embodiments of the present invention provides a method for data interaction, including the following steps: setting an FPGA between control equipment and controlled equipment, and judging whether the control equipment has data to be transmitted to the corresponding controlled equipment; responding to the data which are required to be transmitted to the corresponding controlled equipment in the control equipment, and sending a direct memory access transmission request to the FPGA; responding to the FPGA receiving the direct memory access transmission request, transmitting corresponding data to corresponding controlled equipment, and analyzing a chip selection signal and a read/write enabling signal of the direct memory access transmission request; and determining an operation instruction according to the read/write enabling signal, and sending the operation instruction to corresponding controlled equipment according to the chip selection signal.
In some embodiments, the transmitting the corresponding data to the corresponding controlled device and resolving the chip select signal and the read/write enable signal of the direct memory access transmission request includes: judging whether the difference between a read address pointer and a write address pointer of the direct memory access buffer area is one or not; and in response to the difference between the read address pointer and the write address pointer of the direct memory access buffer area being not one, sequentially encapsulating the direct memory access data streams and transmitting the encapsulated data packets through a bus.
In some embodiments, the transmitting the corresponding data to the corresponding controlled device and resolving the chip select signal and the read/write enable signal of the direct memory access transmission request includes: judging whether the data stream is transmitted according to the data stream end identification bit; and adding one to the write pointer of the direct memory access buffer in response to completion of the data stream transmission, and encapsulating and sending the current address pointer to a device driver.
In some embodiments, the method further comprises: and responding to the completion of the data stream transmission, generating an interrupt signal, and acquiring a direct memory access read address pointer by analyzing the received data packet.
In another aspect of the embodiments of the present invention, a data interaction system is further provided, including: the device comprises a setting module, a data transmission module and a data transmission module, wherein the setting module is configured to set an FPGA between control equipment and controlled equipment and judge whether the control equipment has data to be transmitted to the corresponding controlled equipment; the sending module is configured to respond to the fact that the control equipment has data to be transmitted to corresponding controlled equipment, and send a direct memory access transmission request to the FPGA; the transmission module is configured to respond to the FPGA receiving the direct memory access transmission request, transmit corresponding data to corresponding controlled equipment and analyze a chip selection signal and a read/write enabling signal of the direct memory access transmission request; and the execution module is configured to determine an operation instruction according to the read/write enable signal and send the operation instruction to the corresponding controlled device according to the chip selection signal.
In some embodiments, the transmission module is configured to: judging whether the difference between a read address pointer and a write address pointer of the direct memory access buffer area is one or not; and in response to the difference between the read address pointer and the write address pointer of the direct memory access buffer area being not one, sequentially encapsulating the direct memory access data streams and transmitting the encapsulated data packets through a bus.
In some embodiments, the transmission module is configured to: judging whether the data stream is transmitted according to the data stream end identification bit; and adding one to the write pointer of the direct memory access buffer in response to completion of the data stream transmission, and encapsulating and sending the current address pointer to a device driver.
In some embodiments, the system further comprises: and the interrupt module is configured to generate an interrupt signal in response to completion of the data stream transmission, and acquire a direct memory access read address pointer by analyzing the received data packet.
In another aspect of the embodiments of the present invention, there is also provided a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method as above.
In a further aspect of the embodiments of the present invention, a computer-readable storage medium is also provided, in which a computer program for implementing the above method steps is stored when the computer program is executed by a processor.
The invention has the following beneficial technical effects: the set FPGA module is introduced to serve as the transition of a PCIe bus and low-speed equipment, and the FPGA and PCIe technology are combined to solve the problem of performance reduction of the equipment caused by the low-speed equipment.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
FIG. 1 is a schematic diagram of an embodiment of a method of data interaction provided by the present invention;
FIG. 2 is a flow chart of data transmission in a PCIe bus module in an embodiment of the invention;
FIG. 3 is a flowchart illustrating operation of a local bus control module according to an embodiment of the present invention;
FIG. 4 is a schematic hardware structure diagram of an embodiment of a computer device for data interaction provided by the present invention;
FIG. 5 is a schematic diagram of an embodiment of a computer storage medium for data interaction provided by the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
In view of the above object, a first aspect of the embodiments of the present invention provides an embodiment of a method for data interaction. Fig. 1 is a schematic diagram illustrating an embodiment of a method for data interaction provided by the present invention. As shown in fig. 1, the embodiment of the present invention includes the following steps:
s1, setting a Field-Programmable Gate Array (FPGA) between the control device and the controlled device, and judging whether the control device has data to be transmitted to the corresponding controlled device;
s2, responding to the data of the control equipment needing to be transmitted to the corresponding controlled equipment, and sending a direct memory access transmission request to the FPGA;
s3, responding to the direct memory access transmission request received by the FPGA, transmitting corresponding data to corresponding controlled equipment and analyzing a chip selection signal and a read/write enabling signal of the direct memory access transmission request; and
and S4, determining an operation instruction according to the read/write enabling signal, and sending the operation instruction to the corresponding controlled equipment according to the chip selection signal.
According to the embodiment of the invention, the FPGA bridge is arranged between the PCIe bus port and the low-speed equipment, so that the problem of instrument performance reduction caused by the low-speed equipment is solved. The FPGA bridge consists of a PCIe bus control module and a local bus control module, wherein the PCIe bus control module is used for data interaction between the CPU and the FPGA; the local bus control module is used for realizing the analysis of the CPU command, controlling the state of the low-speed equipment and finishing the data interaction between the CPU and the low-speed equipment. Through the coordination of the FPGA bridge, the bandwidth of the internal bus can be improved.
The FPGA is a high-speed device directly connected with the PCIe bus; on the other hand, a large number of low-speed devices are connected under PCIe devices implemented by FPGAs. In the new hardware architecture, the CPU regards the FPGA as a common high-speed local device, operates the FPGA in a high-speed time sequence, manages a plurality of low-speed devices simultaneously, and analyzes an operation command sent by the CPU to the low-speed devices. The FPGA can realize real-time conversion between the CPU high-speed time sequence and the low-speed equipment time sequence, and essentially, the FPGA is a time sequence converter.
And arranging an FPGA between the control equipment and the controlled equipment, and judging whether the control equipment has data to be transmitted to the corresponding controlled equipment. And responding to the data which is required to be transmitted to the corresponding controlled equipment in the control equipment, and sending a direct memory access transmission request to the FPGA. In the embodiment of the invention, the control equipment is a CPU, and the controlled equipment is low-speed equipment. When data needs to be transmitted, the application program initiates a DMA (Direct Memory Access) transmission request to the PCIe interface module.
And responding to the FPGA receiving the direct memory access transmission request, transmitting corresponding data and analyzing a chip selection signal and a read/write enable signal of the direct memory access transmission request.
In some embodiments, the transmitting the corresponding data to the corresponding controlled device and resolving the chip select signal and the read/write enable signal of the direct memory access transmission request includes: judging whether the data stream is transmitted according to the data stream end identification bit; and adding one to the write pointer of the direct memory access buffer in response to completion of the data stream transmission, and encapsulating and sending the current address pointer to a device driver. And the interface module encapsulates the DMA data stream according to the TLP byte sequence, the encapsulated data packet is sent out through a bus, whether the DMA transmission is finished or not is judged through a data stream ending identification bit, if the DMA transmission is finished, a write pointer of the buffer area address queue is added with 1, and meanwhile, the current address pointer is encapsulated into a TLP packet and sent to a device driver.
In some embodiments, the method further comprises: and responding to the completion of the data stream transmission, generating an interrupt signal, and acquiring a direct memory access read address pointer by analyzing the received data packet. When one DMA transmission is completed, one interrupt signal is generated, and then a DMA read address pointer is obtained by analyzing the received TLP data packet.
The interrupt of the PCIe bus module supports two interrupt vector inputs, vector 00 is a DMA write interrupt vector and 01 is a DMA read interrupt vector. During initialization, the host enables the MSI interrupt enabling signal, and when the cfg _ interrupt _ msiable signal is 1, the host indicates that the PCIe device supports the MSI interrupt mode. When the interrupt needs to be initiated, enabling cfg _ interrupt and cfg _ interrupt _ rdy signals, and after the two signals are effective at the same time, sending an interrupt message to a host by the PCIe IP core to realize interrupt application.
Fig. 2 is a flow chart illustrating data transmission in the PCIe bus module according to the embodiment of the present invention. As shown in fig. 2, after receiving a DMA transfer request, it is determined whether the DMA buffer is full, if so, a blocking signal is sent to the DMA buffer, and if not, the DMA buffer request is responded. And then packaging and sending a TLP (transaction layer) packet, judging whether the DMA transmission is finished in sequence, if so, generating an interrupt, and if not, continuously sending the TLP packet. And after the interrupt is generated, adding one to the DMA write pointer, sending the write pointer to the driver, and updating the DMA write pointer. At the same time, a TLP responding to the interrupt is also received, and the DMA read pointer is updated.
In some embodiments, the transmitting the corresponding data to the corresponding controlled device and resolving the chip select signal and the read/write enable signal of the direct memory access transmission request includes: judging whether the difference between a read address pointer and a write address pointer of the direct memory access buffer area is one or not; and in response to the difference between the read address pointer and the write address pointer of the direct memory access buffer area being not one, sequentially encapsulating the direct memory access data streams and transmitting the encapsulated data packets through a bus. Whether the DMA buffer is full can be judged first, and judgment can be carried out through the difference value of the read-write address pointers of the buffer. If the difference between the read-write address pointers of the buffer area is 1, the buffer area is full at this time, and the PCIe interface module blocks the data cache, otherwise, the interface module responds to the transmission request and starts DMA transmission.
And determining an operation instruction according to the read/write enable signal, and sending the operation instruction to the corresponding controlled equipment according to the chip selection signal.
The local bus control module allocates a proper read-write address space to each device according to the number of low-speed peripherals to be accessed in the instrument and the realized functions. The local bus control module receives the data from the IP core and can parse out whether the command is to be read or written. In the instrument, several low speed devices are connected directly to the signals in the local bus. These devices share the address bus (ADDR), the DATA bus (DATA), and the read/write enable (RD/WE #) in the control bus, but the chip select signals (CS #) are not shared but independent of each other. The CPU uses these separate chip select signals to access different devices.
When the CPU wants to perform data transfer with device 1, it makes CS0# active (active low). When device 1 detects that CS0# is active, the device also asserts control line RD/WE # high and low to determine whether the CPU is to initiate a read or write operation. After the judgment is finished, the device 1 responds to the read-write operation of the CPU.
Fig. 3 is a flow chart illustrating the operation of the local bus control module in the embodiment of the present invention. As shown in fig. 3, the FPGA IP core receives and sends data, and the control module analyzes the data, and determines whether the data is a write operation, if so, the low-speed device performs the write operation according to the data, if not, the low-speed device prepares the data, then pulls up the chip select signal, and the control module reads back the data and enters the next cycle.
According to the invention, the FPGA is added between the PCIe bus and the low-speed equipment, and the problem of equipment performance reduction caused by the low-speed equipment can be solved by combining the FPGA and the PCIe technology, so that compared with the PCIe equipment which needs to use a plurality of complex Switch chips, the interface circuit design is simplified.
It should be particularly noted that, the steps in the embodiments of the data interaction method described above may be mutually intersected, replaced, added, or deleted, and therefore, these methods of data interaction, which are transformed by reasonable permutation and combination, should also belong to the scope of the present invention, and should not limit the scope of the present invention to the embodiments.
In view of the above object, a second aspect of the embodiments of the present invention provides a system for data interaction, including: the device comprises a setting module, a data transmission module and a data transmission module, wherein the setting module is configured to set an FPGA between control equipment and controlled equipment and judge whether the control equipment has data to be transmitted to the corresponding controlled equipment; the sending module is configured to respond to the fact that the control equipment has data to be transmitted to corresponding controlled equipment, and send a direct memory access transmission request to the FPGA; the transmission module is configured to respond to the FPGA receiving the direct memory access transmission request, transmit corresponding data to corresponding controlled equipment and analyze a chip selection signal and a read/write enabling signal of the direct memory access transmission request; and the execution module is configured to determine an operation instruction according to the read/write enable signal and send the operation instruction to the corresponding controlled device according to the chip selection signal.
In some embodiments, the transmission module is configured to: judging whether the difference between a read address pointer and a write address pointer of the direct memory access buffer area is one or not; and in response to the difference between the read address pointer and the write address pointer of the direct memory access buffer area being not one, sequentially encapsulating the direct memory access data streams and transmitting the encapsulated data packets through a bus.
In some embodiments, the transmission module is configured to: judging whether the data stream is transmitted according to the data stream end identification bit; and adding one to the write pointer of the direct memory access buffer in response to completion of the data stream transmission, and encapsulating and sending the current address pointer to a device driver.
In some embodiments, the system further comprises: and the interrupt module is configured to generate an interrupt signal in response to completion of the data stream transmission, and acquire a direct memory access read address pointer by analyzing the received data packet.
In view of the above object, a third aspect of the embodiments of the present invention provides a computer device, including: at least one processor; and a memory storing computer instructions executable on the processor, the instructions being executable by the processor to perform the steps of: s1, setting an FPGA between the control equipment and the controlled equipment, and judging whether the control equipment has data to be transmitted to the corresponding controlled equipment; s2, responding to the data of the control equipment needing to be transmitted to the corresponding controlled equipment, and sending a direct memory access transmission request to the FPGA; s3, responding to the direct memory access transmission request received by the FPGA, transmitting corresponding data to corresponding controlled equipment and analyzing a chip selection signal and a read/write enabling signal of the direct memory access transmission request; and S4, determining an operation instruction according to the read/write enabling signal, and sending the operation instruction to the corresponding controlled device according to the chip selection signal.
In some embodiments, the transmitting the corresponding data to the corresponding controlled device and resolving the chip select signal and the read/write enable signal of the direct memory access transmission request includes: judging whether the difference between a read address pointer and a write address pointer of the direct memory access buffer area is one or not; and in response to the difference between the read address pointer and the write address pointer of the direct memory access buffer area being not one, sequentially encapsulating the direct memory access data streams and transmitting the encapsulated data packets through a bus.
In some embodiments, the transmitting the corresponding data to the corresponding controlled device and resolving the chip select signal and the read/write enable signal of the direct memory access transmission request includes: judging whether the data stream is transmitted according to the data stream end identification bit; and adding one to the write pointer of the direct memory access buffer in response to completion of the data stream transmission, and encapsulating and sending the current address pointer to a device driver.
In some embodiments, the steps further comprise: and responding to the completion of the data stream transmission, generating an interrupt signal, and acquiring a direct memory access read address pointer by analyzing the received data packet.
Fig. 4 is a schematic hardware structural diagram of an embodiment of the computer device for data interaction provided by the present invention.
Taking the apparatus shown in fig. 4 as an example, the apparatus includes a processor 201 and a memory 202, and may further include: an input device 203 and an output device 204.
The processor 201, the memory 202, the input device 203 and the output device 204 may be connected by a bus or other means, and fig. 4 illustrates the connection by a bus as an example.
The memory 202, which is a non-volatile computer-readable storage medium, may be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as program instructions/modules corresponding to the method for data interaction in the embodiments of the present application. The processor 201 executes various functional applications of the server and data processing, namely, a method for realizing data interaction of the above-described method embodiments, by executing the nonvolatile software program, instructions and modules stored in the memory 202.
The memory 202 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required for at least one function; the storage data area may store data created according to the use of the method of data interaction, and the like. Further, the memory 202 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other non-volatile solid state storage device. In some embodiments, memory 202 may optionally include memory located remotely from processor 201, which may be connected to local modules via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The input device 203 may receive information such as a user name and a password that are input. The output device 204 may include a display device such as a display screen.
Program instructions/modules corresponding to one or more methods of data interaction are stored in the memory 202 and, when executed by the processor 201, perform the methods of data interaction in any of the method embodiments described above.
Any embodiment of the computer device executing the method for data interaction can achieve the same or similar effects as any corresponding method embodiment.
The invention also provides a computer readable storage medium storing a computer program which, when executed by a processor, performs the method as above.
FIG. 5 is a schematic diagram of an embodiment of a computer storage medium for data interaction provided by the present invention. Taking the computer storage medium as shown in fig. 5 as an example, the computer readable storage medium 3 stores a computer program 31 which, when executed by a processor, performs the above method.
Finally, it should be noted that, as one of ordinary skill in the art can appreciate that all or part of the processes of the methods of the above embodiments can be implemented by a computer program to instruct related hardware, and the program of the method for data interaction can be stored in a computer readable storage medium, and when executed, the program can include the processes of the embodiments of the methods as described above. The storage medium of the program may be a magnetic disk, an optical disk, a Read Only Memory (ROM), a Random Access Memory (RAM), or the like. The embodiments of the computer program may achieve the same or similar effects as any of the above-described method embodiments.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A method of data interaction, comprising the steps of:
setting an FPGA between control equipment and controlled equipment, and judging whether the control equipment has data to be transmitted to the corresponding controlled equipment;
responding to the data which are required to be transmitted to the corresponding controlled equipment in the control equipment, and sending a direct memory access transmission request to the FPGA;
responding to the FPGA receiving the direct memory access transmission request, transmitting corresponding data to corresponding controlled equipment, and analyzing a chip selection signal and a read/write enabling signal of the direct memory access transmission request; and
and determining an operation instruction according to the read/write enabling signal, and sending the operation instruction to corresponding controlled equipment according to the chip selection signal.
2. The method of claim 1, wherein the transmitting the corresponding data to the corresponding controlled device and resolving the chip select signal and the read/write enable signal of the dma transmit request comprises:
judging whether the difference between a read address pointer and a write address pointer of the direct memory access buffer area is one or not; and
and in response to the difference between the read address pointer and the write address pointer of the direct memory access buffer area is not one, encapsulating the direct memory access data streams in sequence, and transmitting the encapsulated data packets through a bus.
3. The method of claim 2, wherein the transmitting the corresponding data to the corresponding controlled device and resolving the chip select signal and the read/write enable signal of the dma transmit request comprises:
judging whether the data stream is transmitted according to the data stream end identification bit; and
and responding to the completion of the data stream transmission, adding one to the write pointer of the direct memory access buffer area, and packaging and sending the current address pointer to a device driver.
4. The method of claim 3, further comprising:
and responding to the completion of the data stream transmission, generating an interrupt signal, and acquiring a direct memory access read address pointer by analyzing the received data packet.
5. A system for data interaction, comprising:
the device comprises a setting module, a data transmission module and a data transmission module, wherein the setting module is configured to set an FPGA between control equipment and controlled equipment and judge whether the control equipment has data to be transmitted to the corresponding controlled equipment;
the sending module is configured to respond to the fact that the control equipment has data to be transmitted to corresponding controlled equipment, and send a direct memory access transmission request to the FPGA;
the transmission module is configured to respond to the FPGA receiving the direct memory access transmission request, transmit corresponding data to corresponding controlled equipment and analyze a chip selection signal and a read/write enabling signal of the direct memory access transmission request; and
and the execution module is configured to determine an operation instruction according to the read/write enabling signal and send the operation instruction to the corresponding controlled device according to the chip selection signal.
6. The system of claim 5, wherein the transmission module is configured to:
judging whether the difference between a read address pointer and a write address pointer of the direct memory access buffer area is one or not; and
and in response to the difference between the read address pointer and the write address pointer of the direct memory access buffer area is not one, encapsulating the direct memory access data streams in sequence, and transmitting the encapsulated data packets through a bus.
7. The system of claim 6, wherein the transmission module is configured to:
judging whether the data stream is transmitted according to the data stream end identification bit; and
and responding to the completion of the data stream transmission, adding one to the write pointer of the direct memory access buffer area, and packaging and sending the current address pointer to a device driver.
8. The system of claim 7, further comprising:
and the interrupt module is configured to generate an interrupt signal in response to completion of the data stream transmission, and acquire a direct memory access read address pointer by analyzing the received data packet.
9. A computer device, comprising:
at least one processor; and
a memory storing computer instructions executable on the processor, the instructions when executed by the processor implementing the steps of the method of any one of claims 1 to 4.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, carries out the steps of the method according to any one of claims 1 to 4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110057604.XA CN112749113A (en) | 2021-01-15 | 2021-01-15 | Data interaction method, system, device and medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110057604.XA CN112749113A (en) | 2021-01-15 | 2021-01-15 | Data interaction method, system, device and medium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112749113A true CN112749113A (en) | 2021-05-04 |
Family
ID=75652262
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110057604.XA Withdrawn CN112749113A (en) | 2021-01-15 | 2021-01-15 | Data interaction method, system, device and medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112749113A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114398303A (en) * | 2022-01-19 | 2022-04-26 | 扬州万方科技股份有限公司 | Data transmission method and system for realizing low delay |
| CN114595173A (en) * | 2022-03-18 | 2022-06-07 | 山东云海国创云计算装备产业创新中心有限公司 | Data transmission method, system and computer readable storage medium |
| CN115174701A (en) * | 2022-06-30 | 2022-10-11 | 江苏科瑞恩自动化科技有限公司 | Data transmission method and device, computer equipment and storage medium |
| CN116610631A (en) * | 2023-07-21 | 2023-08-18 | 西安智多晶微电子有限公司 | FPGA (field programmable Gate array) starting configuration method supporting multi-SPI Flash access |
-
2021
- 2021-01-15 CN CN202110057604.XA patent/CN112749113A/en not_active Withdrawn
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114398303A (en) * | 2022-01-19 | 2022-04-26 | 扬州万方科技股份有限公司 | Data transmission method and system for realizing low delay |
| CN114398303B (en) * | 2022-01-19 | 2022-10-28 | 扬州万方科技股份有限公司 | Data transmission method and system for realizing low delay |
| CN114595173A (en) * | 2022-03-18 | 2022-06-07 | 山东云海国创云计算装备产业创新中心有限公司 | Data transmission method, system and computer readable storage medium |
| CN115174701A (en) * | 2022-06-30 | 2022-10-11 | 江苏科瑞恩自动化科技有限公司 | Data transmission method and device, computer equipment and storage medium |
| CN116610631A (en) * | 2023-07-21 | 2023-08-18 | 西安智多晶微电子有限公司 | FPGA (field programmable Gate array) starting configuration method supporting multi-SPI Flash access |
| CN116610631B (en) * | 2023-07-21 | 2023-09-26 | 西安智多晶微电子有限公司 | FPGA (field programmable Gate array) starting configuration method supporting multi-SPI Flash access |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112749113A (en) | Data interaction method, system, device and medium | |
| CN106951388B (en) | PCIe-based DMA data transmission method and system | |
| CN107203484B (en) | PCIe and SRIO bus bridging system based on FPGA | |
| US11829309B2 (en) | Data forwarding chip and server | |
| WO2021244194A1 (en) | Register reading/writing method, chip, subsystem, register group, and terminal | |
| CN111666242B (en) | Multi-channel communication system based on FT platform LPC bus | |
| CN114546913B (en) | Method and device for high-speed data interaction between multiple hosts based on PCIE interface | |
| CN109739786B (en) | DMA controller and heterogeneous acceleration system | |
| US12034604B2 (en) | MQTT protocol simulation method and simulation device | |
| CN114297124B (en) | Communication system of SRIO high-speed bus based on FPGA | |
| CN112131176A (en) | PCIE (peripheral component interface express) -based FPGA (field programmable Gate array) rapid local reconstruction method | |
| CN113821475A (en) | Data transmission method and device, electronic equipment and storage medium | |
| CN115374046B (en) | Multiprocessor data interaction method, device, equipment and storage medium | |
| CN112947857A (en) | Data moving method, device, equipment and computer readable storage medium | |
| CN112422485B (en) | Communication method and device of transmission control protocol | |
| CN115470163A (en) | Control method, control device, control equipment and storage medium for DMA transmission | |
| CN116431558B (en) | AXI protocol-based request response method, device, system and medium | |
| CN117591450A (en) | Data processing system, method, equipment and medium | |
| CN113533941B (en) | Chip interface testing method and device, computer equipment and storage medium | |
| KR20120054142A (en) | Soc-based system network protocol for qos and improvement of transfer efficiency | |
| CN108228517A (en) | I3C circuit arrangements, system and communication means | |
| CN116136790A (en) | Task processing method and device | |
| CN114116554A (en) | Radar data forwarding architecture and method based on FPGA | |
| CN111371799A (en) | Method, device and equipment for controlling data transmission and reception of MCTP (Multi-channel media processing protocol) controller | |
| CN116048893B (en) | Method for testing optical fiber bus interface and related equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20210504 |
|
| WW01 | Invention patent application withdrawn after publication |