CN1127280C - Method and apparatus for switching data between bitstreams of time division multiplexed network - Google Patents
Method and apparatus for switching data between bitstreams of time division multiplexed network Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 230000015654 memory Effects 0.000 claims abstract description 21
- 238000003860 storage Methods 0.000 claims description 38
- 230000001360 synchronised effect Effects 0.000 claims description 7
- 230000005540 biological transmission Effects 0.000 claims 3
- 238000013507 mapping Methods 0.000 description 71
- 239000000872 buffer Substances 0.000 description 70
- 230000000875 corresponding effect Effects 0.000 description 50
- 101100166829 Mus musculus Cenpk gene Proteins 0.000 description 39
- 230000007246 mechanism Effects 0.000 description 7
- 230000008569 process Effects 0.000 description 6
- 238000004891 communication Methods 0.000 description 5
- 230000008859 change Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 230000033228 biological regulation Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000009432 framing Methods 0.000 description 2
- 230000000977 initiatory effect Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 239000013307 optical fiber Substances 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 125000004122 cyclic group Chemical group 0.000 description 1
- 238000013506 data mapping Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 230000007717 exclusion Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 238000002203 pretreatment Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
- 230000011664 signaling Effects 0.000 description 1
- 238000011144 upstream manufacturing Methods 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/06—Time-space-time switching
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
- H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
- H04J2203/0003—Switching fabrics, e.g. transport network, control network
- H04J2203/0005—Switching elements
- H04J2203/001—Switching elements using a shared central buffer
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
- H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
- H04J2203/0028—Local loop
- H04J2203/003—Medium of transmission, e.g. fibre, cable, radio
- H04J2203/0032—Fibre
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
- H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
- H04J2203/0028—Local loop
- H04J2203/0039—Topology
- H04J2203/0044—Bus, e.g. DQDB
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
- H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
- H04J2203/0089—Multiplexing, e.g. coding, scrambling, SONET
- H04J2203/0091—Time slot assignment
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Abstract
The present invention refers to a method and an apparatus for switching data between a set of input bitstreams and a set of output bitstreams in a circuit switched time division multiplexed network, each of said bitstreams being divided into recurring frames and each of said frames being divided into time slots. According to the invention, each one of said input bitstreams is received, and frames of time slot data from said input bitstreams are temporarily stored in a set of memory means (31-34), each one of said memory means being used for storing frames of a respective bitstream of said input bitstreams. Furthermore, for each frame of each one of said output bitstreams and sequentially in accordance with the order that said time slot data are to be transmitted in the respective output frame, time slot data is selectively read from frames presently temporarily stored in said set of memory means and is then transmitted into allocated time slots of said output bitstreams.
Description
Technical field
The present invention relates to a kind of one group of incoming bit stream and one group of method and apparatus of exporting swap data between the bit stream at the circuit switching time-division multiplexing network, each described bit stream is divided into cycle frame and each described frame is divided into time slot.
Background technology
Now, developed a kind of novel circuit switched communications network network, used the time division multiplexing bit stream to transmit information, wherein the bit stream of network is divided into frame circulation, that be generally fixed dimension, and then each frame is divided into time slot.
Such one is called in DTM (dynamic synchronization load mode) the network of network example article below and is described, by Christer Bohm, Per Lindgren, Lars Ramfelt and Peter sjodin are 3 (2) of express network magazine in 1994: " the DTM giga-bit network " delivered in the 109-126 page or leaf and by Lars Gauffin, Lars Hakansson and Bjorn Pehrson are 24 (2) of the computer network in April, 1992 and ISDN system: " based on the thousands of megabit networks of DTM " delivered on the 119-139 page or leaf.
In such network, each so-called telephone net node that is connected at least two bit streams is used between different bit streams, more precisely switching time slot data between the time slot position on the different bit streams.For example, if by second group of time slot position definition circuit (or " channel ") on first group of time slot position on first bit stream and second bit stream, then telephone net node generally is used for transmitting or duplicating the time slot data to second group of time slot position from first group of time slot position.
According to prior art, the switch in the circuit switching time-division multiplexing network uses control storage that the input time slot location map is arrived the output time solt position.Such mapping can comprise the mapping of time domain, promptly controls the order that the time slot data are written into each bit stream, and the mapping of spatial domain, promptly controls which time slot data to which bit stream.For general situation, so-called TST (TST) exchange has been described in " data and the computer communication " of MacmillanPublishing Company the 4th edition by Williams Stallings.
As the example of a prior art switch, US 4 005 272 (people such as Collins) has described a switch device, and wherein the incoming bit stream frame is stored in the corresponding inlet memory and wherein exports the bit stream frame and is stored in the corresponding exit memory.According to the information that provides in a plurality of control storages, the time slot data that are stored in described inlet memory are sent to described exit memory through a space switch.First control storage is used to specify the inlet of the inlet memory that is currently connected to space switch, therefore provides a time function of exchange at arrival end.Another control storage is used to specify the inlet of the exit memory that is currently connected to space switch, therefore provides a time function of exchange at the port of export accordingly.Simultaneously, provide the interconnection of carrying out on another inherent time of control storage control space switch.
The top shortcoming of mentioning the telephone net node of type is that they do not allow arbitrarily communication between input and output port, and promptly they show for the arbitrarily restriction of switching time slot possibility on the room and time.Therefore exchange velocity and capacity have also been limited.Because the operating characteristic of the sort of space switch of using in US 4 005 272 for example, arbitrary generally is impossible to arbitrary exchange.In most of the cases, first kind of selection of a specific input time slot location map to a specific output time solt position will directly be meaned restriction for second kind of selection of other mapping.This has also limited the possibility that room and time multileaving and/or broadcasting are provided certainly.
In addition, in the prior art, input and output port uses shared medium to link together, and requires the total exchange capacity of this medium control input end mouth not cause obstruction.This general requirement is carried out the switch inter-process with the bit rate of several times of network bit stream bit rate, and this has limited the scalability of this design certainly.
Summary of the invention
The purpose of this invention is to provide a kind of switching equipment and method, they provide the bigger degree of freedom for the possibility of random switching time slot on the room and time.
Another object of the present invention provides the solution of a kind of effective control time and space multileaving and broadcast channel.
Another object of the present invention provides a kind of simple and mechanism fast, is used for exchanging between by a plurality of input and output bit streams of arbitrarily phase shift.
Another object of the present invention is to increase total exchange velocity and capacity.
A further object of the invention provides a kind of telescopic switching system, and wherein less switch can be easily integrated to form bigger switch.
Can obtain above-mentioned and other purpose by the defined the present invention of dependent claims.
According to the present invention, a kind of one group of incoming bit stream and one group of method and apparatus of exporting swap data between the bit stream that is used at the circuit switching time-division multiplexing network is provided, each described bit stream is divided into cycle frame and each described frame is divided into time slot.Incoming bit stream is received and its frame is temporarily stored in one group of storage device and (for simplicity, is called a framing buffer below).Each frame buffer is used for storing the frame of a corresponding bit stream of described incoming bit stream temporarily.For each frame of each described output bit stream with according to the order of the described time slot data sequence that will launch there, the time slot data read from the frame that temporarily is stored in described frame buffer group selectively.The described time slot data of selecting to read from described frame buffer be transmitted into subsequently described output bit stream distribute the time slot.
Therefore, embody in the switch of the present invention at one, each input port is relevant with a respective frame buffer of the frame that is used for being stored in described input port reception temporarily.All output ports can be in a kind of mode of unblock, each other independently from any one or a plurality of described frame buffer reading of data.Whole like this switch comprises a framing buffer, and each is arranged in 1 mode to a plurality of (input is to a plurality of outputs).
According to the present invention, by reading of data from the frame that is stored in described frame buffer group selectively, deadline and space exchange valuably in single integrated step, only require that the single controlled function that reads (for example using a so-called time slot mapping table to finish) is used to control each output bit stream described have select to read.
In addition, when each incoming bit stream is written into a corresponding frame buffer, and when from the time slot data of output bit stream along with request output by when described frame buffer reads, only needing according to switch of the present invention can be with basically corresponding to the speed operation of bit stream bit rate.Yet this can not stop the present invention to be used to be operated in the storage arrangement that surpasses the bit rate that wire rate is arranged.
Simultaneously, use the present invention, different with situation about often running in the prior art, input one side of storage arrangement do not need multiplexed time slot from different bit streams (or accordingly export a side go multiplexed).
According to a preferred embodiment of the invention, described frame buffer realizes by means of multiple-port random access memory (RAM), and it allows to realize independently to insert and retrieval and do not need Phase synchronization.
Have a plurality of RAM that read in port by use, each output bit stream will be independent of other bit stream and retrieve its time slot data, and preferably use the circuit that is exclusively used in described output bit stream to collect it, and a kind of choke free operation is provided like this.Therefore, need on shared resource, not repel or adopt complicated reservation scheme mutually.Thereby the speed that receives input or emission output with each circuit is compared, and need higher communication speed requirement not arranged in any part of design.Therefore, implement switch of the present invention and compare with the prior art switch, demonstrating the possibility that arbitrarily exchanges for time slot on time and the space has the very big operation degree of freedom.
Just as is understood, as long as storage arrangement such as suggested in the present invention provide the support of selecting to read access (with the order of the time-slot sequence of corresponding output frame) to having to output port, more than Jian Yi multiple-port random access memory can provide a plurality of actual physical read ports, or the single physical port of a plurality of virtual read ports (one is exclusively used in each output port) for example is provided successively.Therefore, as mentioned above, if wish like this or requirement, then a bit rate that surpasses the bit stream bit rate can be still used in the operation in storage arrangement.
Because frame buffer repeats to upgrade with two-forty, it is contemplated that to not needing memory refress based on the realization of dynamic ram (DRAM).
As mentioned, according to a preferred embodiment of the invention, all output ports are independently of each other from described frame buffer group reading of data, and the time slot data are preferably on the circuit that is exclusively used in each output port and are sent to output port from described frame buffer.
Usually, each described frame buffer will comprise a plurality of time slot data inlets, each time slot data inlet of one of them frame buffer is arranged with the time slot data of storage from the respective cycle time slot position, and described position is in the sequence of time slots of the incoming bit stream relevant with described frame buffer.
Because the time slot data can be read different output ports from any time slot item of described frame buffer, so, the mechanism's (promptly sending data to a plurality of output ports from an input port) that is used to broadcast with multileaving impliedly is provided.
Switch device according to the present invention preferably includes for example have the control storage form device of (" time slot mapping table "), for being assigned to receive from those time slots in the frame of each output bit stream of the time slot data of incoming bit stream, its each corresponding sign that provides the related time-slot data of described frame buffer to enter the mouth is provided, described time slot data inlet provides the time slot data for corresponding distributed time slot.
A kind of like this sign can for example be that a kind of unique identification frame buffer and its provide the sign of the time slot data that will be launched into the output time solt relevant with described sign, expression writes access to corresponding output time solt and does not belong to switch and output time solt sign from the time slot data of described incoming bit stream will be provided, idle mode will be produced and be launched into the sign of corresponding output time solt by switch, and perhaps the time slot data that receive from another switch will be launched into the sign of described corresponding time slot.The swap data of being appointed as of collecting the data of each output time solt so wherefrom provides some kinds of new possibilities.For example, the type of back makes and may in a simple manner a plurality of switches be connected to form a bigger switch in four exemplary type of above-mentioned sign, therefore increased exchange possibility and basically very intricately realize.
Each incoming frame buffer preferably has three sequence frames, the frame page or leaf that is also referred to as described frame buffer or the capacity of row that keeps incoming bit stream in corresponding frame memory area territory.Each incoming bit stream uses three frame pages or leaves to mean the consistency of guaranteeing to exchange, promptly guarantee from a frame or one page read selectively the input that can not occur in this specific frame or page or leaf write finish before.According to preferred embodiment, need one page to allow the time slot that in time domain, remaps, need another page to store concurrently in the mode of double buffering, any frame phase difference between the output port that needs the 3rd page of input port of managing to write described frame buffer and read from described frame buffer, promptly, be restricted to the difference of one page as for example general synchronous result of DTM network.
Usually by corresponding frame synchronizing signal control, it then advances internal pointer to discern current frame page or leaf or the current frame page or leaf that is used to read (at an output port) that is used to write (at an input port) to each input and output port.The time slot of incoming bit stream reads output from described frame buffer for the arbitrary access among the item of selecting to read the page or leaf that then uses current selection with the order write memory of order.
Therefore, the local clock and the frame synchronizing signal that use each port are come timing time slot and frame, and pass through port access frame buffer device according to corresponding local frame synchronization.Basic imagination is that frame synchronizing signal never has the skew greater than a frame, it is the phase difference between incoming bit stream and the output bit stream, just do not have the frame poor (deviation) of accumulation, it is the criterion that for example adapts in the DTM network, so the present invention is significant especially in a kind of like this network.
The frame synchronization of incoming bit stream is preferably controlled one and is write time slot counter, time slot according to each reception, it make the time slot item of specifying the respective frame buffer write pointer advance to next time slot item (according to frame synchronization, write time slot counter preferably be reset begin with minimum time slot at next frame).The frame synchronization of incoming bit stream is preferably also controlled one and is write page or leaf selection piece, and its specifies one page of respective frame buffer, and one of three frames that allow buffer are used to write access (according to frame synchronization, selecting next frame page or leaf in the mode of circulation).
The frame synchronization of output bit stream is preferably controlled an output time solt counter, at each output time solt, it advances to obtain about where collecting the information (according to frame synchronization, the output time solt counter preferably is reset and begins with the minimum time slot at next output frame) of the time slot data of the output time solt that is used for subordinate pointer in the described time slot table.The frame synchronization of output bit stream is preferably also controlled one and is read page or leaf and select a piece, and its is selected, and which frame page or leaf of respective frame buffer is current can be used for reading selectively access.According to frame synchronization, select next frame page or leaf in a looping fashion.
Therefore, an advantage of the invention is that the control operation at each port of switch is provided by the local frame synchronization to each corresponding port, eliminated the needs of the crosscorrelation lazy-tongs that between different input and output ports, provide complicated like this.
According to another improved embodiment of the present invention,,, control described selection of reading page or leaf as on time-slot by time-slot basis, activating by the time slot mapping table also by so-called page or leaf skew and bypass characteristic.Bypass mode provides selection to obtain to read frame of access actual before reading access indicator, and it has reduced the stand-by period through switch, but has limited time slot allocation, so that guarantee not have access conflict or inconsistent generation during time domain remaps.
According to another embodiment of the invention, provide a kind of mechanism that is used to finish the automatic renewal of time slot mapping table, promptly preserved conforming mode and upgrade a plurality of time slot tables and its a plurality of time slot items simultaneously with a kind of.
Best implementation according to exchange of the present invention is in the DTM network.The basic topological structure of DTM network is the buses with two multiple access optical fiber unidirectional, a plurality of nodes of connection preferably.Yet, notice that topological structure also may be only realized by the structure of any other type, for example loop configuration or hub architecture.
The bandwidth of each wavelength on the bus, promptly each bit stream on each optical fiber is divided into frame regular length, that be generally 125 μ s, these frames then be divided into regular length, be generally 64 time slot.The quantity of time slot depends on the bit rate of network in the one-period like this.Time slot is divided into two groups, control time slot and data slot.The control time slot is used for transmitting signaling message between the described node of network internal operation.Data slot is used for the terminal use or uses described node to insert between the application of DTM network and transmit data.
To corresponding channel, the node of DTM network generally is arranged dynamically to set up, the channel on modification and the described bit stream of terminating by time slot that dynamically distribute to select.Therefore, can regulate along with offered load change dynamics ground for different nodes or terminal use's the time slot and the distribution of data slot.As is understood, title or the address information that in such circuit switching, in data slot, does not embed in fact.
For the more detailed description of DTM technology, can be referring to " DTM giga-bit network " above-mentioned and " based on thousands of megabit networks of DTM ".
Description of drawings
With reference to example embodiment, accompanying drawing, can more fully understand above-mentioned and other aspect and the feature of the present invention from following description.
Referring now to accompanying drawing example embodiment of the present invention is described, wherein:
Fig. 1 schematically shows one and realizes the time of time slot data and the switch device of space exchange;
Fig. 2 schematically shows a switch device according to the embodiment of the invention;
Fig. 3 schematically shows an embodiment who is used in the time slot mapping table in the switch shown in Figure 2;
Fig. 4 schematically shows one and is used in the frame page or leaf selection mechanism of each input and output port of switch according to the preferred embodiment of the invention.
Fig. 5 a and 5b schematically show the page or leaf skew with remap fully mode and bypass mode respectively;
Fig. 6 schematically shows the part of switching equipment in accordance with another embodiment of the present invention; And
Fig. 7,8a and 8b schematically show the mechanism of the time slot mapping table that is used to upgrade shown in Fig. 3.
Embodiment
In Fig. 1, switch device Sw is used for swap data between one group of incoming bit stream of circuit switching time-division multiplexing network and one group of output bit stream, and each described bit stream is divided into cycle frame and each described frame is divided into time slot.More precisely, the switch device Sw of Fig. 1 will be from the time slot A of the frame of incoming bit stream A and B on time and space
0-A
n, B
0-B
nThe time slot data exchange in the time slot of frame of second bit stream C and D.As shown in Figure 1, the output frame of bit stream C comprises from the one or more of any selection of incoming bit stream A, B and the data that transmit from the random input time slot of its selection.A in the frame of output bit stream C and D
0Appearance corresponding to multileaving A to C and D output bit stream
0The content of input time slot, but to the different time-gap of output frame.
The switch device of the example embodiment according to the present invention is described referring now to Fig. 2.In Fig. 2, switch Sw receives from the time slot data of four incoming bit stream 1-4 and with timeslot number and reportedly delivers to four output bit stream 5-8.Therefore, switch Sw comprises four input media access unit 21-24 and four output medium access unit 65-68, provides to be linked into corresponding bit-stream.
Each input media access unit 21-24 is arranged each frame that receives from corresponding bit stream is write corresponding frame buffer 31-34.Each frame buffer 31-34 has in three corresponding frame memory area territories or page or leaf 31a-31c, 32a-32c, 33a-33c and 34a-34c store the capacity of three sequence frames of corresponding bit stream, and each page has the capacity of a frame of storage.For example, interim storage process input media access unit 21 sequentially is stored in first frame frame page or leaf 31a from the frame buffer 31 of each frame that bit stream 1 receives, next (second) frame is stored in frame page or leaf 31b, and ensuing (the 3rd) frame is stored in frame page or leaf 31c.Then, (the 4th) frame of following also will use frame page or leaf 31a to store, and rewrite previously stored first frame like this.Simultaneously, the item of the corresponding time slot data of respective frame page or leaf is sequentially write in attention from the time slot data of the time slot of a frame, and promptly data for each input time slot enter the mouth.
Simultaneously, as illustrate among the embodiment that is described below, four time slot data selection unit 45-48 can be for example provide with the form of multiplexer or tristate bus line, be arranged to by for each output time solt that will be launched into corresponding output bit stream, determine which frame buffer, its frame page or leaf and its time slot data inlet (promptly among time slot data) from the current storage of all four incoming bit stream 1-4, the time slot data are collected or are delivered to corresponding output bit stream, and selection will be launched into the time slot data of corresponding output bit stream 5-8.Therefore, each selected cell 45-48 is connected to the time slot data that all four frame buffer 31-34 are used to select and collect the there.
In order to know which frame buffer, page or leaf and item are used for a specific output time solt, each selected cell 45-48 can use a corresponding time slot mapping table 55-58, with reference to Fig. 3 this table is described in more detail below, for each time slot of corresponding output bit stream frame with at corresponding, this table provides the field 55b-55b of the item of the time slot data that the field 55a-58a of a designated frame buffer and appointment be used to read output time solt.The output time solt item of time slot mapping table 55-58 is preferably with the storage of the time sequencing order of corresponding output frame, and each time slot mapping table for each frame stepping of corresponding bit stream once.
Therefore, when read bit flows the time slot data of first time slot in 5 each frame, selected cell 45 will be visited first of time slot mapping table 55, first data field of first data field of 55a row and 55b row more precisely, with obtain about which and it in four frame buffers which the time slot data be collected the information of first output time solt of the frame that is used for bit stream 5.Equally, as described in more detail below, for the current frame that is sent to bit stream 5, which frame page or leaf that selected cell 45 will be controlled each frame buffer 31-34 of selection is used to read the time slot data.Therefore, selected cell will pick up the time slot data with given output order, be used to be provided to each output bit stream time slot of receiving slot data.Certainly, switch Sw will only transmit time slot data those time slots to the output bit stream that distributes for this purpose.
The embodiment of the time slot mapping table of the sort of type of discussing with reference to Fig. 2 (and below with reference to Fig. 7) above describing referring now to Fig. 3.The time slot mapping table is a table that defines allocated channel.As shown in Figure 2, preferably a time slot mapping table is arranged for each output bit stream.Time slot mapping table shown in Fig. 3 is the degree of depth of a frame and comprises four logical storage zones or row 12-18, each row comprises a plurality of fields corresponding to timeslot number in the output frame, makes to comprise that from a field of each row each discern incoming bit stream and its time slot uniquely for each output time solt.The position of time slot in first row, the 12 identification output frames.Incoming bit stream of each Field Definition (or incoming frame buffer) of secondary series 13 (also the 55a at Fig. 2 illustrates), and its time slot of each Field Definition of the 3rd row 16 (also the 55b at Fig. 2 illustrates) (or its frame buffer data inlet), the Field Definition of the 4th row 18 will be below with reference to the skew of Fig. 4,5a and 5b frame page or leaf discussed in detail.For the output time solt of each order, promptly for each item in proper order of time slot mapping table, the time slot mapping table defines the time slot list of output frame like this, and combines the exchange on time and spatial domain.
For each output frame, the item of time slot mapping table is by the order run-down with order, and with the mapping of each output time solt of defining it, and the time slot data of being correlated with from frame buffer are directly specified in the output of time slot mapping table.Like this, as below describing, only need to produce to the sequence address of time slot mapping table with a simple counting device, this table is converted to the random reference that is used for the buffer data retrieval with these.
Like this, use the demonstration time slot mapping table shown in Fig. 3, with shown in first time slot of each output frame of closing of time slot mapping epiphase will comprise time slot data from the 15th time slot of each frame of the 3rd incoming bit stream, second output time solt do not possess the data from any incoming bit stream, if the access of writing to second output time solt is assigned with by switch device and uses, then selectively cause writing of an idle hyte, the time slot data of the 3rd output time solt will be taken out at the 3988th time slot of each frame of second incoming bit stream, or the like.
Be described in the frame page or leaf selection mechanism that each input and output port uses referring now to Fig. 4,5a and 5b.Input for the time slot data of frame buffer, and use the time slot mapping table to have and select to read the output time solt data, by separate and independently frame synchronizing signal control, this signal obtains or the definition corresponding bit-stream from corresponding bit-stream, and they comprise that together N (quantity of input) adds the exchange of M (quantity of output) clocking domain.Frame synchronizing signal is used for advancing and writes accordingly or reading pointer is selected the frame page or leaf of corresponding frame buffer.
For each bit stream, promptly for bit stream of each input with for a bit stream of each output, which the frame page or leaf that illustrates among Fig. 4, be used to control corresponding frame buffer by the corresponding pointer blocks 100 of corresponding frame synchronizing signal Frame Synch timing is used for frame and writes or select the addressing of reading.In each pointer blocks 100, self-excitation counter 102 increases progressively 1 in mould 3 modes with the frame page address of selecting according to each reception of corresponding frame synchronizing signal, and frame page pointer address 0,1,2,0,1,2 so sequentially is provided ..., or the like.Further discuss with reference to Fig. 5 a and 5b as following, a page or leaf shifted signal (for example the value that provides in the 4th row 18 by Fig. 3 time slot mapping table provides) also is provided each pointer blocks 100, is added in a value of mould 3 adders 104 these signals on the value of (also in mould 3 modes) self-excitation counter to provide final frame page or leaf to select signal.
Specifying what take place with the order of the frame page or leaf of the frame buffer of the frame that is used to write corresponding bit stream is that the corresponding order that is used for the frame page or leaf of the frame buffer that the selection of time slot data reads is specified.For each frame buffer, will provide one to write pointer (relevant) and M reading pointer (selection of each and corresponding output bit stream is read relevant, and M is the quantity of output bit stream) with writing of corresponding incoming bit stream.
Importantly finish for the appointment of the frame page or leaf that writes with for the appointment of the frame page or leaf of selecting to read, thereby keep the buffer consistency, to avoid before finishing it write, reading the time slot data of frame.As further discussing,, therefore make the minimum range that may between the writing and read of each time slot data, always keep half frame by using three frame page memories to obtain such consistency for each bit stream frame buffer with reference to Fig. 5 a and 5b.
Mention with reference to Fig. 3 as top, when the pointer blocks 100 of Fig. 4 was used in the output port that the selection of frame reads, self-excitation counter frame page address was revised selectively by the page or leaf shifted signal that receives from the time slot mapping table is provided.Frame page or leaf shifted signal obtains from the frame page or leaf offset column of time slot mapping table (Fig. 3 18), and equally in mould 3 modes, by a skew being added thereunto to form the address that a skew page address is revised pointer blocks.Therefore, according to frame synchronization phase deviation (being the phase difference between the input and output bit stream frame) and limited-access criterion, regulation frame page or leaf shifted signal on the basis of each time slot.Limited-access is the restriction of forcing in the time exchange, is remapped to the stand-by period of cost reduction by switch to limit the possible time.The scope of frame synchronization phase deviation is expressed as the part of entire frame in-1＜skew＜1.
Fig. 5 a be illustrated in so-called remap fully during, promptly when not applying limited-access, be also referred to as standard or the page or leaf skew during normal mode distribute.In Fig. 5 a, frame page or leaf skew selective sequential, that be used for the pointer blocks that incoming bit stream writes of supposing designated frame buffers frames page or leaf is set to 2, this means after the next frame synchronizing signal of incoming bit stream receives, write will move to actual buffers frames page or leaf 0 (in mould 3=2+1).Read and to use 0 or 1 replacement reference to storage zone according to frame synchronization phase deviation from the selection of frame buffer subsequently as the page or leaf skew.When being operated in the minus phase skew, this means that the frame synchronizing signal of output bit stream appears at before the frame synchronizing signal of incoming bit stream, the page or leaf skew is set to 0 (the replacement cursor arrow of lower left among Fig. 5 a).Like this, selecting to read the pointer that writes that will always jump to next frame page or leaf if having time and will can not moved to new frame page or leaf later on catch up with.When being operated in positive phase deviation, promptly when output bit stream frame synchronizing signal arrived after the incoming bit stream frame synchronizing signal, the page or leaf skew was set to 1 (the replacement cursor arrow in Fig. 5 a lower right corner).As is understood, this is corresponding to add a frame page or leaf (frame) buffer surplus between writing and reading.Equally, these allocation rule guarantee that the renewal that writes of frame page or leaf is finished when reading the frame page pointer and advance to a new page or leaf.It also meaned by proceed to next frame page or leaf at reading pointer before and enters the frame page or leaf of being read, upgrade write pointer will be not can wraparound and catch up with.
Fig. 5 b illustrates the frame page or leaf skew that distributes with so-called bypass mode, and it can be by the data excitation of time slot mapping table the four row 18 of Fig. 3.As is understood, in the above in the normal mode with reference to Fig. 5 a discussion, the switch output time solt to the end that allows to remap fully from the data of first input time slot, vice versa, but this not only require to cushion one write the page or leaf and one read page or leaf, and require an extra frame (the 3rd page) to guarantee consistency, so it has introduced the propagation stand-by period by switch.Discuss as following, in bypass mode, the stand-by period by switch can be with the cost that is restricted to that the time is remapped, and one or more time slots of frame are reduced a frame relatively.Therefore, in the bypass mode shown in Fig. 5 b, as Fig. 5 b explanation pass through will replace the reading pointer arrow and compare to move right with Fig. 5 a and move a step, the normal mode page or leaf skew of Fig. 5 a is increased progressively 1 provisionally for independent one or more time slots of a frame, thereby it allows to write and the identical page or leaf of the interim use of the reader of selecting.
Certainly, this bypass mode may only not allow under the restriction of reading before the write device of order at the reader of selecting, it guarantees if do not export the output time solt of bit stream, then receives from the data input time slot of incoming bit stream, that have higher sequence of time slots number.Like this, output time solt #9 can use bypass mode to reduce stand-by period by switch when from input time slot # 3 reading of data, but output time solt # 3 can not use bypass mode from input time slot #9 read data.
In fact, when considering actual skew, can loosen this requirement for bypass.For simplicity, hypothesis is represented phase deviation in time slot now.When phase deviation is positive, in the time of promptly before the frame synchronizing signal of incoming bit stream appears at the frame synchronizing signal of exporting bit stream, (writing synchronously before reading of selection is synchronous), as long as the switch reference is other parameter of phase deviation rather than front, phase deviation can be used to allow read from the input time slot with higher order number the time slot data of output time solt.For negative phase deviation, in the time of promptly before the frame synchronizing signal of output bit stream appears at the frame synchronizing signal of incoming bit stream (be written in select to read before), normal mode has added the surplus of a frame, it means if phase deviation is almost zero does not bear, and then allows most bypass to remap.On the other hand, when phase deviation almost is a frame of bearing, do not allow the bypass reference of front.This situation is summarised in the following Table I.
Table I
| Mode | Phase deviation | Stand-by period |
The mapping | |
| Standard | Positive | |||
| 1 frame+phase deviation | Do not have | |||
| | Bear | 2 frames-ABS (phase deviation) | Do not have | |
| Bypass | Positive | Phase deviation | Input time slot #-output time solt＜phase | |
| Bypass | Bear | |||
| 1 frame-ABS (phase deviation) | Input time slot #-output time solt＜phase deviation |
As is understood, frame synchronization and the page or leaf selection mechanism described with reference to Fig. 4,5a and 5b preferably are used among the embodiment of Fig. 2, and the parts of even now are not clearly shown that there that it is also contained among the embodiment that describes below with reference to Fig. 6 equally.
Describe referring now to Fig. 6 and to have comprised another embodiment that top Fig. 2,3,4,5a and 5b describe the switch of the present invention of characteristic, wherein switch device Sw is arranged at N incoming bit stream and M and exports switching time slot data between the bit stream.For the purpose of describing easily, because the exchange of one to M output bit stream from N incoming bit stream demonstrates and the identical configuration of other incoming bit stream exchanges, and because the selection reading displayed of each goes out identical configuration from N incoming bit stream frame buffer to M output bit stream, as Fig. 2 explanation, it is shown in Figure 6 to have only main and an incoming bit stream and one to export the relevant parts of bit stream, so the description of the switch device of Fig. 6 is limited.
In Fig. 6, incoming bit stream is received and is provided to input demultiplexer 220 by the input port 210 of switch Sw.The frame synchronization unit of input port obtains the frame synchronizing signal from incoming bit stream, and it is synchronous with the operation that writes page selected cell 250 to write time slot counter 240 in view of the above.Equally, the clock unit of input port 210 is arranged to be provided at the signal of time slot frequency generation to writing time slot counter 240.Write incoming frame page or leaf selected cell 250 and be arranged rate controlled demultiplexer 220 with frame synchronizing signal, for the described incoming bit stream of mould 3 modes, make incoming bit stream each frame sequential be delivered among 300 3 frame pages or leaves of frame buffer (or " memory area ") 300a, 300b and the 300c one.The particular frame that is transfused to bit stream when the page or leaf that writes page selected cell 250 and input demultiplexer 220 which frame buffer of control is write fashionable, writes item quilt which page or leaf time slot counter will control and writes from the time slot data of each particular time-slot of a frame.As is understood, will find the component set of this description at each incoming bit stream port of switch Sw.
The output of the switch shown in Fig. 6 lower part comprises for first group of M output multiplexer 310 of each output bit stream, second output multiplexer 320, output port 330, output time solt counter 350, time slot mapping table 370, frame page or leaf selected cell 380 and idle slotted mode generator 390.
Output port 330 is from exporting bit stream (if existed synchronously on described bit stream, then described bit stream results from the node that is positioned at relative switch upstream), perhaps the inside by frame synchronizing signal produces (if switch is in starting point of output bit stream) and obtains frame synchronizing signal.
Frame synchronizing signal is provided to the operation of synchronous output time solt counter 350 and frame page or leaf selected cell 380.Output port also acquires the clock signal that occurs in the time slot frequency of output time solt counter 350.The item of output time solt counter 350 tables 370 of addressing time slot mapping sequentially, each frame stepping by the time slot mapping table once.Like this, for the specific output time solt of an output bit stream, the output time solt counter will point to a corresponding entry of time slot mapping table 370.Discuss as top, the time slot mapping table will provide three based on the signal that reads from this subsequently, discuss with reference to Fig. 3,4,5a, 5b as top, the incoming bit stream that the time slot data of an assigned timeslot are collected, which signal sends to second output multiplexer 320, the time slot data of which time slot of the cyclic sequence of time slot are collected in one frame of an appointment incoming bit stream, which signal sends to all N frame buffer, and which page skew a signal specify to be used, and which signal sends to frame page or leaf selected cell 380.
At first, selected input time slot quantity when the output time solt of pre-treatment, input time slot quantity i for example, in arbitrary access, be provided to N the frame buffer (Fig. 6 only illustrates) each, make from each three pages of N frame buffer each read i item (providing total reading) like this from 3 * N data field from time slot mapping table 370.Three of each frame buffer read described first group that sends to output multiplexer 310 subsequently, and each multiplexer 310 is the receiving slot data from three pages of relevant frame buffer.Frame page or leaf selected cell 380 is arranged described first group with the rate controlled of frame synchronizing signal output multiplexer 310 subsequently, consider from any frame page or leaf skew of time slot mapping table reception or the appearance of bypass instruction which determines transmit by multiplexer 310 at any given time corresponding to the time slot data of corresponding page or leaf.Therefore each in first group of output multiplexer 310 will provide the time slot data from a field of respective frame buffer, suppose that total N is read timeslot number and reportedly be delivered to second output multiplexer 320.As select the signal appointment from the bit stream of time slot mapping table 370, in second multiplexer, determine described N in reading which, promptly from which bit stream, be passed to the output bit stream.Like this, time slot mapping table 370 and frame page or leaf selected cell 380 use described first and second multiplexers 310,320 to retrieve a regioselective time slot data field from a frame buffer of selecting.
Equally, as shown in Figure 6, an idle slotted mode and a cascade input are provided to second output multiplexer.Therefore, time slot mapping table 370 can be for any particular time-slot of defeated stream, order second output multiplexer 320 to be sent to the output bit stream, for example second of the time slot data mapping tables of Fig. 3, unappropriated time slot from the idle slotted mode of idle slotted mode generator 390.Yet, notice that a unappropriated time slot not necessarily means send an idle pulley, because time slot may very well be divided other nodes that are equipped with by being connected to the output bit stream to use.In order to regulate the possibility that a plurality of switches of such connection are big switch, can use the cascade input.Then, be connected to the cascade input of second multiplexer from the output bit stream of another switch, so still as the control of time slot mapping table 370, may with from the exchanges data of described another switch in the output bit stream of switch Sw.The possibility of cascade allows to use some less switches to realize that bigger flock-mate changes planes, and for example uses four 4 * 4 switches to realize 8 * 8 complete switches.
The configuration instruction of representing as Fig. 6 arrow and followingly describe, provide configuration signal from the Node Controller of control time slot mapping table renewal to there with reference to Fig. 7,8a and 8b.
As is understood, this description of output block 310-390 set will be found in each of M carry-out bit flow port of switch, so for example provide altogether N * M first output multiplexer and individual second multiplexer of M altogether.
As described above, at the output of each frame buffer, first order multiplexer is used to select the data from three frame pages or leaves there.Its result feeds second level multiplexer subsequently to select from a specific bit stream (input port).This scheme is used for following purpose, and a) the explanation data transmit being exclusively used on the circuit of each output, have avoided the requirement of shared common medium like this, and b) can control the different parameter of selection.
Yet, consider the hardware cost of selecting many width bus routes, it is also conceivable that other standarized components of non-multiplexer.Therefore, in another embodiment, use three-state or precharge bus to replace multiplexer to be used for the identical purpose of multiplexer but have better zone and utilize.When using standard RAM (RAM) module to come the achieve frame buffer, generally comprised ternary output.Should notice that such an embodiment does not require any other mutual exclusion device.At each constantly, allowing the source of driving bus is unique regulation.In such an embodiment, the signal that is used for enable driver is produced by decoder block, and this decoder block has input port (as reading the time slot mapping table) and frame page pointer (0,1,2) conduct input.
Similarly, replace the frame of incoming bit stream is provided to the input demultiplexer of frame buffer respective frame page or leaf, also can substitute, wherein write enable signal and select which writes with all buses of three pages of feeding.
Referring now to Fig. 7,8a and 8b the process that is used to upgrade switch time slot mapping table according to the present invention is described.Because resource is redistributed, the channel or the time slot that exchange between different bit streams change thereupon, use the external interface of center cell in the switch or the computer by the control switch to upgrade the time slot mapping table of switch, such center cell or computer usually are called Node Controller (NC).Externally provide under the situation of computer, external interface separates with the port of switch, and the bandwidth that the time slot mapping table upgrades is generally much lower than the bandwidth of switch ports themselves.
Problem when the time slot mapping table is upgraded in a plurality of outputs with different frame phase place is to keep consistency, and it for example is requirement when redistributing multileaving.A useful mode that addresses this problem illustrates at Fig. 7,8a and 8b, this problem is not restricted to the renewal of multileaving channel on a plurality of output ports certainly, wherein Fig. 7 illustrates three updating forms by the Node Controller addressing, Fig. 8 a illustrates the flow chart that Node Controller upgrades operation, being called the overall situation upgrades, Fig. 8 b illustrates the flow chart that each time slot mapping table upgrades operation, is called local updating.
When beginning during a renewal process, at the step S10 of Fig. 8 a, Node Controller is the updating form shown in addressing Fig. 7 410,420 and 430, it for example can be in Node Controller or with the switch of Node Controller communication in provide.At first, at step S20, Node Controller will provide the table 430 with one group of item (table 430 is used for each time slot mapping table), and these are specified, and which output time solt upgrades in corresponding time slot mapping table and the data of which corresponding data in the corresponding entry replace old of described time slot mapping table in the output time solt sequence.As determining at step S30, presetting all themes for all theme time slot mapping tables by this way upgrades, Node Controller will be by being provided with a group echo, each time slot mapping table one mark, 1 (table 410 expression of Fig. 7 is to the indication of four time slot mapping tables) in the table 410 comes order time slot mapping table to upgrade their content.A frame option table 420 also is provided, has the information of which selection frame of mould 3 order that specify in frame, this time slot mapping table will upgrade their content.
Correspondingly, the beginning of every frame of representing by the reception of frame synchronizing signal at step B10, each time slot mapping table will be in step B20 application form 410 its mark, look at whether its time slot mapping table will be updated.If not, be zero if promptly belong to the mark set of time slot mapping table, then with above-described general fashion, the time slot mapping table will selectively read the time slot data from the incoming frame buffer at step B30, B40 and B50 initiation command.Yet, if mark indication requires to upgrade, be 1 if promptly belong to the mark set of time slot mapping table, step B60 time slot mapping table will check frame option table 420 look at time slot mapping table whether should the beginning of present frame or in the back frame begin renewal.To take place at the frame of back if upgrade, then with above-described general fashion, the time slot mapping table reads the time slot data with initiation command selectively from the incoming frame buffer.Yet, if take place during 420 indications of frame option table are updated in present frame, then the time slot mapping table will begin to handle time slot as usual, but look at will being updated of theme time slot whether for each its updating form of time slot item inspection 430 at step B70, if like this, then before carrying out reading of selecting, be used in the information updating item that updating form 430 provides.When stepping by this way during by entire frame, Node Controller is notified in will reset in table 410 its update mark of time slot mapping table like this, and its renewal is finished.
Correspondingly, Node Controller will repeatedly be checked updating form 410 at step S50, look at resetted their mark of all time slot mapping tables whether.If done like this, promptly when the institute underlined reset-to-zero of table 410, S60 finishes renewal process in step.
Design this renewal process to reduce synchronizing signal again, promptly from the quantity of the signal of synchronous other clock zones.Can depend on a set-reset flip-flop synchronously for what each output was selected.Controlling each by local time slot mapping table renewal process then resets.
In another embodiment, the single time slot that replaces updating form upgrades, and Node Controller can provide data for whole new frame, orders the data of time slot mapping table exchange entire frame so simply.Yet a small amount of time slot of a frame can prove that this embodiment that compares with the time slot that only upgrades a subclass does not expend time in.
Though top specific embodiment with reference to demonstration has been described the present invention, it should be appreciated by those skilled in the art, can carry out various modifications, change and combination here and do not deviate from scope of the present invention by accessory claim book definition.
Claims (28)
1. one kind is used between one group of incoming bit stream of circuit switching time-division multiplexing network and one group of output bit stream the method for swap data on time and space, each described bit stream is divided into cycle frame and each described frame is divided into time slot, and described method comprises step:
Receive each described incoming bit stream;
Interim storage is from the time slot Frame of described incoming bit stream, and wherein the frame from different incoming bit streams is stored in the corresponding memory device of storage stack device;
For each output frame of each described output bit stream, the frame from temporarily be stored in described banks of memory devices reads the time slot data selectively; Wherein be independent of other bit streams and finish for reading of the described selection of each bit stream, and wherein said selection read make the data based described time slot data that in corresponding output frame, will be transmitted of time slot sequence read; And
The described time slot data that the read distributed time slot to described output bit stream is selected in transmission from described interim storage frame.
2. the method for claim 1, wherein said independence reads and provides by finishes described selection on the circuit that is exclusively used in each output bit stream.
3. method as claimed in claim 1 or 2, the step of wherein said interim storage comprise the time slot data of interim storage from the respective cycle time slot position in the sequence of the described incoming bit stream time slot of the corresponding time slot data inlet of described storage arrangement.
4. method as claimed in claim 1 or 2, the described step that wherein reads selectively comprises step:
For the order time slot of a frame of a bit stream of described output bit stream, the corresponding sign that provides of the time slot data inlet of described banks of memory devices is provided, described time slot data inlet provides the time slot data of described time slot; And
For the described time slot of described frame, read the time slot data from described time slot data inlet selectively based on described sign.
5. claim 1 or 2 described methods as described above, comprise step: receive additional bit stream, time slot for the frame of at least one bit stream of described output bit stream, described time slot is assigned with to receive the time slot data from described additional bit stream, read from the time slot data based on the described additional bit stream of a sign, the described time slot of this sign indication is arranged to receive the time slot data from described additional bit stream.
6. claim 1 or 2 described methods comprise step as described above, one sign is provided for each time slot of a frame of each described output bit stream, whether the corresponding time slot of the described output bit stream of this sign appointment receives the time slot data from any one described incoming bit stream, if like this, collect described time slot data from the time slot data inlet of which described storage arrangement.
7. method as claimed in claim 6 comprises step, provide a group id to upgrade and relevant information regularly, this regularly is relevant to and when uses described identification renewal to upgrade described sign, and adopts described identification renewal to upgrade described sign in the time of described relevant timing information appointment.
As described above in the claim 1 or 2 described methods comprise step, for each described incoming bit stream, detect frame synchronizing signal, and frame synchronization that in view of the above will described interim storage arrives the respective stored apparatus of described banks of memory devices.
As described above in the claim 1 or 2 described methods comprise step, for each described output bit stream, determine frame synchronization, and make the described selection of time slot data read with them synchronous in view of the above to the transmission of corresponding output bit stream.
10. 1 or 2 described methods in the claim as described above, wherein the described step of interim storage comprises three sequence frames of interim each described incoming bit stream of storage.
11. method as claimed in claim 10 comprises step, at each of point, indicates which current memory that is written in three sequence frames of interim storage of each described incoming bit stream preset time.
12. method as claimed in claim 10 comprises step, at each of point, indicates in three sequence frames of interim storage of each described incoming bit stream which current selection that is used for described output bit stream timeslot number certificate to read preset time.
13. 1 or 2 described methods in the claim as described above, the channel on the wherein said bit stream is by the corresponding time slot group definition of corresponding each frame of bit stream, and described time slot is dynamically allocated according to the requirement that network node dynamically changes capacity.
14. one group of incoming bit stream and one group of equipment of exporting swap data between the bit stream that is used at Circuit-switched time-division multiplexing network, each described bit stream is divided into cycle frame and each described frame is divided into time slot, and described equipment comprises:
Input unit (21-24; 210) be used to receive each described incoming bit stream;
Storage stack device (31-34; 300), each storage arrangement is arranged for storing the frame of the corresponding bit stream of described incoming bit stream temporarily;
Select reading device (45-48,55-58; 310,320,370,380), each output frame for each described output bit stream, time slot data from frame are stored in the described banks of memory devices temporarily, wherein read for the described selection of each bit stream to be independent of other bit streams and to finish, and wherein said selection are read with reading the sequence that causes the data based described time slot data that will be launched of time slot in corresponding output frame; And
Output device (5-8; 330), be used to transmit the described time slot data that read selectively by described selection reading device distributed time slot to described output bit stream.
15. equipment as claimed in claim 14 wherein is each described storage arrangement (31-34; 300) provide a plurality of read ports, and wherein each described read port is arranged in the described output bit stream corresponding one.
16. as claim 14 or 15 described equipment, wherein said selection reading device comprises one group of reading device, each reading device is arranged to read the time slot data for a corresponding bit stream of described output bit stream.
17. as claim 14 or 15 described equipment, each storage arrangement of wherein said banks of memory devices comprises a plurality of time slot data inlets, and each time slot data inlet of a storage arrangement of wherein said banks of memory devices is arranged to store the time slot data from a respective cycle time slot position in the sequence of time slots of the incoming bit stream that is relevant to described storage arrangement.
18. as claim 14 or 15 described equipment, wherein said selection reading device comprises generator (10; 55-58; 370), for each described output bit stream be assigned with reception its those time slots from the time slot data of described incoming bit stream, the corresponding sign of described banks of memory devices corresponding time slot data inlet is provided, and wherein said selection reading device is arranged to read from described time slot data inlet according to described sign the time slot data of described time slot.
19., comprise the device (320) that is used to receive additional bit stream and be used to provide the device (10 of sign to the time slot of the frame of at least one bit stream of described output bit stream as claim 14 or 15 described equipment; 55-58; 370), described time slot is assigned with to receive the time slot data from described additional bit stream, described sign is relevant to the described additional bit stream that the time slot data are provided, and wherein said selection reading device is arranged to read from described additional bit stream according to described sign the time slot data of described time slot.
20. as claim 14 or 15 described equipment, wherein be used to provide the described device of sign to be arranged to offer sign of each time slot of each described output bit stream one frame, whether the described time slot of this sign appointment receives the time slot data from any one described incoming bit stream, if like this, read described time slot data from which time slot item of described banks of memory devices.
21., comprise that being used to store a group id upgrades and be used to store about when using described identification renewal to upgrade the device (430) of the relevant timing information (420) of described sign as claim 14 or 15 described equipment; And use described identification renewal group to upgrade the device of described sign (410) in the time of described relevant timing information appointment.
22. as claim 14 or 15 described equipment, comprise being used for detecting every corresponding one frame synchronizing signal of described incoming bit stream and the described device (210) that temporarily stores the respective stored apparatus of described banks of memory devices into that is used for coming synchronization frame according to described frame synchronizing signal.
23., comprise being used for determining the frame synchronization of each corresponding described output bit stream and being used for synchronous in view of the above from described banks of memory devices reading selectively and they devices (330) to the time slot data to the transmission of corresponding output bit stream as claim 14 or 15 described equipment.
24. as claim 14 or 15 described equipment, wherein each described storage arrangement comprises three frame memory area territories (31a-31c, 32a-32c, 33a-33c, 34a-34c; 300a-300c), be used for storing sequentially and provisionally three sequence frames of corresponding incoming bit stream.
25. equipment as claimed in claim 24 comprises writing indicator device (100; 250),, specify which frame memory area territory of described banks of memory devices to be used to store the current frame that writes described banks of memory devices from described incoming bit stream at each of some preset time.
26. equipment as claimed in claim 24 comprises reading pointer device (100; 380), each preset time point specify selectively reading of the current time slot data that are used for described output bit stream in which frame memory area territory of described banks of memory devices.
27., comprise instantaneous offset assembly (18 as claim 14 or 15 described equipment; 104), for the time slot of described output bit stream, the appointment that instantaneous skew is provided by described reading pointer device, so that read the time slot data of described time slot from another frame memory area territory, rather than by that of the default appointment of described reading pointer device.
28. as claim 14 or 15 described equipment, wherein said storage arrangement comprises a random asccess memory with a plurality of read ports.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SE97040679 | 1997-11-06 | ||
| SE9704067A SE513518C2 (en) | 1997-11-06 | 1997-11-06 | Data switching apparatus for switching bit-streams between input and output in time division multiplexing |
| US6647797P | 1997-11-26 | 1997-11-26 | |
| US60/066,477 | 1997-11-26 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1283379A CN1283379A (en) | 2001-02-07 |
| CN1127280C true CN1127280C (en) | 2003-11-05 |
Family
ID=26663120
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN98812747A Expired - Lifetime CN1127280C (en) | 1997-11-06 | 1998-11-05 | Method and apparatus for switching data between bitstreams of time division multiplexed network |
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| Country | Link |
|---|---|
| US (1) | US6430180B1 (en) |
| EP (1) | EP1038376A2 (en) |
| JP (1) | JP2001523069A (en) |
| KR (1) | KR20010052097A (en) |
| CN (1) | CN1127280C (en) |
| AU (1) | AU1182599A (en) |
| BR (1) | BR9813190A (en) |
| WO (1) | WO1999025099A2 (en) |
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| US4005272A (en) * | 1974-08-14 | 1977-01-25 | Arthur A. Collins, Inc. | Time folded TST (time space time) switch |
| FR2538976A1 (en) * | 1982-12-29 | 1984-07-06 | Servel Michel | SYSTEM FOR SWITCHING SYNCHRONOUS PACKETS OF FIXED LENGTH |
| US4809261A (en) * | 1987-07-10 | 1989-02-28 | Solid State Systems, Inc. | Space and time switch for 22 PCM highways |
| US5128929A (en) * | 1988-11-15 | 1992-07-07 | Nec Corporation | Time division switching system capable of broad band communications service |
| US5323390A (en) * | 1992-10-20 | 1994-06-21 | At&T Bell Laboratories | Multirate, sonet-ready, switching arrangement |
| US5619503A (en) * | 1994-01-11 | 1997-04-08 | Ericsson Inc. | Cellular/satellite communications system with improved frequency re-use |
| US5619563A (en) * | 1994-12-19 | 1997-04-08 | Lucent Technologies Inc. | Mnemonic number dialing plan |
-
1998
- 1998-11-05 CN CN98812747A patent/CN1127280C/en not_active Expired - Lifetime
- 1998-11-05 WO PCT/SE1998/002003 patent/WO1999025099A2/en not_active Application Discontinuation
- 1998-11-05 EP EP98954893A patent/EP1038376A2/en not_active Withdrawn
- 1998-11-05 BR BR9813190-7A patent/BR9813190A/en not_active Application Discontinuation
- 1998-11-05 JP JP2000519980A patent/JP2001523069A/en not_active Withdrawn
- 1998-11-05 KR KR1020007004934A patent/KR20010052097A/en not_active Application Discontinuation
- 1998-11-05 AU AU11825/99A patent/AU1182599A/en not_active Abandoned
-
2000
- 2000-05-04 US US09/565,205 patent/US6430180B1/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| AU1182599A (en) | 1999-05-31 |
| KR20010052097A (en) | 2001-06-25 |
| US6430180B1 (en) | 2002-08-06 |
| EP1038376A2 (en) | 2000-09-27 |
| WO1999025099A3 (en) | 1999-08-05 |
| CN1283379A (en) | 2001-02-07 |
| JP2001523069A (en) | 2001-11-20 |
| WO1999025099A2 (en) | 1999-05-20 |
| BR9813190A (en) | 2000-08-22 |
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