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CN112713090B - Preparation method of QFN device and QFN device - Google Patents

Preparation method of QFN device and QFN device Download PDF

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Publication number
CN112713090B
CN112713090B CN201911019801.1A CN201911019801A CN112713090B CN 112713090 B CN112713090 B CN 112713090B CN 201911019801 A CN201911019801 A CN 201911019801A CN 112713090 B CN112713090 B CN 112713090B
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Prior art keywords
chip
pin
pins
hole
qfn device
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CN201911019801.1A
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CN112713090A (en
Inventor
马浩华
敖利波
史波
曹俊
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Gree Electric Appliances Inc of Zhuhai
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Gree Electric Appliances Inc of Zhuhai
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49517—Additional leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The invention provides a preparation method of a QFN device and the QFN device, wherein the QFN device comprises a chip substrate, the chip substrate comprises at least one first pin, a plurality of second pins surrounding the first pin, and a plurality of first holes which are arranged around all the second pins and are connected with the second pins one by one; the chip is assembled in the chip substrate area, covers and is communicated with the first pin, and is connected with the second pin through a bonding wire; the plastic packaging body is used for plastically packaging the chip on the chip substrate and exposing the first pin and the second pin; the flat tin layer is formed on the bottom surface of the first pin, the bent tin layers are formed on the second pin one by one, and each bent tin layer comprises a bottom area covering the bottom surface of the second pin and a side area covering the side surface, located in the first hole, of the second pin. The side surface of the pin of the QFN device is electroplated with the tin layer, so that the welding strength of the device and a PCB (printed circuit board) is improved, and the reliability of the device is improved.

Description

Preparation method of QFN device and QFN device
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a preparation method of a QFN device and the QFN device.
Background
With the miniaturization demand of electronic components, the application of small flat quad flat no-lead (QFN) devices is wider and wider; QFN devices have many advantages, such as low cost of the device, ability to provide excellent electrical performance, etc.; however, in QFN, all leads are surrounded by epoxy after the device is injection molded.
As shown in fig. 1, the QFN device includes a die pad 02, a die 04 is fixed on the die pad 02 by solder 03, and external terminals of the die 04 are connected to leads 01 located on the periphery of the bottom of the QFN device by bonding wires 05. In order to protect the chip 04, the bonding wire 05 and the like from corrosion, oxidation and the like, the plastic package body 06 is used for plastic packaging of the device, only the pin 01 and the chip base 02 are exposed, and for convenience of welding, a part of the pin 01 is exposed from the side surface of the QFN device, and forms a smooth surface with the plastic package body 06 on the side surface of the QFN device, and a tin layer is only electroplated on the surface of the exposed package shell 06 during electroplating, so that the tin layer 07 is not plated on the side surface of the pin 01, and as the tin layer is not formed on the side surface of the pin 01, the welding between the pin 01 and a PCB is not firm easily caused during terminal application, and the device is loosened from the PCB so as to cause electrical connection failure.
Disclosure of Invention
In order to solve the technical problems, the invention provides a method for manufacturing a QFN device, wherein tin is plated on the side face of a pin of the QFN device, so that the welding strength of the device and a PCB (printed circuit board) is improved, and the reliability is improved.
In a first aspect of the present invention, a method for manufacturing a QFN device is provided, including:
preparing a substrate, wherein the substrate comprises at least one chip base area, the chip base area comprises at least one first pin, a plurality of second pins arranged around the first pin and a plurality of first holes arranged around all the second pins and connected with the second pins one by one;
assembling a chip in the chip substrate area, enabling the chip to cover and be communicated with the first pin, and then connecting the chip with the second pin through a bonding wire;
plugging the first hole by a plugging piece, then plastically packaging the chip on the chip substrate area, and removing the plugging piece;
performing tin plating treatment on the chip substrate area to form a flat tin layer on the bottom surfaces of the first pins and simultaneously form bent tin layers on each second pin, wherein each bent tin layer comprises a bottom area covering the bottom surfaces of the second pins and a side area covering the second pins and located in the first holes;
and cutting the chip substrate area and ensuring that a cutting track is tangent to or close to the side area of the bent tin layer.
Herein, the term "closely adjacent" means that the interval between adjacent parts is 0.05 to 1mm.
Further, plugging the first hole by a plugging member, then plastically packaging the chip on the chip substrate region and removing the plugging member, including: the substrate, the chip and the bonding wire are accommodated by the spliced upper die and the lower die, a plugging piece formed on the lower die is forced to plug the first hole, molten plastic packaging material is injected into the upper die and the lower die, the chip is packaged on the chip substrate area through a packaging shell formed by the solidified plastic packaging material after the molten plastic packaging material is solidified, and then the upper die and the lower die are removed and the plugging piece is forced to be separated from the first hole.
Further, the blocking piece is a protrusion on the surface of the lower die and is integrally formed with the lower die.
Further, the cross sections of the protrusion and the first hole are the same and are rectangular, and one side of the rectangle is formed on the second pin.
Further, the first hole is a through hole.
Further, the die is attached to the die pad area by soldering or adhesive means.
Further, a second hole which is arranged between the first pin and the second pin and can receive packaging materials is further arranged in the chip substrate area.
Further, the QFN device is a CPU or a GPU.
The invention provides a QFN device, which comprises a chip substrate, a first lead, a plurality of second leads and a plurality of openings, wherein the chip substrate comprises a first lead, a plurality of second leads surrounding the first lead, and the openings are arranged around all the second leads and are connected with the second leads one by one;
the chip is assembled in the chip substrate area, covers and is communicated with the first lead, and is connected with the second lead through a bonding wire;
the plastic packaging body is used for plastically packaging the chip on the chip substrate and exposing the first pin and the second pin;
the flat tin layer is formed on the bottom surface of the first pin, the bent tin layers are formed on the second pin one by one, and each bent tin layer comprises a bottom area covering the bottom surface of the second pin and a side area covering the side surface, located in the opening, of the second pin.
Further, the shape of the opening is a rectangle, and one side of the rectangle is formed on the second pin.
Compared with the prior art, the second pin side of the QFN device is electroplated with the tin layer, so that the welding strength of the device and a PCB is improved, and the reliability of the device is improved.
The above-described technical features can be combined in various technically feasible ways to produce new embodiments, as long as the object of the invention is achieved.
Drawings
The invention will be described in more detail hereinafter on the basis of non-limiting examples only and with reference to the accompanying drawings. Wherein:
fig. 1 shows a schematic structure of a QFN device in the prior art;
FIG. 2 is a schematic diagram showing the structure of a QFN device in an embodiment of the invention;
FIG. 3 is a schematic structural diagram of a substrate in an embodiment of the method for manufacturing a QFN device of the present invention;
FIG. 4 is a schematic diagram showing the substrate and the injection molding lower mold in an embodiment of the method for manufacturing a QFN device of the present invention;
FIG. 5 shows a schematic structural diagram of an injection molded QFN device in an embodiment of the method for manufacturing the QFN device;
FIG. 6 shows a schematic structural diagram after tin plating in an embodiment of a QFN device preparation method of the invention;
fig. 7 shows a schematic structural diagram of the QFN device formed after cutting along the dotted line in fig. 6.
In the drawings, like components are denoted by like reference numerals. The figures are not drawn to scale.
Wherein the reference numerals are:
01. a pin; 02. a chip base; 03. welding flux; 04. a chip; 05. a bonding wire; 06. packaging the shell; 07. A tin layer; 100. a QFN device; 1. a substrate; 2. a chip substrate; 21. a first pin; 22. a second pin; 3. welding flux; 4. a chip; 5. a bonding wire; 6. molding the body; 7. a flat tin layer; 8. bending the tin layer; 9. a first hole; 10. a blocking member; 11. a lower die; 12. an opening; 13. a second aperture.
Detailed Description
The invention will be described in further detail below with reference to the drawings and specific examples. It should be noted that, as long as there is no conflict, the embodiments and the features in the embodiments of the present invention may be combined with each other, and the technical solutions formed are within the scope of the present invention.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The terms "first," "second," and the like, as used herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalent, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.
In the description of the present invention, the terms "upper", "lower", "top", "bottom", "inner", "outer", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and when the absolute position of the described object is changed, the relative positional relationships may be changed accordingly, and thus, are not to be construed as limiting the present invention.
Parts which are not described in the invention can be realized by adopting or referring to the prior art.
The first aspect of the invention provides a method for preparing a QFN device, which comprises the following steps:
step S101, preparing a substrate 1,
referring to fig. 3, the substrate 1 includes at least one chip substrate region, which includes a first lead 21 and a plurality of second leads 22 arranged around the first lead 21, and a plurality of first holes 9 arranged around all the second leads 22 and connected to each of the second leads 22 one by one;
step S102, assembling a chip 4 in the chip base area and enabling the chip 4 to cover and communicate with the first pins 21, and then connecting the chip 4 with second pins 22 through bonding wires 5;
step S103,
Referring to fig. 4-5, the first hole 9 is sealed by a sealing member 10, and then the chip 4 is plastically packaged on the first pin 21 of the chip substrate region and the sealing member 10 is removed;
step S104, carrying out tin plating treatment on the chip substrate area to form a flat tin layer 7 on the bottom surface of the first pin 21 and simultaneously form a bent tin layer 8 on each second pin 22, wherein each bent tin layer comprises a bottom area covering the bottom surface of the second pin 22 and a side area covering the second pin 22 and positioned in the first hole 9; the tin plating results are shown in FIG. 6.
Step S105, cutting the substrate region of the chip and ensuring that the cutting track is tangent to or in close proximity to the side region of the bent tin layer 8, so as to form the complete QFN device 100 as shown in fig. 2 or fig. 7.
According to the manufacturing method, the first hole is formed in the position where the pin is connected with the pin, and the first hole is sealed before plastic package, so that plastic package materials (such as epoxy resin) can be prevented from being injected into the first hole, the bottom surface and the side surface of the second pin can be guaranteed to form a bent tin layer in the tinning process, a large-area tin layer can be reserved on the side surface of the second pin after the product is cut, the welding strength of a device and a PCB (printed circuit board) during welding is improved, and the reliability of the device is improved.
Further, in step S103, the first hole 9 is sealed by the sealing member 10, and then the chip 4 is plastically packaged on the chip substrate region 2 and the sealing member 10 is removed, which specifically includes:
step S1031, accommodating the substrate 1, the chip 4 and the bonding wires 5 by a spliced upper die (not shown in the figure) and a lower die, forcing a blocking piece 10 formed on the lower die 11 to block the first hole 9;
step S1032, injecting molten plastic packaging material into the upper mold and the lower mold 11, and after the molten plastic packaging material is solidified, packaging the chip 4 on the chip substrate region through a plastic packaging body 6 formed by solidifying the plastic packaging material;
step S033, removes the upper and lower molds 11 and forces the block piece 10 out of the first hole 9.
In an alternative embodiment, the blocking element 10 may be a block that fits into the first hole 9.
In an alternative embodiment, the blocking element 10 is a protrusion of the surface of the lower mold 11 and is integrally formed with the lower mold 11.
Preferably, the cross section of the protrusion 12 and the cross section of the first hole 9 are the same, and both are rectangular, and one side of the rectangle is formed on the second pin 22.
In an alternative embodiment, the depth of the first hole 9 is greater than or equal to the thickness of the second pin 22 when the lateral surface is not plated with tin, and is less than or equal to the thickness of the lateral surface of the device 1. Therefore, the tightness of the chip 4 and the bonding wire 5 can be ensured, the tin layer with enough area can be reserved on the side surface of the second pin 22, and the stability of the device during welding with a PCB (printed circuit board) is ensured.
Preferably, the first hole 9 is a through hole to reduce the manufacturing difficulty and improve the production efficiency.
Preferably, the depth of the first hole 9 is equal to the thickness of the second pin 22 when the side is not plated with tin.
Moreover, while the operations of the invention are described in a particular order, this does not imply or imply that the operations must be performed in that particular order, or that all of the illustrated operations must be performed, to achieve desirable results. Certain steps may be omitted, multiple steps combined into one step or one step performed as multiple steps. For example, in an actual manufacturing process, the order of mounting the chip in the chip substrate region in step S102 and connecting the chip to the second leads 22 and covering and communicating the first leads may be interchanged with the order of sealing the first holes 9 in step S103, the first holes 9 are sealed first, and then the steps of mounting the chip 4 in the chip substrate region and connecting the chip 4 to the second leads 22 and covering and communicating the first holes 21 and connecting the chip 4 to the second leads 22 through the bonding wires 5 are performed.
Preferably, the chip 4 is connected to the chip pad area, i.e. the first pin, by soldering or adhesive means.
In an alternative embodiment, the chip substrate region further includes a second hole 13 disposed between the first lead 21 and the second lead 22 and capable of receiving the packaging material. The second hole 13 contributes to improvement of connection stability of the package.
In a preferred embodiment, the QFN device may be selected as a CPU or GPU, etc.
A second aspect of the invention provides a QFN device prepared by the method provided in the first aspect of the invention, as shown in fig. 2, and in one embodiment, QFN device 100 of the invention comprises
The chip comprises a chip substrate 2, wherein the chip substrate 2 comprises at least one first pin 21 and a plurality of second pins 22 surrounding the first pin 21, and a plurality of openings 12 arranged around all the second pins 22 and connected with one of the second pins 22; the opening 12 is part of the first hole 9 on the substrate.
The chip substrate 2 is internally provided with a chip 4 which covers and is communicated with the first pin 21 and is connected with the second pin 22 through a bonding wire 5;
a molding body 6 for molding the chip 4 on the chip substrate 2 and exposing the first and second pins 21 and 22;
the flat tin layer 7 is formed on the bottom surface of the first pin 21, the bent tin layers 8 are formed on the second pin 22 one by one, and each bent tin layer 8 comprises a bottom area covering the bottom surface of the second pin 11 and a side area covering the side surface, located in the opening 12, of the second pin 22.
The side surface of the second pin of the QFN device is electroplated with the tin layer, so that the welding strength of the device and a PCB (printed circuit board) is improved, and the reliability of the device is improved.
In an alternative embodiment, the opening 12 is rectangular in shape, with one side of the rectangle formed on the second leg 22.
As shown in fig. 1, since the opening 12 is formed along the side surface of the second lead 22, the tin layer (i.e., the folded tin layer 8) plated on the inner wall of the opening 12 is formed on the side surface of the second lead 221. Therefore, the tin layer is electroplated on the side surface of the second pin 22, so that the welding strength of the device and the PCB is improved, and the reliability of the device is improved.
In an alternative embodiment, the depth of the opening 12 is greater than or equal to the thickness of the second lead 22 when the sides are not soldered, and is less than the thickness of the sides of the device 1.
In a normal situation, the first leads 21 and the second leads 22 are disposed on the periphery of the chip substrate 2, and at this time, the openings 12 are required to be disposed on the bottoms of the four sides of the QFN device; this is not absolute, however, and if the second leads 22 are provided only on the bottom of certain sides of the QFN device, the openings 12 may be provided only on the bottom of these sides.
Preferably, the molding material forming the molded body 6 is epoxy resin.
In an alternative embodiment, the chip 4 is fixed to the chip base 2 by means of solder 3 or a chip material.
It will thus be appreciated by those skilled in the art that while the invention has been described with reference to a preferred embodiment, various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In particular, the technical features mentioned in the embodiments can be combined in any way as long as there is no structural conflict. It is intended that the invention not be limited to the particular embodiments disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims (7)

1. A method for manufacturing a QFN device is characterized by comprising the following steps:
preparing a substrate, wherein the substrate comprises at least one chip base area, the chip base area comprises at least one first pin, a plurality of second pins arranged around the first pin and a plurality of first holes arranged around all the second pins and connected with the second pins one by one;
assembling a chip in the chip base area, enabling the chip to cover and be communicated with the first pins, and then connecting the chip with the second pins through bonding wires;
plugging the first hole by a plugging piece, then plastically packaging the chip on the chip substrate area, and removing the plugging piece;
performing tin plating treatment on the chip substrate area to form a flat tin layer on the bottom surfaces of the first pins and simultaneously form bent tin layers on each second pin, wherein each bent tin layer comprises a bottom area covering the bottom surfaces of the second pins and a side area covering the second pins and located in the first holes;
cutting the chip substrate area and ensuring that a cutting track is tangent to or close to the side area of the bent tin layer;
wherein, block through a blocking piece to the first hole, then with the chip plastic envelope in the chip base district on and remove the blocking piece, specifically include: the substrate, the chip and the bonding wire are accommodated by an upper die and a lower die which are spliced together, a plugging piece formed on the lower die is forced to plug the first hole, molten plastic packaging material is injected into the upper die and the lower die, the chip is packaged on the chip substrate area through a plastic packaging body formed by solidifying the plastic packaging material after the molten plastic packaging material is solidified, and then the upper die and the lower die are removed and the plugging piece is forced to be separated from the first hole.
2. The method for manufacturing QFN device according to claim 1, wherein the blocking piece is a protrusion of the lower mold surface and is integrally molded with the lower mold.
3. The method for manufacturing a QFN device according to claim 2, wherein the protrusion and the first hole have the same cross section and are both rectangular, and one side of the rectangle is formed on the second lead.
4. The method for manufacturing QFN device according to claim 2, wherein the first hole is a through hole.
5. Method for producing a QFN device according to any one of claims 1 to 3, wherein the die is attached to the die pad area by soldering or adhesive means.
6. The method for manufacturing a QFN device according to any one of claims 1 to 3, wherein the chip substrate region further comprises a second hole disposed between the first lead and the second lead and capable of receiving an encapsulation material.
7. The method for manufacturing QFN device according to any one of claims 1 to 3, wherein the QFN device is a CPU or a GPU.
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