CN112685344B - DMA programming circuit and programming method based on same - Google Patents
DMA programming circuit and programming method based on same Download PDFInfo
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Abstract
The invention discloses a DMA programming circuit and a programming method based on the same, wherein the DMA programming circuit mainly comprises the following steps: a DMA interface, a data multiplexer and a control multiplexer; the DMA interface is used for acquiring a DMA control signal, and a second data channel is arranged between the DMA interface and the Flash controller; the control multiplexer is used for selecting the DMA control signal and the processor control signal; the data multiplexer is used for selecting and gating the first data channel and the second data channel; the Flash controller is used for writing programming data from the DMA interface into the Flash memory according to the DMA control signal and the second data channel, or writing programming data from the CPU interface into the Flash memory according to the processor control signal and the first data channel. The technical scheme of the invention can release the processor resource and improve the performance of the processor during programming control.
Description
Technical Field
The present invention relates to the field of data processing technologies, and in particular, to a DMA programming circuit and a programming method based on the DMA programming circuit.
Background
At present, a flash memory capable of being rewritten is usually integrated in the SoC/MCU chip for storing programs and data. When data is read from the flash memory, a flash address and a control signal need to be given, and the data is directly read from the flash memory. When writing data or programming data into the flash memory, the mode and the read data are greatly different. Before writing data, a string of control timing is required for the flash memory, and then the data is written. In this process, the control timing of the flash is generated by the execution of software by the processor. Therefore, the processor is required to participate in writing data to or programming the flash memory. However, when the processor participates in writing data, the CPU resources are occupied, and the application program can only be stopped, and other application programs cannot be executed continuously, so that performance loss is caused.
In view of this, there is a need for further improvements in the programming techniques of current flash memories.
Disclosure of Invention
In order to solve at least one of the above problems, a main object of the present invention is to provide a DMA programming circuit and a programming method based on the DMA programming circuit.
In order to achieve the above object, the first technical scheme adopted by the present invention is as follows: there is provided a Direct Memory Access (DMA) programming circuit comprising: the CPU interface is used for acquiring a control signal of the processor, a first data channel is arranged between the CPU interface and the Flash controller, and the DMA programming circuit further comprises: a DMA interface, a data multiplexer and a control multiplexer;
the DMA interface is used for acquiring a DMA control signal, and a second data channel is arranged between the DMA interface and the Flash controller;
The control multiplexer is used for selecting the DMA control signal and the processor control signal;
The data multiplexer is used for selecting and gating the first data channel and the second data channel;
The Flash controller is configured to write programming data from the DMA interface into the Flash memory according to the DMA control signal and the second data channel, or write programming data from the CPU interface into the Flash memory according to the processor control signal and the first data channel.
And the Flash controller is further configured to verify the DMA control signal, and when the verification result of the DMA control signal is correct, control the DMA interface to obtain the programming data and write the programming data into the Flash memory through the second data channel.
The first input end of the data multiplexer is electrically connected with the CPU interface through the first data channel, the second input end of the data multiplexer is electrically connected with the DMA interface through the second data channel, the output end of the data multiplexer is electrically connected with the Flash controller, and the data multiplexer is used for connecting one of the first input end and the second input end with the output end so as to select one of the first data channel and the second data channel.
The first input end of the control multiplexer is electrically connected with the CPU interface, the second input end of the control multiplexer is electrically connected with the DMA interface, the output end of the control multiplexer is electrically connected with the Flash controller, and the control multiplexer is used for connecting one of the first input end and the second input end with the output end so as to selectively output the DMA control signal and the processor control signal.
The DMA interface is provided with a feedback end, the feedback end is connected with the Flash controller and is used for receiving programming state feedback information sent by the Flash controller, and the DMA interface is also used for controlling the data flow of the programming data according to the programming state feedback information.
The DMA programming circuit further comprises a DMA controller, wherein the output end of the DMA controller is connected with the DMA interface, and the DMA controller is used for carrying the programming data to the DMA interface so that the DMA interface writes the programming data into the Flash memory through the second data channel.
In order to achieve the above object, the second technical scheme adopted by the present invention is as follows: provided is a programming method based on a DMA programming circuit, comprising:
acquiring a DMA control signal and a processor control signal;
selecting the DMA control signal and the processor control signal;
selecting and gating the first data channel and the second data channel;
Programming data from a DMA interface is written into the Flash memory according to the selected DMA control signal and the second data channel, or programming data from a CPU interface is written into the Flash memory according to the selected processor control signal and the first data channel.
Wherein the method further comprises:
checking the DMA control signal;
And when the verification result of the DMA control signal is correct, controlling the DMA interface to acquire programming data.
The DMA control signal comprises DMA data configuration information and DMA data transmission information, and the step of checking the DMA control signal specifically comprises the following steps:
checking the DMA data configuration information;
And when the verification result of the DMA control signal is correct, controlling the DMA interface to acquire the programming data, wherein the method specifically comprises the following steps:
when the verification result of the DMA data configuration information is correct, feeding back DMA data transmission information corresponding to the DMA data configuration information to the DMA interface;
and controlling the DMA interface to acquire the programming data according to the DMA data transmission information.
Wherein the DMA data transfer information includes a transfer length value, and the acquiring the programming data according to the DMA data transfer information includes:
And carrying the programming data with the corresponding length to the DMA interface successively according to the transmission length value.
After the DMA control signal is checked, the method further includes:
And when the check result of the DMA control signal is an error, controlling the DMA interface to stop acquiring the programming data and outputting an interrupt signal, wherein the interrupt signal is used for informing an external processor to write the programming data into the Flash memory through the CPU interface and the first data channel.
Wherein the writing programming data from the DMA interface into the Flash memory according to the selected DMA control signal and the second data channel further comprises:
setting the DMA data configuration information as a first data block, setting a source address of the first data block according to a storage position of the DMA data configuration information, and setting a target address of the first data block as the Flash controller;
setting the programming data as a second data block, setting a source address of the second data block according to a storage position of the programming data, and setting a target address of the second data block as the Flash memory;
and respectively transmitting the first data block and the second data block in a block transmission mode according to the source address and the target address of the first data block and the second data block.
The technical scheme of the invention mainly comprises a CPU interface, a DMA interface, a data multiplexer, a control multiplexer, a Flash controller and a Flash memory, wherein the CPU interface is used for acquiring a processor control signal and the DMA interface is used for acquiring a DMA control signal, the control multiplexer is used for selectively outputting the two control signals to the Flash controller, the CPU interface is controlled to acquire programming data or the DMA control signal is controlled to acquire the programming data according to the processor control signal, the programming data acquired by the DMA interface is gated by a second data channel and written into the Flash memory, and the programming data acquired by the CPU interface is gated by a first data channel and written into the Flash memory, so that when an external processor is occupied, the CPU interface cannot write the programming data, the programming data can be written into through the DMA interface, so that the resources of the processor are released, and the performance of the processor is improved. In addition, the scheme also keeps a CPU interface capable of writing programming data, and can improve the reliability of programming data writing.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of a DMA programming circuit according to an embodiment of the present invention;
FIG. 2 is a block diagram of a DMA programming circuit according to another embodiment of the present invention;
FIG. 3 is a flowchart of a programming method of a DMA programming circuit according to an embodiment of the present invention;
fig. 4 is a block diagram of an electronic device according to an embodiment of the present invention.
The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that the description of "first," "second," etc. in this disclosure is for descriptive purposes only and is not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present invention.
The invention provides a direct memory access DMA programming circuit which aims at writing programming data through a DMA interface without writing the programming data through a CPU interface, so that the resources of the CPU can be released, and the performance of the processor is improved. The DMA programming circuit is referred to the following embodiments, and will not be described herein.
Referring to fig. 1, fig. 1 is a block diagram of a DMA programming circuit according to an embodiment of the invention. In an embodiment of the present invention, the direct memory access DMA programming circuit includes: the CPU interface 110, the Flash controller 150 and the Flash memory 160, wherein the CPU interface 110 is used for obtaining a processor control signal, and a first data channel 101 is arranged between the CPU interface 110 and the Flash controller 150.
The DMA programming circuit further includes: a DMA interface 120, a data multiplexer 130, and a control multiplexer 140; a DMA interface 120, configured to obtain a DMA control signal, where a second data channel 121 is provided between the DMA interface 120 and the Flash controller 150; a control multiplexer 140 for selecting the DMA control signal and the processor control signal; a data multiplexer 130 for selectively gating the first data channel 101 and the second data channel 121; flash controller 150 is configured to write programming data from DMA interface 120 to Flash memory 160 according to the DMA control signal and second data channel 121, or to write programming data from CPU interface 110 to Flash memory 160 according to the processor control signal and first data channel 101.
In this embodiment, the present solution may use the DMA interface 120 or the CPU interface 110 to obtain the programming data, where the DMA interface 120 is used to connect with a DMA controller, and the CPU interface 110 is used to connect with a processor. The processor may be a SoC (System On Chip) or MCU (Micro-Controller Unit) Chip. In some application scenarios, for example, when the processor executes other application programs and is occupied, or when the programming data currently required to be written into Flash memory 160 does not require additional processing by the processor, the programming data may be written into Flash memory 160 by DMA. Specifically, the DMA controller sends DMA control signals to the DMA interface 120. DMA interface 120 obtains the DMA control signal and transmits it to control multiplexer 140, where control multiplexer 140 selects the DMA control signal and transmits it to Flash controller 150.Flash controller 150 writes programming data from DMA interface 120 to Flash memory 160 according to the DMA control signal and second data channel 121. The processor is not needed to participate in the process, which is equivalent to releasing the resources of the processor, and the processor can execute other application programs, so that the performance of the processor can be improved.
In order to improve the reliability of programming data writing, the scheme also maintains a CPU interface 110. In other application scenarios, for example, DMA cannot write programming data, or when programming data currently needed to be written to Flash memory needs to be processed by a processor, programming data may be written to Flash memory 160 by the processor. Specifically, the processor sends a processor control signal to the CPU interface 110. The CPU interface 110 acquires the processor control signal, selects the processor control signal by controlling the multiplexer 140 and transmits the processor control signal to the Flash controller 150, and the Flash controller 150 writes the programming data from the CPU interface 110 into the Flash memory 160 according to the processor control signal and the first data channel 101. The control multiplexer 140 and the data multiplexer 130 can gate the corresponding control signals and data channels to simplify the programming circuit.
In a specific embodiment, the first data channel and the second data channel are both connected to the Flash controller through the data multiplexer 130. Specifically, a first input terminal of the data multiplexer 130 is electrically connected to the CPU interface 110 through the first data channel 101, a second input terminal of the data multiplexer 130 is electrically connected to the DMA interface 120 through the second data channel 121, an output terminal of the data multiplexer 130 is electrically connected to the Flash controller 150, and the data multiplexer 130 is configured to connect the first input terminal and the second input terminal to the output terminal, so as to select one of the first data channel 101 and the second data channel 121.
In this embodiment, the data multiplexer 130 may be a selector, specifically, when the output terminal of the data multiplexer 130 is selectively connected to the first input terminal, the first data channel 101 between the CPU interface 110 and the Flash controller 150 is gated; when the output of the data multiplexer 130 selects to connect to the second input, the second data channel 121 between the DMA interface 120 and the Flash controller 150 is gated.
In a specific embodiment, a first input terminal of the control multiplexer 140 is electrically connected to the CPU interface 110, a second input terminal of the control multiplexer 140 is electrically connected to the DMA interface 120, an output terminal of the control multiplexer 140 is electrically connected to the Flash controller 150, and the control multiplexer 140 is used for selectively connecting the first input terminal and the second input terminal to the output terminal, so as to selectively output the DMA control signal and the processor control signal.
In this embodiment, the control multiplexer 140 may also select one of two selectors, specifically, when the output terminal of the control multiplexer 140 is selectively connected to the first input terminal, the processor control signal written from the CPU interface 110 is selected; when the output of control multiplexer 140 selects to connect to the second input, the DMA control signal written from DMA interface 120 is selected.
In a specific embodiment, the Flash controller 150 is further configured to verify the DMA control signal, and when the verification result of the DMA control signal is correct, control the DMA interface 120 to obtain the programming data and write the programming data into the Flash memory 160 through the second data channel 121; when the check result of the DMA control signal is an error, the DMA interface 120 is controlled to stop acquiring the program data and output an interrupt signal.
Further, the DMA interface 120 has a feedback end, and the feedback end is connected to the Flash controller 150 and is configured to receive the programming status feedback information sent by the Flash controller 150, and the DMA interface 120 is further configured to control a data stream of the programming data according to the programming status feedback information.
In this embodiment, the DMA interface 120 has a feedback end for receiving the programming status feedback information sent by the verification result of the DMA control signal, specifically, after the Flash controller 150 writes the programming data into the Flash memory 160, the programming status feedback information can be generated. The program state feedback information is used to feedback the current program state of Flash memory 160 to the DMA controller or external processor, where the program state may include a program mode (DMA program or CPU program) state, a program result (normal or abnormal) state, and the like. The DMA interface 120 receives the programming status feedback information through the feedback terminal to determine whether the current programming status of the Flash memory is normal, thereby controlling the data flow of the programming data according to the programming status feedback information. For example, when the programming status is DMA programming and the programming result is normal, the DMA interface 120 may be controlled to continue to acquire the programming data stream and continue to send the programming data stream through the second data channel 121. In one embodiment, when the program status is confirmed to be DMA programming and the programming result is normal, the DMA interface 120 may output a confirmation message to the DMA controller, so that the DMA controller continues to acquire the program data stream according to the confirmation message. Alternatively, the acknowledgement information may be an ACK (Acknowledge character, acknowledgement character) or other preset information for indicating the programming status.
The CPU interface 110 also has a feedback end, which is connected to the Flash controller 150 and is configured to receive the programming status feedback information sent by the Flash controller 150. The CPU interface 110 receives the programming status feedback information through the feedback terminal to determine whether the current programming status of the Flash memory 160 is normal, thereby controlling the data flow of the programming data according to the programming status feedback information. For example, when the programming status is DMA programming and the programming result is abnormal, the CPU interface 110 may be controlled to acquire the programming data stream and continue to transmit the programming data stream through the first data channel 101. In one embodiment, when the check result of the DMA control signal is an error, the CPU interface 110 may output an interrupt signal to the processor to notify the processor to acquire the programming data stream according to the interrupt signal.
Referring to fig. 2, fig. 2 is a block diagram of a DMA programming circuit according to another embodiment of the present invention. Specifically, the DMA programming circuit further includes a DMA controller 170, an output of the DMA controller 170 is connected to the DMA interface 120, and the DMA controller 170 is configured to carry programming data to the DMA interface 120, so that the DMA interface writes the programming data to the Flash memory 160 through the second data channel 121. External programming data may be carried to the DMA interface by DMA controller 170, which in turn writes the programming data to Flash memory 160 via second data channel 121.
Referring to fig. 3, fig. 3 is a flowchart of a programming method of a DMA programming circuit according to an embodiment of the invention. In an embodiment of the present invention, the programming method based on the DMA programming circuit includes the steps of: s110, acquiring a DMA control signal and a processor control signal; s120, selecting a DMA control signal and a processor control signal; s130, selecting one of the first data channel and the second data channel; and S140, programming data from the DMA interface is written into the Flash memory according to the selected DMA control signal and the second data channel, or programming data from the CPU interface is written into the Flash memory according to the selected processor control signal and the first data channel.
In some application scenarios, for example, when the processor executes other application programs and is occupied, or when the programming data currently required to be written into the Flash memory does not need additional processing by the CPU, the programming data can be written into the Flash memory in a DMA mode. Specifically, a DMA control signal is obtained through a DMA interface, then the DMA control signal is selected through a control multiplexer, and the Flash controller writes programming data from the DMA interface into the Flash memory according to the DMA control signal and the second data channel. The whole programming data writing process does not need the participation of a processor, and is equivalent to releasing the resources of the processor. In other application scenarios, for example, the DMA cannot write programming data, or when programming data currently required to be written into the Flash memory needs to be processed by the processor, the programming data may be written into the Flash memory by the processor. Specifically, the processor sends a processor control signal to the CPU interface. The CPU interface acquires a processor control signal and selects the processor control signal through the control multiplexer, and the Flash controller writes programming data from the CPU interface into the Flash memory according to the processor control signal and the first data channel.
In a specific embodiment, the method further comprises: checking the DMA control signal; when the verification result of the DMA control signal is correct, controlling the DMA interface to acquire programming data; when the check result of the DMA control signal is error, controlling the DMA interface to stop acquiring programming data and outputting an interrupt signal, wherein the interrupt signal is used for informing an external processor to write the programming data into the Flash memory through the CPU interface and the first data channel.
In this embodiment, the Flash controller may be used to verify the acquired DMA control signal, and control the programming data to be written into the Flash memory according to the verification result. Specifically, when the verification result of the DMA control signal is correct, the Flash controller controls the DMA interface to continuously acquire programming data, and writes the programming data into the Flash memory through the second data channel. When the check result of the DMA control signal is an error, the Flash controller controls the DMA interface to stop acquiring programming data and output an interrupt signal, and after the interrupt signal is transmitted to the processor, the processor writes the programming data into the Flash memory through the CPU interface and the first data channel according to the interrupt signal.
Further, the DMA control signal includes DMA data configuration information and DMA data transmission information, and the step of checking the DMA control signal specifically includes: and checking the DMA data configuration information.
When the verification result of the DMA control signal is correct, controlling the DMA interface to acquire programming data specifically comprises: when the verification result of the DMA data configuration information is correct, feeding back DMA data transmission information corresponding to the DMA data configuration information to the DMA interface; and controlling the DMA interface to acquire programming data according to the DMA data transmission information.
In this embodiment, when the verification result of the DMA data configuration information by the Flash controller is correct, it is indicated that programming data corresponding to the DMA data configuration information exists outside at this time, so that the Flash controller feeds back the verification result to the DMA interface, and controls the DMA interface to continuously acquire the programming data according to the DMA data transmission information, and writes the programming data into the Flash memory through the second data channel. When the verification result of the DMA data configuration information is an error, the DMA is not capable of writing programming data, the Flash controller controls the DMA interface to stop acquiring the programming data and output an interrupt signal, and after the interrupt signal is transmitted to the processor, the processor writes the programming data into the Flash memory through the CPU interface and the first data channel according to the interrupt signal.
Further, the DMA data transfer information includes a transfer length value, and the acquiring programming data according to the DMA data transfer information includes: and carrying programming data with corresponding length to the DMA interface successively according to the transmission length value.
In this embodiment, the transmission length value may be set according to specific requirements, the whole programming data may be divided into a plurality of data segments with transmission lengths, and during the data transmission, the DMA interface may acquire the data segments one by one, and write the plurality of data segments into the Flash memory sequentially through the second data channel.
In a specific embodiment, programming data from the DMA interface is written to the Flash memory according to the selected DMA control signal and the second data channel, further comprising: setting DMA data configuration information as a first data block, setting a source address of the first data block according to a storage position of the DMA data configuration information, and setting a target address of the first data block as a Flash controller; setting programming data as a second data block, setting a source address of the second data block according to a storage position of the programming data, and setting a target address of the second data block as a Flash memory; the first data block and the second data block are transmitted in block transmission according to the source address and the destination address of the first data block and the second data block, respectively.
In this embodiment, when the Flash controller controls the programming data to be written into the Flash memory, the DMA control signal and the programming data need to be configured first. Specifically, the DMA control signal includes DMA data configuration information and DMA data transfer information. The method comprises the steps of configuring the first data block according to DMA data configuration information, setting a source address of the first data block according to a storage position of the DMA data configuration information, and setting a target address of the first data block as a Flash controller, so that when DMA control signals are transmitted, the first data block is transmitted from the source address to the Flash controller in a block transmission mode, and the DMA control signals are transmitted first. And setting the programming data as a second data block, setting a source address of the second data block according to a storage position of the programming data, and setting a target address of the second data block as a Flash memory, so that the second data block is written into a designated position of the Flash memory from the source address in a block transmission mode during programming data transmission, and writing the programming data is realized.
Referring to fig. 4, fig. 4 is a block diagram of an electronic device according to an embodiment of the invention. The electronic device may be used to implement the programming method of the DMA programming circuit in the previous embodiments. As shown in fig. 4, the electronic device mainly includes: memory 301, processor 302, bus 303, and a computer program stored on memory 301 and executable on processor 302, memory 301 and processor 302 being connected by bus 303. When the processor 302 executes the computer program, the programming method based on the DMA programming circuit in the foregoing embodiment is implemented. Wherein the number of processors may be one or more.
The memory 301 may be a high-speed random access memory (RAM, random Access Memory) memory or a non-volatile memory (non-volatile memory), such as a disk memory. The memory 301 is used for storing executable program code, and the processor 302 is coupled to the memory 301.
Further, the embodiment of the present invention further provides a readable storage medium, which may be provided in the electronic device in each of the foregoing embodiments, and the readable storage medium may be a memory in the foregoing embodiment shown in fig. 4.
The readable storage medium has stored thereon a computer program which, when executed by a processor, implements the programming method of the previous embodiment based on a DMA programming circuit. Further, the computer-readable medium may be any medium capable of storing a program code, such as a usb (universal serial bus), a removable hard disk, a Read-Only Memory (ROM), a RAM, a magnetic disk, or an optical disk.
In the several embodiments provided by the present invention, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of modules is merely a logical function division, and there may be additional divisions of actual implementation, e.g., multiple modules or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or modules, which may be in electrical, mechanical, or other forms.
The modules illustrated as separate components may or may not be physically separate, and components shown as modules may or may not be physical modules, i.e., may be located in one place, or may be distributed over a plurality of network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may exist alone physically, or two or more modules may be integrated into one module. The integrated modules may be implemented in hardware or in software functional modules.
The integrated modules, if implemented in the form of software functional modules and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention may be embodied essentially or in part or all of the technical solution or in part in the form of a software product stored in a readable storage medium, including instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods of the embodiments of the present invention. And the aforementioned readable storage medium includes: a usb disk, a removable hard disk, a ROM, a RAM, a magnetic disk, or an optical disk, etc.
It should be noted that, for the sake of simplicity of description, the foregoing method embodiments are all expressed as a series of combinations of actions, but it should be understood by those skilled in the art that the present invention is not limited by the order of actions described, as some steps may be performed in other order or simultaneously in accordance with the present invention. Further, those skilled in the art will appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily all required for the present invention.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments.
The foregoing description is only of the preferred embodiments of the present invention, and is not intended to limit the scope of the invention, and all the structural equivalents of the invention described in the specification and drawings are included in the scope of the invention, or the invention may be directly/indirectly applied to other related technical fields.
Claims (11)
1. A direct memory access, DMA, programming circuit comprising: the DMA programming circuit is characterized by further comprising: a DMA interface, a data multiplexer and a control multiplexer;
the DMA interface is used for acquiring a DMA control signal, and a second data channel is arranged between the DMA interface and the Flash controller;
The control multiplexer is used for selecting the DMA control signal and the processor control signal;
The data multiplexer is used for selecting and gating the first data channel and the second data channel;
The Flash controller is used for writing programming data from the DMA interface into the Flash memory according to the DMA control signal and the second data channel, or writing programming data from the CPU interface into the Flash memory according to the processor control signal and the first data channel;
The DMA interface is provided with a feedback end for receiving programming state feedback information sent by a verification result of a DMA control signal, and the Flash controller generates programming state feedback information for feeding back the current programming state of the Flash memory to the DMA controller or an external processor after writing the programming data into the Flash memory; the programming states include a programming mode state and a programming result state;
And when the programming state is DMA programming and the programming result is normal, the feedback end controls the DMA interface to continuously acquire the programming data stream and continuously send the programming data stream through the second data channel.
2. The DMA programming circuit of claim 1, wherein the Flash controller is further configured to verify the DMA control signal and, when a result of the verification of the DMA control signal is correct, control the DMA interface to obtain the programming data and write the programming data to the Flash memory through the second data channel.
3. The DMA programming circuit of claim 1, wherein a first input terminal of the data multiplexer is electrically connected to the CPU interface via the first data channel, a second input terminal of the data multiplexer is electrically connected to the DMA interface via the second data channel, an output terminal of the data multiplexer is electrically connected to the Flash controller, and the data multiplexer is configured to connect either the first input terminal or the second input terminal to the output terminal to selectively gate the first data channel or the second data channel.
4. The DMA programming circuit of claim 1, wherein a first input terminal of the control multiplexer is electrically connected to the CPU interface, a second input terminal of the control multiplexer is electrically connected to the DMA interface, an output terminal of the control multiplexer is electrically connected to the Flash controller, and the control multiplexer is configured to connect the first input terminal and the second input terminal to the output terminal alternatively to output the DMA control signal and the processor control signal alternatively.
5. The DMA programming circuit of any one of claims 1 to 4, further comprising a DMA controller, an output of the DMA controller coupled to the DMA interface, the DMA controller to handle the programming data to the DMA interface to cause the DMA interface to write the programming data to the Flash memory through the second data channel.
6. A programming method based on a DMA programming circuit, applied to the DMA programming circuit according to any one of claims 1 to 5, characterized in that the programming method comprises:
acquiring a DMA control signal and a processor control signal;
selecting the DMA control signal and the processor control signal;
selecting and gating the first data channel and the second data channel;
Programming data from a DMA interface is written into the Flash memory according to the selected DMA control signal and the second data channel, or programming data from a CPU interface is written into the Flash memory according to the selected processor control signal and the first data channel;
writing the programming data into a Flash memory to generate programming state feedback information for feeding back the current programming state of the Flash memory to the DMA controller or an external processor; the programming states comprise a programming mode state and a programming result state;
And when the programming state is DMA programming and the programming result is normal, the feedback end controls the DMA interface to continuously acquire the programming data stream and continuously send the programming data stream through the second data channel.
7. The programming method of a DMA programming circuit of claim 6, wherein the method further comprises:
checking the DMA control signal;
And when the verification result of the DMA control signal is correct, controlling the DMA interface to acquire programming data.
8. The method for programming a DMA programming circuit according to claim 7, wherein the DMA control signal includes DMA data configuration information and DMA data transfer information, and the step of verifying the DMA control signal specifically includes:
checking the DMA data configuration information;
And when the verification result of the DMA control signal is correct, controlling the DMA interface to acquire the programming data, wherein the method specifically comprises the following steps:
when the verification result of the DMA data configuration information is correct, feeding back DMA data transmission information corresponding to the DMA data configuration information to the DMA interface;
and controlling the DMA interface to acquire the programming data according to the DMA data transmission information.
9. The programming method of the DMA programming circuit according to claim 8, wherein the DMA data transfer information includes a transfer length value, and the acquiring the programming data based on the DMA data transfer information includes:
And carrying the programming data with the corresponding length to the DMA interface successively according to the transmission length value.
10. The programming method of a DMA programming circuit according to claim 7, wherein after the verifying the DMA control signal, the method further comprises:
And when the check result of the DMA control signal is an error, controlling the DMA interface to stop acquiring the programming data and outputting an interrupt signal, wherein the interrupt signal is used for informing an external processor to write the programming data into the Flash memory through the CPU interface and the first data channel.
11. The programming method of the DMA programming circuit of claim 8, wherein the writing programming data from a DMA interface to the Flash memory according to the selected DMA control signal and the second data channel further comprises:
setting the DMA data configuration information as a first data block, setting a source address of the first data block according to a storage position of the DMA data configuration information, and setting a target address of the first data block as the Flash controller;
setting the programming data as a second data block, setting a source address of the second data block according to a storage position of the programming data, and setting a target address of the second data block as the Flash memory;
and respectively transmitting the first data block and the second data block in a block transmission mode according to the source address and the target address of the first data block and the second data block.
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