CN112650139B - DDR3 storage protocol-oriented clock controller and control method - Google Patents

Abstract

A clock controller and a control method facing a DDR3 storage protocol abandon traditional clock control circuits, adopt a negative feedback structure to reduce the influence of a clock caused by process, temperature and noise, and the structure comprises a digital delay phase-locked loop, a mirror symmetry delay chain, a Gray code phase selector and a Gray code phase interpolator to realize accurate control, lower phase error and less locking time of the clock. The DDR3 storage protocol-oriented clock controller can realize accurate delay of 64-level TAP of a DDR3 clock, guarantee the central position of a sampling clock delay data effective window, improve the stability and reliability of high-frequency clock sampling, and enable the highest frequency of the clock to be as high as 800 MHz.

Description

A clock controller and control method for DDR3 storage protocol

technical field

The invention relates to a clock controller and a control method oriented to a DDR3 storage protocol, in particular to a clock control circuit optimized for DDR3 application requirements through programmable logic devices, belonging to the field of integrated circuits.

Background technique

DDR3 SDRAM adopts a more advanced production process on the basis of DDR2 SDRAM, its working voltage is reduced from 1.8V to 1.5V, and using a more advanced process, its memory data transfer rate has been greatly improved, up to 1600MHz, can Meet the needs of high-performance servers while enabling fast, stable and reliable system operation

In DDR3 SDRAM, the data is doubled, and the data sampling clock can reach up to 800MHz, that is, both the rising and falling edges of the data clock are sampled at the same time. Therefore, how to quickly and accurately locate the sampling clock in the DDR3 SDRAM controller is very important. Whether the accurate sampling data and sampling precision can be correctly controlled has become an important factor affecting the performance of the memory controller. Therefore, there are high requirements for the performance and accuracy of the clock controller oriented to the DDR3 protocol. The DDR3 controller has two clocks, one is an external bus clock, and the other is an internal working clock. Theoretically, the two clocks of the DDR3 controller should be synchronized, but due to various reasons, such as temperature, voltage fluctuations, etc., delays make it difficult to synchronize the two. If the internal clock of DDR3 memory deviates from the external clock, it is likely to cause errors due to data asynchrony. In view of the fact that the external clock and the internal clock will not be absolutely unified, the delay of the internal clock needs to be dynamically corrected according to the external clock to synchronize with the external clock, so as to achieve precise control of the clock and lower phase error, and to achieve 64-level TAP for the DDR3 clock. precise delay. At the same time, less locking time, higher flexibility, and higher clock controller performance are required.

SUMMARY OF THE INVENTION

The technical problem solved by the present invention is: overcoming the deficiencies of the prior art, providing a clock controller and a control method oriented to the DDR3 storage protocol, and solving the problem of asynchrony between the internal and external clocks of the DDR3 memory caused by temperature, voltage fluctuation, etc., Improve the performance of the delay line, solve the problem of accurate delay of 64-level TAP of DDR3 clock, solve the problem of poor sampling accuracy of DDR3 clock controller, and solve the problem of poor anti-interference ability and long locking time of DDR3 clock controller.

The technical solution of the present invention is: a clock controller oriented to the DDR3 storage protocol, a digital delay phase locked loop, a mirror symmetrical delay chain, a Gray phase selector, and a Gray code phase interpolator;

The digital delay phase-locked loop receives the external common clock signal CLK_IN, outputs the clock signal CLK_FB and feeds back into the input, and sends the output voltage signals Vctrl_P and Vctrl_N to the mirror symmetrical delay chain;

Mirror symmetrical delay chain, receives external ordinary clock signal CLK_IN, receives digital delay phase-locked loop voltage signals Vctrl_P and Vctrl_N and converts them into 8 output clocks Clk45, Clk225, Clk90, Clk270, Clk135, Clk315, Clk180, Clk0 to Gray code phase selector;

Gray code phase selector, receives external common control signals PS0, PS1, PS2, and selects eight output clocks of the mirror symmetrical delay chain to the Gray code phase interpolator;

Gray code phase interpolator, receives external common control signals PI0, PI1, PI2, receives the output Vctrl_P and Vctrl_N voltage signals of the digital delay phase-locked loop, receives the gray code phase selector output, and outputs external clock signals Output_P and Output_N.

Further, the frequency range of the external common clock signal CLK_IN is 400MHz to 800MHz; the external clock signals Output_P and Output_N are a pair of differential output clock signals; the external common control signals PS0, PS1, PS2 are used to control the gray code phase selector to work normally. The external common control signals PI0, PI1, PI2 are the clock signals that control the normal control operation of the Gray code phase interpolator.

Further, the digital delay phase-locked loop includes an N-channel mos tube K15, a P-channel mos tube K14, a delay unit K9, a delay unit K10, a delay unit K11, a delay unit K12, a delay unit K13, and a phase detector K5. , charge pump K6, filter K7, reference circuit K8;

The external common clock input terminal signal CK_IN is connected to the input terminal of the delay unit K9 and the input terminal of the phase detector K5, and the other input terminal of the phase detector K5 is connected to the feedback clock signal CK_FB; the output terminal UP and the output terminal of the phase detector K5 DOWN is connected to the input terminal of the charge pump K6, and the output terminal Vctrl of the charge pump is connected to the input terminal of the filter K7; the output terminal Vctrl_A of the filter K7 is connected to the input terminal of the reference circuit K8, and the output terminals of the reference circuit are Vctrl_P and Vctrl_N; the control of the delay unit K9 The terminal C24 is connected to the drain of the P-channel MOS transistor, the control terminal C23 is connected to the drain of the N-channel MOS transistor, and the output terminal is connected to the input terminal of the next stage delay unit K10; the control terminal C27 of the delay unit K10 is connected to the P-channel The drain of the channel MOS transistor, the control terminal C26 is connected to the drain of the N-channel MOS transistor, and the output terminal is connected to the input terminal of the next stage delay unit K11; the control terminal C30 of the delay unit K11 is connected to the drain of the P-channel MOS transistor, The control terminal C29 is connected to the drain of the N-channel MOS transistor, and the output terminal is connected to the input terminal of the next stage delay unit K12; the control terminal C33 of the delay unit K12 is connected to the drain of the P-channel MOS transistor, and the control terminal C32 is connected to N The drain of the channel MOS transistor, the output terminal is connected to the input terminal of the next stage delay unit K13; the control terminal C35 of the delay unit K13 is connected to the drain of the P-channel MOS transistor, and the control terminal C36 is connected to the drain of the N-channel MOS transistor , the output is connected to the feedback clock input CK_FB.

Further, the phase detector K5 includes a flip-flop K16, a flip-flop K19, an inverter K18, and a NAND gate K17;

The external common clock signal CK_IN is connected to the clock input terminal of the flip-flop K16, the common clock signal CK_FB is connected to the clock input terminal of the flip-flop K19, the data terminal of the flip-flop K16 is connected to the power supply VS, the data terminal of the flip-flop K19 is connected to the power supply VS, and the data terminal of the flip-flop K16 is connected to the power supply VS. The output terminal Q and the output terminal of the flip-flop K19 are connected to the input port of the NAND gate K17, the output terminal of the NAND gate K17 is connected to the input terminal of the inverter K18, and the output terminal of the inverter K18 is connected to the flip-flop K16 and the flip-flop K19. reset port.

Further, the charge pump K6 includes a P-channel MOS transistor K24, a P-channel MOS transistor K20, a P-channel MOS transistor K22, an N-channel MOS transistor K21, an N-channel MOS transistor K23, and an N-channel MOS transistor K25;

The power supply VS is connected to the source of the P-channel MOS transistor K24, the gate of the P-channel MOS transistor K24 is connected to the input terminal control signal Vctrl_P, and the drain is connected to the sources of the P-channel MOS transistor K20 and the P-channel MOS transistor K22 The gate of the P-channel MOS transistor K20 is connected to the input terminal signal UP, and the drain is connected to the drain of the N-channel MOS transistor K21; the source of the N-channel MOS transistor K25 is connected to the ground GS, and the gate is connected to the input terminal control signal Vctrl_N , the drain is connected to the source of the N-channel MOS transistor K21 and the N-channel MOS transistor K23; the gate of the N-channel MOS transistor K23 is connected to the reverse of the input signal DOWN, and the drain is connected to the P-channel MOS transistor K22 The drain of the P-channel MOS transistor K22 is connected to the reverse of the input signal UP, and the drain of the P-channel MOS transistor K20 is connected to the output terminal Vctrl.

Further, the filter K7 includes a capacitor K24, a resistor K25, and a capacitor K26;

One end of the capacitor K24 and the capacitor K26 is connected to the ground GS; the input end Vctrl is connected to the other end of the capacitor K24, and is connected to one end of the resistor K25, and is connected to the output end Vctrl_A; the other end of the resistor K25 is connected to the other end of the capacitor K26;

The reference circuit K8 includes a P-channel MOS transistor K26, a P-channel MOS transistor K27, a P-channel MOS transistor K32, a P-channel MOS transistor K33, a P-channel MOS transistor K34, a P-channel MOS transistor K35, and an N-channel MOS transistor Tube K28, N-channel MOS tube K29, N-channel MOS tube K30, N-channel MOS tube K31, N-channel MOS tube K39, N-channel MOS tube K36, N-channel MOS tube K37, resistor K38;

The power supply VS is connected to the source of the P-channel MOS transistor K26, the gate of the P-channel MOS transistor K26 is connected to the output terminal of the resistor K38, and the drain of the P-channel MOS transistor K26 is connected to the source of the P-channel MOS transistor K27 The gate of the P-channel MOS transistor K27 is connected to the ground GS, the drain of the P-channel MOS transistor K26 is connected to the drain and gate of the N-channel MOS transistor K28, and the gate of the N-channel MOS transistor K28 is connected to The gate of the N-channel MOS transistor K30, the source of the N-channel MOS transistor K28 are connected to the drain of the N-channel MOS transistor K29 and the source of the N-channel MOS transistor K30, and the gate of the N-channel MOS transistor K29 Connect the control signal ctrl, the source of the N-channel MOS transistor K29 is connected to the ground GS; the source of the N-channel MOS transistor K30 is connected to the source of the N-channel MOS transistor K31 and the N-channel MOS transistor K39, and the N-channel MOS transistor K31 The gate of the N-channel MOS transistor K31 is connected to the input terminal control signal Vctrl_A, the drain of the N-channel MOS transistor K31 is connected to the input terminal of the resistor K38 and the drain of the P-channel MOS transistor K33, and the gate of the N-channel MOS transistor K39 is connected to the N-channel MOS transistor K39. The gate of the channel MOS transistor K37, the drain of the N-channel MOS transistor K39 is connected to the gate and drain of the P-channel MOS transistor K32, and the source of the P-channel MOS transistor K32 is connected to the power supply VS and the P-channel MOS transistor The source of the tube K33, the drain of the P-channel MOS tube K33 is connected to the input end of the resistor K38, and the output end of the resistor K38 is connected to the gate of the P-channel MOS tube K34 and the output end Vctrl_P; The source is connected to the power supply VS, the drain is connected to the source of the P-channel MOS transistor K35, the gate of the P-channel MOS transistor K35 is connected to the ground GS, and the drain of the P-channel MOS transistor K35 is connected to the N-channel MOS transistor The drain of K37, the gate of the N-channel MOS transistor K37 are connected to the output terminal Vctrl_N and the drain of the N-channel MOS transistor K36, the gate of the N-channel MOS transistor K36 is connected to the control signal ctrl, and the source is connected to the ground GS.

Further, the mirror-symmetrical delay chain includes a delay unit K40, a delay unit K41, a delay unit K42, a delay unit K43, a delay unit K44, a P-channel MOS transistor K39, an N-channel MOS transistor K45, and an inverting phase. inverter K46, inverter K47, inverter K48, inverter K49;

The common clock input terminal signal CK_IN is connected to the input terminal of the delay unit K40, and the control terminal C53 of the delay unit K40 is connected to the control terminal C56 of the delay unit K41, the control terminal C58 of the delay unit K42, the control terminal C62 of the delay unit K43, and the delay unit K41. The control terminal C64 of the unit K44, the gate of the P-channel MOS transistor K39 is connected to the input terminal Vctrl_P, the source of the P-channel MOS transistor K39 is connected to the power supply VS, the control terminal C52 of the delay unit K40 is connected to the control terminal C55 of the delay unit K41, and the delay The control terminal C59 of the unit K42, the control terminal C61 of the delay unit K43, the control terminal C65 of the delay unit K44, the drain of the N-channel MOS tube K45, the gate of the N-channel MOS tube K45 is connected to the input terminal Vctrl_N, and the N-channel MOS tube K45 The source is connected to the ground GS, the output terminal C54 of the delay unit K40 is connected to the input terminal of the next stage delay unit K41, the output terminal Clk_45, the input terminal of the inverter K46, the output terminal C57 of the delay unit K41 is connected to the next stage delay unit K42 The input terminal, the output terminal Clk90, the input terminal of the inverter K47, the output terminal C60 of the delay unit K42 is connected to the input terminal of the next stage delay unit K43, the output terminal Clk_135, the input terminal of the inverter K48, the output terminal C63 of the delay unit K43 Connect the input terminal of the next stage delay unit K44, the output terminal Clk180, the input terminal of the inverter K49, the output terminal of the inverter K46 is connected to the output terminal Clk_225, the output terminal of the inverter K47 is connected to the output terminal Clk_270, and the output terminal of the inverter K48 is connected to the output terminal Clk_270. The output terminal Clk_315 is connected, and the output terminal of the inverter K49 is connected to the output terminal Clk_0.

Further, the Gray code phase selector is connected to input terminals Clk_45, Clk_225, Clk_90, Clk_270, Clk_135, Clk_315, Clk_180, Clk_0, external input terminals PS0, PS1, PS2, and output terminals Out1_P, Out1_N, Out2_P, Out2_N.

Further, the Gray code phase interpolator includes a Gray code decoding circuit K51, a P-channel MOS transistor K52, a P-channel MOS transistor K53, a P-channel MOS transistor K54, a P-channel MOS transistor K55, and a P-channel MOS transistor K56, P-channel MOS tube K57, P-channel MOS tube K58, P-channel MOS tube K59, P-channel MOS tube K60, P-channel MOS tube K61, P-channel MOS tube K611, P-channel MOS tube K62 , P-channel MOS tube K63, P-channel MOS tube K64, P-channel MOS tube K65, P-channel MOS tube K66, P-channel MOS tube K67, P-channel MOS tube K68, P-channel MOS tube K69, P-channel MOS tube K70, P-channel MOS tube K71, P-channel MOS tube K72, P-channel MOS tube K73, P-channel MOS tube K74, P-channel MOS tube K75, P-channel MOS tube K76, P Channel MOS tube K77, P-channel MOS tube K78, P-channel MOS tube K79, P-channel MOS tube K80, P-channel MOS tube K81, N-channel MOS tube K82, N-channel MOS tube K83;

The Gray code decoding circuit is connected to the input terminals PI0, PI1, PI2, and outputs 16 control signals I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15 , I16, the power supply VS is connected to the source of the P-channel MOS transistor K52, the gate of the P-channel MOS transistor K52 is connected to the input terminal Vctrl_P, the drain of the P-channel MOS transistor K52 is connected to the source of the P-channel MOS transistor K61 and the P-channel The source of the channel MOS transistor K611, the gate of the P-channel MOS transistor K61 is connected to the ground GS, the gate of the P-channel MOS transistor K611 is connected to the control signal I0, and the drain of the P-channel MOS transistor K61 is connected to the P-channel MOS transistor The drain of K62, the drain of P-channel MOS transistor K64, the drain of P-channel MOS transistor K66, the drain of P-channel MOS transistor K68, the drain of P-channel MOS transistor K70, the drain of P-channel MOS transistor K70, the drain of P-channel MOS transistor K66 The drain of K72, the drain of P-channel MOS transistor K74, the drain of P-channel MOS transistor K76, the source of P-channel MOS transistor K78, the source of P-channel MOS transistor K80, the P-channel MOS transistor The drain of K611 is connected to the drain of P-channel MOS transistor K63, the drain of P-channel MOS transistor K65, the drain of P-channel MOS transistor K67, the drain of P-channel MOS transistor K69, and the drain of P-channel MOS transistor K69. The drain of K71, the drain of the P-channel MOS transistor K73, the drain of the P-channel MOS transistor K75, the drain of the P-channel MOS transistor K77, the source of the P-channel MOS transistor K79, the P-channel MOS transistor The source of K81, the power supply VS is connected to the source of the P-channel MOS transistor K53, the gate of the P-channel MOS transistor K53 is connected to the input terminal Vctrl_P, the drain of the P-channel MOS transistor K53 is connected to the source of the P-channel MOS transistor K62 and The source of the P-channel MOS transistor K63, the gate of the P-channel MOS transistor K62 is connected to the control signal I1, the gate of the P-channel MOS transistor K63 is connected to the control signal I2, and the power supply VS is connected to the source of the P-channel MOS transistor K54 , the gate of the P-channel MOS transistor K54 is connected to the input terminal Vctrl_P, the drain of the P-channel MOS transistor K54 is connected to the source of the P-channel MOS transistor K64 and the source of the P-channel MOS transistor K65, and the The gate is connected to the control signal I3, the gate of the P-channel MOS transistor K65 is connected to the control signal I4, the power supply VS is connected to the source of the P-channel MOS transistor K55, the gate of the P-channel MOS transistor K55 is connected to the input terminal Vctrl_P, and the P-channel The drain of the MOS transistor K55 is connected to the source of the P-channel MOS transistor K66 and the source of the P-channel MOS transistor K67, the gate of the P-channel MOS transistor K66 is connected to the control signal I5, and the gate of the P-channel MOS transistor K67 is connected to The control signal I6, the power supply VS is connected to the source of the P-channel MOS transistor K56, the gate of the P-channel MOS transistor K56 is connected to the input terminal Vctrl_P, the drain of the P-channel MOS transistor K56 is connected to the source of the P-channel MOS transistor K68 and P ditch The source of the channel MOS transistor K69, the gate of the P-channel MOS transistor K68 is connected to the control signal I7, the gate of the P-channel MOS transistor K69 is connected to the control signal I8, the power supply VS is connected to the source of the P-channel MOS transistor K57, P The gate of the channel MOS transistor K57 is connected to the input terminal Vctrl_P, the drain of the P-channel MOS transistor K57 is connected to the source of the P-channel MOS transistor K70 and the source of the P-channel MOS transistor K71, and the gate of the P-channel MOS transistor K70 The control signal I9 is connected, the gate of the P-channel MOS transistor K71 is connected to the control signal I10, the power supply VS is connected to the source of the P-channel MOS transistor K58, the gate of the P-channel MOS transistor K58 is connected to the input terminal Vctrl_P, and the P-channel MOS transistor The drain of K58 is connected to the source of the P-channel MOS transistor K72 and the source of the P-channel MOS transistor K73, the gate of the P-channel MOS transistor K72 is connected to the control signal I11, and the gate of the P-channel MOS transistor K73 is connected to the control signal I12, the power supply VS is connected to the source of the P-channel MOS transistor K59, the gate of the P-channel MOS transistor K59 is connected to the input terminal Vctrl_P, the drain of the P-channel MOS transistor K59 is connected to the source of the P-channel MOS transistor K74 and the P-channel The source of the MOS transistor K75, the gate of the P-channel MOS transistor K74 is connected to the control signal I13, the gate of the P-channel MOS transistor K75 is connected to the control signal I14, the power supply VS is connected to the source of the P-channel MOS transistor K60, and the P-channel The gate of the channel MOS transistor K60 is connected to the input terminal Vctrl_P, the drain of the P-channel MOS transistor K60 is connected to the source of the P-channel MOS transistor K76 and the source of the P-channel MOS transistor K77, and the gate of the P-channel MOS transistor K76 is connected to Control signal I15, the gate of the P-channel MOS tube K77 is connected to the power supply VS, the source of the P-channel MOS tube K78, the source of the P-channel MOS tube K79, and the source of the P-channel MOS tube K80 are connected to the power supply Vdd input terminal K88 ; The drain of the P-channel mos tube K78, the drain of the P-channel mos tube K79, and the drain of the P-channel mos tube K80 are commonly connected to the drain of the N-channel mos tube K81; the source of the N-channel mos tube K81 is connected to the N-channel mos tube K81. The drain of the channel mos tube K82, the source of the N-channel mos tube K82 is connected to the drain of the N-channel mos tube K83, the source of the N-channel mos tube K83 is connected to the ground, and the gate of the P-channel mos tube K78 is connected to the input terminal Out1_P, the gate of the P-channel mos tube K79 is connected to the input terminal Out2_P, the gate of the P-channel mos tube K80 is connected to the input terminal Out1_N, the gate of the P-channel mos tube K81 is connected to the input terminal Out2_N, and the drain of the P-channel mos tube K78 is connected The drain of the N-channel mos tube K82, the drain of the P-channel mos tube K79 and the output terminal Output_N, the drain of the P-channel mos tube K80 is connected to the drain of the N-channel mos tube K81, the drain of the P-channel mos tube K83 and the output The terminal Output_P, the gate of the N-channel mos tube K82 is connected to the input terminal Vctrl_N, and the source is connected to the ground GS, N The gate of the channel mos tube K83 is connected to the input terminal Vctrl_N, and the source is connected to the ground GS.

According to a clock control method implemented by a clock controller oriented to a DDR3 storage protocol, the method includes the following steps:

1) The digital delay phase-locked loop receives the external ordinary clock signal CLK_IN, and the output clock signal CLK_FB is fed back into the input, and the output voltage signals Vctrl_P and Vctrl_N control the mirror-symmetrical delay chain;

2) Mirror symmetrical delay chain, receiving the external common clock signal CLK_IN, and converting the input external common clock signal into 8 output clocks Clk45, Clk225, Clk90 of different phases under the control of the digital delay phase-locked loop voltage signals Vctrl_P and Vctrl_N , Clk270, Clk135, Clk315, Clk180, Clk0 to Gray code phase selector;

3) Gray code phase selector, receiving external ordinary control signals PS0, PS1, PS2, and selecting 8 output clocks of different phases of the mirror symmetrical delay chain to the Gray code phase interpolator for phase interpolation;

4) Gray code phase interpolator, receives external common control signals PI0, PI1, PI2, receives the output Vctrl_P and Vctrl_N voltage signals of the digital delay phase-locked loop, receives the gray code phase selector output, and outputs external clock signals Output_P and Output_N, In this way, through the six-bit control signals of PS0, PS1, PS2, PI0, PI1, and PI2, the external input clock can be subjected to 64-level TAP interpolation to achieve accurate phase interpolation and accurate clock delay.

The advantages of the present invention compared with the prior art are:

(1) The present invention can improve the flexibility of the clock controller by adopting the digital delay phase-locked loop structure to realize the precise delay of the clock, and adopt the negative feedback structure to reduce the influence of the clock caused by technology, temperature and noise, and provide a clock controller. anti-interference ability.

(2) The present invention adopts a mirror-symmetrical delay chain structure to ensure that the mirror-symmetrical delay chain and the digital delay phase-locked loop with a negative feedback structure are precisely in phase, thereby improving the stability and reliability of high-frequency clock sampling. At the same time, it can also achieve the same fast locking as the digital delay phase-locked loop to meet the requirements of DDR3 sampling stability and high performance.

(3) The present invention can reduce the phase jitter caused by the traditional phase selection technology by using the Gray code phase selector structure, can perform phase selection quickly and accurately, reduce the error of phase selection, and realize the accurate phase precision and range of DDR3.

(4) By adopting the Gray code phase interpolator structure, the present invention can realize accurate interpolation of 64-level TAP in the selected phase, ensure that the clock can be delayed to the center of the data valid window, improve the sampling accuracy, and ensure the acquisition of DDR3 data The correctness of the DDR3 storage interface and the balance of the setup and hold time ensure that the DDR3 storage interface can perform correct read and write operations and ensure the synchronization of internal and external clocks.

Description of drawings

1 is a schematic diagram of a clock controller of the present invention oriented to a DDR3 storage protocol;

2 is a schematic diagram of a digital delay phase-locked loop circuit of the present invention;

Fig. 3 is the circuit schematic diagram of phase detector K5 of the present invention;

4 is a schematic diagram of a charge pump circuit of the present invention;

Fig. 5 is the circuit schematic diagram of filter K7 of the present invention;

6 is a schematic diagram of a reference circuit of the present invention;

7 is a schematic diagram of a mirror-symmetrical delay chain circuit of the present invention;

8 is a schematic diagram of a Gray code phase selector of the present invention;

FIG. 9 is a schematic diagram of the Gray code phase interpolator of the present invention.

Detailed ways

In order to better understand the above technical solutions, the technical solutions of the present application will be described in detail below through the accompanying drawings and specific embodiments. It is not a limitation on the technical solutions of the present application, and the embodiments of the present application and the technical features in the embodiments may be combined with each other under the condition of no conflict.

A clock controller oriented to the DDR3 storage protocol provided by the embodiments of the present application will be described in further detail below with reference to the accompanying drawings. Symmetrical delay chain K2, Gray code phase selector K3, Gray code phase interpolator K4.

In the solution provided by the embodiment of the present application, as shown in FIG. 1 , the input of the digital delay phase-locked loop is connected to the external ordinary clock signal input CLK_IN, and the other input (C0) is connected to the digital delay phase-locked loop output CLK_FB (C1) . The two outputs Vctrl_P and Vctrl_N are connected to a mirror symmetric delay chain.

The mirror symmetrical delay chain input is connected to the external common clock signal input CLK_IN, the other two inputs are connected to the digital delay phase-locked loop outputs Vctrl_P and Vctrl_N, and the outputs are connected to the Gray code phase selectors Clk45(C5), Clk225(C6), Clk90( C7), Clk270(C8), Clk135(C12), Clk315(C11), Clk180(C10), Clk0(C9).

Gray code phase selector input is connected to external common control signals PS0(C15), PS1(C14), PS2(C13), and is connected to mirror symmetrical delay chain input Clk45(C5), Clk225(C6), Clk90(C7), Clk270( C8), Clk135(C12), Clk315(C11), Clk180(C10), Clk0(C9), the output is connected to the Gray code phase interpolator.

Gray code phase interpolator, the input receives external common control signals PI0 (C16), PI1 (C17), PI2 (C18), the input is connected to the output of the Gray code phase selector, and the input is also connected to the digital delay phase locked loop output Vctrl_P and Vctrl_N , the output is connected to the external clock signals Output_P (C20) and Output_N (C21).

The digital delay phase-locked loop, as shown in Figure 2, includes: N-channel MOS transistor K15, P-channel MOS transistor K14, delay unit K9, delay unit K10, delay unit K11, delay unit K12, delay unit K13, Phaser K5, charge pump K6, filter K7, reference circuit K8.

The external common clock input terminal signal CK_IN (C37) is connected to the input terminal of the delay unit K9 and the input terminal of the phase detector K5, and the other input terminal of the phase detector K5 is connected to the feedback clock signal CK_FB (C38). The output terminals UP (C39) and DOWN (C40) of the phase detector K5 are connected to the input terminal of the charge pump (K6), and the output terminal Vctrl (C41) of the charge pump is connected to the input terminal of the filter K7. The output terminal Vctrl_A (C42) of the filter K7 is connected to the input terminal of the reference circuit (K8), and the output ports of the reference circuit are Vctrl_P (C43) and Vctrl_N (C44). The control terminal C24 of the delay unit K9 is connected to the drain of the P-channel MOS transistor, the control terminal C23 is connected to the drain of the N-channel MOS transistor, and the output terminal is connected to the input terminal of the next stage delay unit K10. The control terminal C27 of the delay unit K10 is connected to the drain of the P-channel MOS transistor, the control terminal C26 is connected to the drain of the N-channel MOS transistor, and the output terminal is connected to the input terminal of the next stage delay unit K11. The control terminal C30 of the delay unit K11 is connected to the drain of the P-channel MOS transistor, the control terminal C29 is connected to the drain of the N-channel MOS transistor, and the output terminal is connected to the input terminal of the next stage delay unit K12. The control terminal C33 of the delay unit K12 is connected to the drain of the P-channel MOS transistor, the control terminal C32 is connected to the drain of the N-channel MOS transistor, and the output terminal is connected to the input terminal of the next stage delay unit K13. The control terminal C35 of the delay unit K13 is connected to the drain of the P-channel MOS transistor, the control terminal C36 is connected to the drain of the N-channel MOS transistor, and the output terminal is connected to the feedback clock input CK_FB (C38).

The phase detector K5, as shown in Figure 3, includes a flip-flop K16, a flip-flop K19, an inverter K18, and a NAND gate K17.

The external common clock signal CK_IN (C45) is connected to the clock input terminal of the flip-flop K16, the common clock signal CK_FB (C46) is connected to the clock input terminal of the flip-flop K19, the data terminal of the flip-flop K16 is connected to the power supply VS, and the data terminal of the flip-flop K19 is connected to the power supply VS, the output terminal Q of the flip-flop K16 and the output terminal of the flip-flop K19 are connected to the input port of the NAND gate K17, the output terminal of the NAND gate K17 is connected to the input terminal of the inverter K18, and the output terminal of the inverter K18 is connected to the trigger Reset port of device K16 and flip-flop K19.

The charge pump, as shown in Figure 4, includes: P-channel MOS transistor K24, P-channel MOS transistor K20, P-channel MOS transistor K22, N-channel MOS transistor K21, N-channel MOS transistor K23, N-channel MOS transistor Tube K25.

The power supply VS is connected to the source of the P-channel MOS transistor K24, the gate of the P-channel MOS transistor K24 is connected to the input terminal control signal Vctrl_P, and the drain is connected to the sources of the P-channel MOS transistor K20 and the P-channel MOS transistor K22 pole. The gate of the P-channel MOS transistor K20 is connected to the input signal UP, and the drain is connected to the drain of the N-channel MOS transistor K21. The source of the N-channel MOS transistor K25 is connected to the ground GS, the gate is connected to the input terminal control signal Vctrl_N, and the drain is connected to the sources of the N-channel MOS transistor K21 and the N-channel MOS transistor K23. The gate of the N-channel MOS transistor K23 is connected to the reverse of the input signal DOWN, and the drain is connected to the drain of the P-channel MOS transistor K22. The gate of the P-channel MOS transistor K22 is connected to the reverse of the input terminal signal UP, and the drain of the P-channel MOS transistor K20 is connected to the output terminal Vctrl.

The filter K7, as shown in Figure 5, includes: a capacitor K24, a resistor K25, and a capacitor K26.

One end of the capacitor K24 and the capacitor K26 is connected to the ground GS. The input end Vctrl (C49) is connected to the other end of the capacitor K24, and is connected to one end of the resistor K25, and is connected to the output end Vctrl_A. The other end of the resistor K25 is connected to the other end of the capacitor K26.

The reference circuit, as shown in Figure 6, includes: P-channel MOS tube K26, P-channel MOS tube K27, P-channel MOS tube K32, P-channel MOS tube K33, P-channel MOS tube K34, P-channel MOS tube Tube K35, N-channel MOS tube K28, N-channel MOS tube K29, N-channel MOS tube K30, N-channel MOS tube K31, N-channel MOS tube K39, N-channel MOS tube K36, N-channel MOS tube K37, resistor K38.

The power supply VS is connected to the source of the P-channel MOS transistor K26, the gate of the P-channel MOS transistor K26 is connected to the output terminal of the resistor K38, and the drain of the P-channel MOS transistor K26 is connected to the source of the P-channel MOS transistor K27 The gate of the P-channel MOS transistor K27 is connected to the ground GS, the drain of the P-channel MOS transistor K26 is connected to the drain and gate of the N-channel MOS transistor K28, and the gate of the N-channel MOS transistor K28 is connected to The gate of the N-channel MOS transistor K30, the source of the N-channel MOS transistor K28 are connected to the drain of the N-channel MOS transistor K29 and the source of the N-channel MOS transistor K30, and the gate of the N-channel MOS transistor K29 The control signal ctrl is connected, and the source of the N-channel MOS transistor K29 is connected to the ground GS. The source of the N-channel MOS transistor K30 is connected to the sources of the N-channel MOS transistor K31 and the N-channel MOS transistor K39, the gate of the N-channel MOS transistor K31 is connected to the input terminal control signal Vctrl_A, and the The drain is connected to the input terminal of the resistor K38 and the drain of the P-channel MOS transistor K33, the gate of the N-channel MOS transistor K39 is connected to the gate of the N-channel MOS transistor K37, and the drain of the N-channel MOS transistor K39 Connected to the gate and drain of the P-channel MOS transistor K32, the source of the P-channel MOS transistor K32 is connected to the power supply VS and the source of the P-channel MOS transistor K33, and the drain of the P-channel MOS transistor K33 is connected to the resistor The input terminal of K38 and the output terminal of the resistor K38 are connected to the gate of the P-channel MOS transistor K34 and the output terminal Vctrl_P. The source of the P-channel MOS transistor K34 is connected to the power supply VS, the drain is connected to the source of the P-channel MOS transistor K35, the gate of the P-channel MOS transistor K35 is connected to the ground GS, and the drain of the P-channel MOS transistor K35 Connected to the drain of the N-channel MOS transistor K37, the gate of the N-channel MOS transistor K37 is connected to the output terminal Vctrl_N and the drain of the N-channel MOS transistor K36, the gate of the N-channel MOS transistor K36 is connected to the control signal ctrl, The source is connected to ground GS.

The mirror-symmetrical delay chain, as shown in Figure 7, includes a delay unit K40, a delay unit K41, a delay unit K42, a delay unit K43, a delay unit K44, a P-channel MOS transistor K39, and an N-channel MOS transistor K45, inverter K46, inverter K47, inverter K48, inverter K49.

The common clock input terminal signal CK_IN (C51) is connected to the input terminal of the delay unit K40, and the control terminal C53 of the delay unit K40 is connected to the control terminal C56 of the delay unit K41, the control terminal C58 of the delay unit K42, and the control terminal C62 of the delay unit K43. , the control terminal C64 of the delay unit K44, the gate of the P-channel MOS tube K39 is connected to the input terminal Vctrl_P, the source of the P-channel MOS tube K39 is connected to the power supply VS, the control terminal C52 of the delay unit K40 is connected to the control terminal C55 of the delay unit K41 , the control terminal C59 of the delay unit K42, the control terminal C61 of the delay unit K43, the control terminal C65 of the delay unit K44, the drain of the N-channel MOS tube K45, the gate of the N-channel MOS tube K45 is connected to the input terminal Vctrl_N, the N-channel The source of the MOS tube K45 is connected to the ground GS, the output terminal C54 of the delay unit K40 is connected to the input terminal of the next stage delay unit K41, the output terminal Clk_45, and the input terminal of the inverter K46, and the output terminal C57 of the delay unit K41 is connected to the next stage delay unit. Time unit K42 input terminal, output terminal Clk90, inverter K47 input terminal, delay unit K42 output terminal C60 is connected to the next stage delay unit K43 input terminal, output terminal Clk_135, inverter K48 input terminal, delay unit K43 The output terminal C63 is connected to the input terminal of the next stage delay unit K44, the output terminal Clk180, and the input terminal of the inverter K49. The output terminal of the inverter K46 is connected to the output terminal Clk_225. The output terminal of the inverter K47 is connected to the output terminal Clk_270. The output terminal of K48 is connected to the output terminal Clk_315, and the output terminal of the inverter K49 is connected to the output terminal Clk_0.

Gray code phase selector, as shown in Figure 8, includes: Gray code phase selector K50

The Gray code phase selector is connected to input terminals Clk_45, Clk_225, Clk_90, Clk_270, Clk_135, Clk_315, Clk_180, Clk_0, external input terminals PS0, PS1, PS2, and output terminals Out1_P, Out1_N, Out2_P, Out2_N.

The Gray code phase interpolator, as shown in Figure 9, includes a Gray code decoding circuit K51, a P-channel MOS transistor K52, a P-channel MOS transistor K53, a P-channel MOS transistor K54, a P-channel MOS transistor K55, a P-channel MOS transistor K55, and a P-channel MOS transistor K55. Channel MOS tube K56, P-channel MOS tube K57, P-channel MOS tube K58, P-channel MOS tube K59, P-channel MOS tube K60, P-channel MOS tube K61, P-channel MOS tube K611, P-channel MOS tube MOS tube K62, P-channel MOS tube K63, P-channel MOS tube K64, P-channel MOS tube K65, P-channel MOS tube K66, P-channel MOS tube K67, P-channel MOS tube K68, P-channel MOS tube Tube K69, P-channel MOS tube K70, P-channel MOS tube K71, P-channel MOS tube K72, P-channel MOS tube K73, P-channel MOS tube K74, P-channel MOS tube K75, P-channel MOS tube K76, P-channel MOS tube K77, P-channel MOS tube K78, P-channel MOS tube K79, P-channel MOS tube K80, P-channel MOS tube K81, N-channel MOS tube K82, N-channel MOS tube K83 .

The Gray code decoding circuit is connected to the input terminals PI0, PI1, PI2, and outputs 16 control signals I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15 , I16, the power supply VS is connected to the source of the P-channel MOS transistor K52, the gate of the P-channel MOS transistor K52 is connected to the input terminal Vctrl_P, the drain of the P-channel MOS transistor K52 is connected to the source of the P-channel MOS transistor K61 and the P-channel The source of the channel MOS transistor K611, the gate of the P-channel MOS transistor K61 is connected to the ground GS, the gate of the P-channel MOS transistor K611 is connected to the control signal I0, and the drain of the P-channel MOS transistor K61 is connected to the P-channel MOS transistor The drain of K62, the drain of P-channel MOS transistor K64, the drain of P-channel MOS transistor K66, the drain of P-channel MOS transistor K68, the drain of P-channel MOS transistor K70, the drain of P-channel MOS transistor K70, the drain of P-channel MOS transistor K66 The drain of K72, the drain of P-channel MOS transistor K74, the drain of P-channel MOS transistor K76, the source of P-channel MOS transistor K78, the source of P-channel MOS transistor K80, the P-channel MOS transistor The drain of K611 is connected to the drain of P-channel MOS transistor K63, the drain of P-channel MOS transistor K65, the drain of P-channel MOS transistor K67, the drain of P-channel MOS transistor K69, and the drain of P-channel MOS transistor K69. The drain of K71, the drain of the P-channel MOS transistor K73, the drain of the P-channel MOS transistor K75, the drain of the P-channel MOS transistor K77, the source of the P-channel MOS transistor K79, the P-channel MOS transistor The source of K81, the power supply VS is connected to the source of the P-channel MOS transistor K53, the gate of the P-channel MOS transistor K53 is connected to the input terminal Vctrl_P, the drain of the P-channel MOS transistor K53 is connected to the source of the P-channel MOS transistor K62 and The source of the P-channel MOS transistor K63, the gate of the P-channel MOS transistor K62 is connected to the control signal I1, the gate of the P-channel MOS transistor K63 is connected to the control signal I2, and the power supply VS is connected to the source of the P-channel MOS transistor K54 , the gate of the P-channel MOS transistor K54 is connected to the input terminal Vctrl_P, the drain of the P-channel MOS transistor K54 is connected to the source of the P-channel MOS transistor K64 and the source of the P-channel MOS transistor K65, and the The gate is connected to the control signal I3, the gate of the P-channel MOS transistor K65 is connected to the control signal I4, the power supply VS is connected to the source of the P-channel MOS transistor K55, the gate of the P-channel MOS transistor K55 is connected to the input terminal Vctrl_P, and the P-channel The drain of the MOS transistor K55 is connected to the source of the P-channel MOS transistor K66 and the source of the P-channel MOS transistor K67, the gate of the P-channel MOS transistor K66 is connected to the control signal I5, and the gate of the P-channel MOS transistor K67 is connected to The control signal I6, the power supply VS is connected to the source of the P-channel MOS transistor K56, the gate of the P-channel MOS transistor K56 is connected to the input terminal Vctrl_P, the drain of the P-channel MOS transistor K56 is connected to the source of the P-channel MOS transistor K68 and P ditch The source of the channel MOS transistor K69, the gate of the P-channel MOS transistor K68 is connected to the control signal I7, the gate of the P-channel MOS transistor K69 is connected to the control signal I8, the power supply VS is connected to the source of the P-channel MOS transistor K57, P The gate of the channel MOS transistor K57 is connected to the input terminal Vctrl_P, the drain of the P-channel MOS transistor K57 is connected to the source of the P-channel MOS transistor K70 and the source of the P-channel MOS transistor K71, and the gate of the P-channel MOS transistor K70 The control signal I9 is connected, the gate of the P-channel MOS transistor K71 is connected to the control signal I10, the power supply VS is connected to the source of the P-channel MOS transistor K58, the gate of the P-channel MOS transistor K58 is connected to the input terminal Vctrl_P, and the P-channel MOS transistor The drain of K58 is connected to the source of the P-channel MOS transistor K72 and the source of the P-channel MOS transistor K73, the gate of the P-channel MOS transistor K72 is connected to the control signal I11, and the gate of the P-channel MOS transistor K73 is connected to the control signal I12, the power supply VS is connected to the source of the P-channel MOS transistor K59, the gate of the P-channel MOS transistor K59 is connected to the input terminal Vctrl_P, the drain of the P-channel MOS transistor K59 is connected to the source of the P-channel MOS transistor K74 and the P-channel The source of the MOS transistor K75, the gate of the P-channel MOS transistor K74 is connected to the control signal I13, the gate of the P-channel MOS transistor K75 is connected to the control signal I14, the power supply VS is connected to the source of the P-channel MOS transistor K60, and the P-channel The gate of the channel MOS transistor K60 is connected to the input terminal Vctrl_P, the drain of the P-channel MOS transistor K60 is connected to the source of the P-channel MOS transistor K76 and the source of the P-channel MOS transistor K77, and the gate of the P-channel MOS transistor K76 is connected to Control signal I15, the gate of the P-channel MOS tube K77 is connected to the power supply VS, the source of the P-channel MOS tube K78, the source of the P-channel MOS tube K79, and the source of the P-channel MOS tube K80 are connected to the power supply Vdd input terminal K88 ; The drain of the P-channel mos tube K78, the drain of the P-channel mos tube K79, and the drain of the P-channel mos tube K80 are commonly connected to the drain of the N-channel mos tube K81; the source of the N-channel mos tube K81 is connected to the N-channel mos tube K81. The drain of the channel mos tube K82, the source of the N-channel mos tube K82 is connected to the drain of the N-channel mos tube K83, the source of the N-channel mos tube K83 is connected to the ground, and the gate of the P-channel mos tube K78 is connected to the input terminal Out1_P, the gate of the P-channel mos tube K79 is connected to the input terminal Out2_P, the gate of the P-channel mos tube K80 is connected to the input terminal Out1_N, the gate of the P-channel mos tube K81 is connected to the input terminal Out2_N, and the drain of the P-channel mos tube K78 is connected The drain of the N-channel mos tube K82, the drain of the P-channel mos tube K79 and the output terminal Output_N, the drain of the P-channel mos tube K80 is connected to the drain of the N-channel mos tube K81, the drain of the P-channel mos tube K83 and the output The terminal Output_P, the gate of the N-channel mos tube K82 is connected to the input terminal Vctrl_N, and the source is connected to the ground GS, N The gate of the channel mos tube K83 is connected to the input terminal Vctrl_N, and the source is connected to the ground GS.

The whole circuit can work under the frequency clock of 400MHz-800MHz, and can be used in the DRAM memory interface facing the DDR3 storage protocol. Under normal working conditions, the circuit of the present invention adopts the 28-nanometer process device of SMIC, and the appropriate device type can also be selected according to the user's own needs, so as to realize the precise delay of the 64-level TAP of the DDR3 clock and ensure the The clock can be delayed to the center of the data valid window. Especially under the frequency clock of 800MHz, the maximum delay accuracy of each TAP can reach 19.53ps, which meets the high-frequency performance of DDR3 protocol DRAM.

Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

The content not described in detail in the specification of the present invention belongs to the well-known technology of those skilled in the art.

Claims (9)

1. A DDR3 storage protocol oriented clock controller, comprising: the digital delay phase-locked loop, the mirror symmetry delay chain, the Gray code phase selector and the Gray code phase interpolator;

the digital delay phase-locked loop receives an external common clock signal CLK _ IN, outputs a clock signal CLK _ FB feedback access input, and sends output voltage signals Vctrl _ P and Vctrl _ N to a mirror symmetry delay chain;

the mirror symmetry delay chain receives an external common clock signal CLK _ IN, receives voltage signals Vctrl _ P and Vctrl _ N of the digital delay phase-locked loop and converts the voltage signals into 8 paths of output clocks Clk45, Clk225, Clk90, Clk270, Clk135, Clk315, Clk180 and Clk0 to a Gray code phase selector;

the gray code phase selector receives external common control signals PS0, PS1 and PS2 and selects eight paths of output clocks of the mirror symmetry delay chain to the gray code phase interpolator;

the gray code phase interpolator receives external common control signals PI0, PI1 and PI2, receives Output voltage Vctrl _ P and Vctrl _ N of the digital delay phase-locked loop, receives Output of the gray code phase selector, and outputs external clock signals Output _ P and Output _ N;

the digital delay phase-locked loop comprises an N-channel mos tube K15, a P-channel mos tube K14, a delay unit K9, a delay unit K10, a delay unit K11, a delay unit K12, a delay unit K13, a phase discriminator K5, a charge pump K6, a filter K7 and a reference circuit K8;

an external common clock input end signal CK _ IN is connected to the input end of the delay unit K9 and the input end of the phase detector K5, and the other input end of the phase detector K5 is connected with a feedback clock signal CK _ FB; the output end UP and the output end DOWN of the phase detector K5 are connected to the input end of a charge pump K6, and the output end Vctrl of the charge pump is connected to the input end of a filter K7; an output end Vctrl _ A of the filter K7 is connected to an input end of a reference circuit K8, and output ports of the reference circuit are Vctrl _ P and Vctrl _ N; the control end C24 of the delay unit K9 is connected to the drain electrode of a P-channel MOS tube, the control end C23 is connected to the drain electrode of an N-channel MOS tube, and the output end of the delay unit K3878 is connected to the input end of the next-stage delay unit K10; the control end C27 of the delay unit K10 is connected to the drain electrode of a P-channel MOS tube, the control end C26 is connected to the drain electrode of an N-channel MOS tube, and the output end of the delay unit K3878 is connected to the input end of the next-stage delay unit K11; the control end C30 of the delay unit K11 is connected to the drain electrode of a P-channel MOS tube, the control end C29 is connected to the drain electrode of an N-channel MOS tube, and the output end of the delay unit K3878 is connected to the input end of the next-stage delay unit K12; the control end C33 of the delay unit K12 is connected to the drain electrode of a P-channel MOS tube, the control end C32 is connected to the drain electrode of an N-channel MOS tube, and the output end of the delay unit K3878 is connected to the input end of the next-stage delay unit K13; the control terminal C35 of the delay unit K13 is connected to the drain of the P-channel MOS transistor, the control terminal C36 is connected to the drain of the N-channel MOS transistor, and the output terminal is connected to the feedback clock input terminal CK _ FB.

2. The clock controller for DDR3 storage protocol-oriented memory controller of claim 1, wherein: the frequency range of the external common clock signal CLK _ IN is 400 MHz-800 MHz; the external clock signals Output _ P and Output _ N are a pair of differential Output clock signals; the external common control signals PS0, PS1 and PS2 are clock signals for controlling the gray code phase selector to normally control the working; the external common control signals PI0, PI1, and PI2 are clock signals for controlling the gray code phase interpolator to normally control the operation.

3. The clock controller for DDR3 storage protocol-oriented memory controller of claim 1, wherein: the phase detector K5 comprises a flip-flop K16, a flip-flop K19, an inverter K18 and a NAND gate K17;

an external common clock signal CK _ IN is connected to a clock input end of a flip-flop K16, a common clock signal CK _ FB is connected to a clock input end of a flip-flop K19, a data end of the flip-flop K16 is connected with a power supply VS, a data end of the flip-flop K19 is connected with the power supply VS, an output end Q of a flip-flop K16 and an output end of a flip-flop K19 are connected to an input port of a NAND gate K17, an output end of the NAND gate K17 is connected with an input end of an inverter K18, and an output end of the inverter K18 is connected to reset ports of the flip-flop K16 and the flip-flop K19.

4. The clock controller for DDR3 storage protocol-oriented memory controller of claim 1, wherein: the charge pump K6 comprises a P-channel MOS tube K24, a P-channel MOS tube K20, a P-channel MOS tube K22, an N-channel MOS tube K21, an N-channel MOS tube K23 and an N-channel MOS tube K25;

the power supply VS is connected to the source electrode of the P-channel MOS tube K24, the grid electrode of the P-channel MOS tube K24 is connected to the input end control signal Vctrl _ P, and the drain electrode of the P-channel MOS tube K20 and the source electrode of the P-channel MOS tube K22; the grid electrode of the P-channel MOS tube K20 is connected with an input end signal UP, and the drain electrode of the P-channel MOS tube K20 is connected with the drain electrode of the N-channel MOS tube K21; the source electrode of the N-channel MOS tube K25 is connected with the ground GS, the grid electrode of the N-channel MOS tube K25 is connected with the input end control signal Vctrl _ N, and the drain electrode of the N-channel MOS tube K21 and the source electrode of the N-channel MOS tube K23; the grid electrode of the N-channel MOS tube K23 is connected with the reverse direction of the signal DOWN at the input end, and the drain electrode of the N-channel MOS tube K23 is connected with the drain electrode of the P-channel MOS tube K22; the grid electrode of the P-channel MOS tube K22 is connected with the reverse direction of the signal UP at the input end, and the drain electrode of the P-channel MOS tube K20 is connected with the output end Vctrl.

5. A DDR3 storage protocol oriented clock controller in accordance with claim 1, wherein: the filter K7 comprises a capacitor K24, a resistor K25 and a capacitor K26;

one ends of the capacitor K24 and the capacitor K26 are connected to the ground GS; the input end Vctrl is connected to the other end of the capacitor K24, connected to one end of the resistor K25 and connected to the output end Vctrl _ A; the other end of the resistor K25 is connected to the other end of the capacitor K26;

the reference circuit K8 comprises a P-channel MOS tube K26, a P-channel MOS tube K27, a P-channel MOS tube K32, a P-channel MOS tube K33, a P-channel MOS tube K34, a P-channel MOS tube K35, an N-channel MOS tube K28, an N-channel MOS tube K29, an N-channel MOS tube K30, an N-channel MOS tube K31, an N-channel MOS tube K39, an N-channel MOS tube K36, an N-channel MOS tube K37 and a resistor K38;

a power supply VS is connected to the source electrode of a P-channel MOS tube K26, the gate electrode of a P-channel MOS tube K26 is connected to the output end of a resistor K38, the drain electrode of the P-channel MOS tube K26 is connected to the source electrode of a P-channel MOS tube K27, the gate electrode of a P-channel MOS tube K27 is connected to the ground GS, the drain electrode of the P-channel MOS tube K26 is connected to the drain electrode and the gate electrode of an N-channel MOS tube K28, the gate electrode of the N-channel MOS tube K28 is connected to the gate electrode of an N-channel MOS tube K30, the source electrode of the N-channel MOS tube K28 is connected to the drain electrode of an N-channel MOS tube K29 and the source electrode of an N-channel MOS tube K30, the gate electrode of the N-channel MOS tube K29 is connected to a control signal ctrl, and the source electrode of the N-channel MOS tube K29 is connected to the ground GS; the source of the N-channel MOS transistor K30 is connected to the sources of the N-channel MOS transistor K31 and the N-channel MOS transistor K39, the gate of the N-channel MOS transistor K31 is connected to the input control signal Vctrl _ a, the drain of the N-channel MOS transistor K31 is connected to the input of the resistor K38 and the drain of the P-channel MOS transistor K33, the gate of the N-channel MOS transistor K39 is connected to the gate of the N-channel MOS transistor K37, the drain of the N-channel MOS transistor K39 is connected to the gate and the drain of the P-channel MOS transistor K32, the source of the P-channel MOS transistor K32 is connected to the power supply VS and the source of the P-channel MOS transistor K33, the drain of the P-channel MOS transistor K33 is connected to the input of the resistor K38, and the output of the resistor K38 is connected to the gate of the P-channel MOS transistor K34 and the output Vctrl _ P; the source electrode of the P-channel MOS tube K34 is connected to a power supply VS, the drain electrode is connected to the source electrode of the P-channel MOS tube K35, the grid electrode of the P-channel MOS tube K35 is connected to the GS, the drain electrode of the P-channel MOS tube K35 is connected to the drain electrode of the N-channel MOS tube K37, the grid electrode of the N-channel MOS tube K37 is connected to the output end Vctrl _ N and the drain electrode of the N-channel MOS tube K36, the grid electrode of the N-channel MOS tube K36 is connected to a control signal ctrl, and the source electrode is connected to the GS.

6. The clock controller for DDR3 storage protocol-oriented memory controller of claim 1, wherein: the mirror symmetry delay chain comprises a delay unit K40, a delay unit K41, a delay unit K42, a delay unit K43, a delay unit K44, a P-channel MOS tube K39, an N-channel MOS tube K45, an inverter K46, an inverter K47, an inverter K48 and an inverter K49;

a signal CK _ IN at a common clock input end is connected to an input end of a delay unit K40, a control end C40 of the delay unit K40 is connected to a control end C40 of a delay unit K40, a control end C40 of the delay unit K40, a grid electrode of a P-channel MOS tube K40 is connected to an input end Vctrl _ P, a source electrode of the P-channel MOS tube K40 is connected to a power supply VS, a control end C40 of the delay unit K40 is connected to a control end C40 of the delay unit K40, a source electrode of the N-channel MOS tube K40, a grid electrode of the N-channel MOS tube K40 is connected to a ground, a C40 of the output end of the delay unit K40 is connected to a next stage C40 of the delay unit K40, a drain electrode of the delay unit K40 is connected to a next stage C40, a drain electrode of the delay unit K40, a drain of the delay unit K40 is connected to a lower stage C40, a drain of the delay unit K40, a delay unit K40 is connected to a lower stage C40, a drain of the delay unit K40 is connected to a delay unit K40, a lower stage of the delay unit K40 is connected to a delay unit K40, a drain of the delay unit K40 is connected to a lower stage, a delay unit K40 is connected to a drain of the delay unit K40, a drain of the delay unit K40 is connected to a drain, a drain of the delay unit K40 is connected to a lower stage, a drain, a delay unit K40 is connected to a drain of the delay unit K40 is connected to a delay unit K40, a drain of the delay unit K40 is connected to a delay unit K40, a delay unit K40 is connected to a ground, a delay unit K40 is connected to a delay unit K40, a delay unit K40 is connected to a delay unit K40, a lower stage, a delay unit K40 is connected to a delay unit K40, a delay unit K685, The output end Clk90 and the input end of the inverter K47 are connected, the output end C60 of the delay unit K42 is connected with the input end of the next-stage delay unit K43, the output end Clk _135 and the input end of the inverter K48, the output end C63 of the delay unit K43 is connected with the input end of the next-stage delay unit K44, the output end Clk180 and the input end of the inverter K49, the output end of the inverter K46 is connected with the output end Clk _225, the output end of the inverter K47 is connected with the output end Clk _270, the output end of the inverter K48 is connected with the output end Clk _315, and the output end of the inverter K49 is connected with the output end Clk _ 0.

7. The clock controller for DDR3 storage protocol-oriented memory controller of claim 1, wherein: the gray code phase selector is connected with the input terminals Clk _45, Clk _225, Clk _90, Clk _270, Clk _135, Clk _315, Clk _180 and Clk _0, the external input terminals PS0, PS1 and PS2 and the output terminal Out1_ P, Out1_ N, Out2_ P, Out2_ N.

8. The clock controller for DDR3 storage protocol-oriented memory controller of claim 1, wherein: a gray code phase interpolator, including a gray code decoding circuit K51, a P-channel MOS tube K611, a P-channel MOS tube K51, a P-channel K51, a P-channel K51, and a P-channel K51;

gray code decoding circuit is connected with input terminals PI0, PI1 and PI2, outputs 16 control signals I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15 and I16, a power supply VS is connected with the source of a P-channel MOS tube K52, the grid of the P-channel MOS tube K52 is connected with an input terminal Vctrl _ P, the drain of the P-channel MOS tube K52 is connected with the source of the P-channel MOS tube K61 and the source of the P-channel MOS tube K611, the grid of the P-channel MOS tube K61 is connected with a ground GS, the grid of the P-channel MOS tube K611 is connected with a control signal I0, the drain of the P-channel MOS tube K0 is connected with the drain of the P-channel MOS tube K0, the drain of the P-channel MOS tube K0, the drain of the MOS tube K0 of the MOS tube 0, the drain electrode of the P-channel MOS tube K611 is connected with the drain electrode of the P-channel MOS tube K63, the drain electrode of the P-channel MOS tube K65, the drain electrode of the P-channel MOS tube K67, the drain electrode of the P-channel MOS tube K69, the drain electrode of the P-channel MOS tube K71, the drain electrode of the P-channel MOS tube K73, the drain electrode of the P-channel MOS tube K75, the drain electrode of the P-channel MOS tube K77, the source electrode of the P-channel MOS tube K79 and the source electrode of the P-channel MOS tube K81, the power supply VS is connected with the source electrode of the P-channel MOS tube K53, the grid electrode of the P-channel MOS tube K53 is connected with the input terminal Vctrl _ P, the drain electrode of the P-channel MOS tube K53 is connected with the source electrode of the P-channel MOS tube K62 and the source electrode of the P-channel MOS tube K63, the grid electrode of the P-channel MOS tube K62 is connected with the control signal I1, the grid electrode of the P-channel MOS tube K63, the power supply VS is connected with the source electrode of the P-channel MOS tube K54, the drain electrode of the P-channel MOS tube K46K 386 and the drain electrode of the P-channel MOS tube K463, the grid of the P-channel MOS tube K64 is connected with a control signal I3, the grid of the P-channel MOS tube K65 is connected with a control signal I4, the power supply VS is connected with the source of the P-channel MOS tube K55, the grid of the P-channel MOS tube K55 is connected with an input end Vctrl _ P, the drain of the P-channel MOS tube K55 is connected with the source of the P-channel MOS tube K66 and the source of the P-channel MOS tube K67, the grid of the P-channel MOS tube K66 is connected with a control signal I5, the grid of the P-channel MOS tube K67 is connected with a control signal I6, the power supply VS is connected with the source of the P-channel MOS tube K56, the grid of the P-channel MOS tube K56 is connected with the input end Vctrl _ P, the drain of the P-channel MOS tube K56 is connected with the source of the P-channel MOS tube K68 and the source of the P-channel MOS tube K69, the grid of the P-channel MOS tube K68 is connected with a control signal I7, the grid of the P-channel MOS tube K69, the source of the P-channel MOS tube K387 is connected with the input end Vctrl-channel MOS tube K57, the drain of a P-channel MOS tube K57 is connected with the source of a P-channel MOS tube K70 and the source of a P-channel MOS tube K71, the gate of a P-channel MOS tube K70 is connected with a control signal I9, the gate of a P-channel MOS tube K71 is connected with a control signal I10, a power supply VS is connected with the source of a P-channel MOS tube K58, the gate of a P-channel MOS tube K58 is connected with an input end Vctrl _ P, the drain of a P-channel MOS tube K58 is connected with the source of a P-channel MOS tube K72 and the source of a P-channel MOS tube K73, the gate of a P-channel MOS tube K72 is connected with a control signal I11, the gate of a P-channel MOS tube K73 is connected with a control signal I12, the power supply VS is connected with the source of a P-channel MOS tube K59, the gate of a P-channel MOS tube K59 is connected with an input end Vctrl _ P, the drain of a P-channel MOS tube K59 is connected with the source of a P-channel MOS tube K6852 and the source of a P-channel MOS tube K5475, the gate of a power supply K74 is connected with the source of a power supply control signal I74, the gate of a power supply VS 74, the control signal VS channel MOS tube K74 is connected with the gate of a P-channel MOS tube K74, the grid electrode of the P-channel MOS tube K60 is connected with an input end Vctrl _ P, the drain electrode of the P-channel MOS tube K60 is connected with the source electrode of the P-channel MOS tube K76 and the source electrode of the P-channel MOS tube K77, the grid electrode of the P-channel MOS tube K76 is connected with a control signal I15, the grid electrode of the P-channel MOS tube K77 is connected with a power supply VS, and the source electrode of the P-channel MOS tube K78, the source electrode of the P-channel MOS tube K79 and the source electrode of the P-channel MOS tube K80 are connected with a power supply Vdd input end K88; the drain electrode of the P-channel mos tube K78, the drain electrode of the P-channel mos tube K79 and the drain electrode of the P-channel mos tube K80 are connected to the drain electrode of the N-channel mos tube K81; the source of an N-channel mos tube K81 is connected to the drain of an N-channel mos tube K82, the source of the N-channel mos tube K82 is connected to the drain of the N-channel mos tube K83, the source of the N-channel mos tube K83 is connected to the ground, the gate of a P-channel mos tube K78 is connected to the input end Out1_ P, the gate of a P-channel mos tube K79 is connected to the input end Out2_ P, the gate of the P-channel mos tube K80 is connected to the input end Out1_ N, the gate of the P-channel mos tube K81 is connected to the input end Out2_ N, the drain of the P-channel mos tube K78 is connected to the drain of the N-channel mos tube K82, the drain of the P-channel mos tube K79 and the Output end Output _ N, the drain of the P-channel mos tube K80 is connected to the N-channel mos tube K81, the drain of the P-channel mos tube K83 and the Output end P-channel mos 78, the gate of the N-channel mos tube K82 is connected to the input end Vcgsl, the source is connected to the ground, the source of the input end GS tube K83 and the input end Vcgs.

9. The clock control method implemented by the clock controller facing the DDR3 storage protocol as claimed in claim 1, wherein the method comprises the following steps:

1) the digital delay phase-locked loop receives an external common clock signal CLK _ IN, outputs a clock signal CLK _ FB feedback access input, and controls an output voltage signal Vctrl _ P and Vctrl _ N to be a mirror symmetry delay chain;

2) the mirror symmetry delay chain receives an external common clock signal CLK _ IN, converts the input external common clock signal into 8 paths of output clocks Clk45, Clk225, Clk90, Clk270, Clk135, Clk315, Clk180, Clk0 to Gray code phase selectors with different phases under the control of a digital delay phase-locked loop voltage signal Vctrl _ P and Vctrl _ N;

3) the gray code phase selector receives external common control signals PS0, PS1 and PS2, and selects 8 paths of output clocks with different phases of the mirror symmetry delay chain to the gray code phase interpolator to perform phase interpolation;

4) the gray code phase interpolator receives external common control signals PI0, PI1 and PI2, receives Output voltage signals Vctrl _ P and Vctrl _ N of the digital delay phase-locked loop, receives Output of the gray code phase selector, and outputs external clock signals Output _ P and Output _ N, so that 64-level TAP interpolation can be performed on an external input clock through six control signals PS0, PS1, PS2, PI0, PI1 and PI2, and accurate phase interpolation and accurate clock delay are achieved.

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