CN112636746B - CML high-speed wide-range asynchronous frequency divider, frequency dividing device and electronic equipment - Google Patents
CML high-speed wide-range asynchronous frequency divider, frequency dividing device and electronic equipment Download PDFInfo
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- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
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Abstract
The invention provides a CML high-speed wide-range asynchronous frequency divider, a frequency dividing device and electronic equipment, which comprise a clock signal port, a control signal port, an asynchronous frequency dividing module, an AND operation module, a D trigger, a first phase inverter and an output port; the asynchronous frequency division module comprises a plurality of frequency dividers; a clock pin of the first frequency divider and a clock pin of the D trigger are connected with a clock signal port, a clock pin of each subsequent frequency divider is connected with an output pin of the previous frequency divider, and the output pins of the frequency dividers are correspondingly connected with the input ends of the operation module one by one; the output end of the operation module is connected with the input end of the D trigger; the output port and the input end of the first inverter are connected with the output end of the D trigger; the reset pin of each frequency divider and one input end of the operation module are connected with the output end of the first phase inverter; and the control pins of the two frequency dividers are correspondingly connected with the input pins of the control signal port one by one.
Description
Technical Field
The invention relates to the technical field of frequency divider design, in particular to a CML high-speed wide-range asynchronous frequency divider, a frequency dividing device and electronic equipment.
Background
At present, most of common wide-range integer frequency dividers can realize any frequency dividing ratio, the limitation of a front-mounted 2/3 cascade dual-mode and multi-mode prescaler to the minimum frequency dividing ratio does not exist, the structure of the frequency divider is a counter formed by a group of resettable D triggers, counting is started through presetting an initial value, namely the frequency dividing ratio, when an input clock edge arrives, every input clock period is counted, the state value is added by 1, each D trigger of the counter is output to a period end detection module to detect whether counting is ended, when the state value is fully recorded, the counter outputs a clock edge, the period end detection module outputs a reset signal, the counter is reset to the initial value, and a counting period is completed. However, this type of wide range integer divider has high power consumption and low operating efficiency, and tends to be limited in use.
Disclosure of Invention
The invention aims to provide a CML high-speed wide-range asynchronous frequency divider, a frequency dividing device and electronic equipment, which are used for realizing the technical effect of reducing the power consumption of the frequency divider while improving the working efficiency of the frequency divider.
In a first aspect, the invention provides a CML high-speed wide-range asynchronous frequency divider, which comprises a clock signal port, a control signal port, an asynchronous frequency dividing module, an and operation module, a D flip-flop, a first inverter and an output port; the asynchronous frequency division module comprises a plurality of frequency dividers; the clock pin of the first frequency divider and the clock pin of the D trigger are both connected with the clock signal port, the clock pin of each subsequent frequency divider is connected with the output pin of the previous frequency divider, and the output pins of the frequency dividers are correspondingly connected with the input ends of the operation module one by one; the output end of the AND operation module is connected with the input end of the D trigger; the output port and the input end of the first phase inverter are both connected with the output end of the D flip-flop; the reset pin of each frequency divider and one input end of the AND operation module are connected with the output end of the first phase inverter; the control signal port comprises a plurality of input pins; and the control pins of the two frequency dividers are correspondingly connected with the input pins one by one.
Further, the frequency halver comprises a setting circuit; the reset switch control circuit is connected with the setting circuit; the frequency division circuit is connected with the reset switch control circuit; the setting circuit is used for controlling the reset switch control circuit; the reset switch control circuit is used for resetting the frequency dividing circuit.
Further, the frequency dividing circuit comprises a first CML latch, a second CML latch, a first triode, a second triode, a first constant current source and a second constant current source; the positive phase output end of the second CML latch is connected with the negative phase input end of the first CML latch; the negative phase output end of the second CML latch is connected with the positive phase input end of the first CML latch; the positive phase input end of the second CML latch is connected with the positive phase output end of the first CML latch; the negative phase input end of the second CML latch is connected with the negative phase output end of the first CML latch; a clock input pin of the second CML latch is connected with a clock input pin of the first CML latch in an inverted state; a current input pin of the first CML latch is connected with a collector of the first triode; the emitter of the first triode is connected with the anode of the first constant current source; the negative electrode of the first constant current source is grounded; a current input pin of the second CML latch is connected with a collector of the second triode; the emitter of the second triode is connected with the anode of the second constant current source; the negative electrode of the second constant current source is grounded; and the base electrode of the first triode and the base electrode of the second triode are both connected with the output end of the first phase inverter.
Further, the reset switch control circuit comprises a third triode, a fourth triode, a fifth triode, a sixth triode, a seventh triode and an eighth triode; the collector of the third triode is connected with the negative phase output end of the first CML latch; a collector of the fourth triode is connected with a positive phase output end of the first CML latch; an emitting electrode of the third triode and an emitting electrode of the fourth triode are both connected with a collecting electrode of the fifth triode; an emitting electrode of the fifth triode is connected with the positive electrode of the first constant current source; the collector of the sixth triode is connected with the negative phase output end of the second CML latch; a collector of the seventh triode is connected with a positive phase output end of the second CML latch; an emitter of the sixth triode and an emitter of the seventh triode are both connected with a collector of the eighth triode; an emitting electrode of the eighth triode is connected with the positive electrode of the second constant current source; the base electrode of the third triode and the base electrode of the sixth triode are both connected with the first output end of the setting circuit; and the base electrode of the fourth triode and the base electrode of the seventh triode are both connected with the second output end of the setting circuit.
Further, the setting circuit comprises a first resistor, a second inverter, a first MOS (metal oxide semiconductor) transistor, a second MOS transistor and a third constant current source; the first end of the first resistor and the first end of the second resistor are both connected with an input power supply; the second end of the first resistor is connected with the drain electrode of the first MOS tube; the second end of the second resistor is connected with the drain electrode of the second MOS tube; the input end of the second phase inverter and the grid electrode of the first MOS tube are both connected with the control pin; the output end of the second inverter is connected with the grid electrode of the second MOS tube; the source electrode of the first MOS tube and the source electrode of the second MOS tube are both connected with the anode of the third constant current source; the negative electrode of the third constant current source is grounded; the first output end of the setting circuit is connected with the drain electrode of the first MOS tube; and the second output end of the setting circuit is connected with the drain electrode of the second MOS tube.
Further, the and operation module comprises a plurality of and gates; and the output of each frequency divider in the asynchronous frequency division module is subjected to AND operation by the output of the plurality of AND gates and the output of the first phase inverter and then is input to the input end of the D trigger.
Further, the asynchronous frequency division module comprises a first frequency divider, a second frequency divider, a third frequency divider and a fourth frequency divider; the AND operation module comprises a first AND gate and a second AND gate; a clock pin of the first frequency divider is connected with the clock port; a clock pin of the second frequency divider is connected with an output pin of the first frequency divider; a clock pin of the third frequency divider is connected with an output pin of the second frequency divider; a clock pin of the fourth frequency divider is connected with an output pin of the third frequency divider; the output pins of the first frequency divider, the second frequency divider and the third frequency divider are connected with the input pins of the first AND gate in a one-to-one correspondence manner; and the output pin of the fourth frequency divider, the output end of the first inverter, the output pin of the first AND gate and the input pin of the second AND gate are connected in a one-to-one correspondence manner.
In a second aspect, the present invention provides a frequency-division apparatus, including a controller; an input device connected to the controller; and the CML high-speed wide-range asynchronous frequency divider is connected with the controller.
In a third aspect, the present invention provides an electronic device, which includes a package housing and the frequency divider disposed in the package housing.
The beneficial effects that the invention can realize are as follows: the invention uses asynchronous frequency divider of current mode structure, connects the output pin of former two-stage frequency divider to the clock pin of next stage; the power consumption of the frequency divider can be reduced step by step; and the AND operation module is used for performing AND operation on the phase reversal of the clock output on the D trigger and the output of each frequency divider, the D trigger is used for outputting signals after the triggering requirements of the D trigger are met, the signals output by the D trigger are output to the reset pins of each frequency divider through the phase inverter to control the reset of the frequency dividers, and the signals meet the requirements of 1 to 2 n The operating efficiency of the frequency divider is improved in the case of a division ratio of-1.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the embodiments of the present invention will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained according to the drawings without inventive efforts.
Fig. 1 is a schematic diagram of a topology structure of a CML high-speed wide-range asynchronous frequency divider according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a CML high-speed wide-range asynchronous frequency divider according to an embodiment of the present invention;
fig. 3 is a schematic diagram of a frequency halving divider according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a latch according to an embodiment of the present invention.
An icon: 10-CML high speed wide range asynchronous frequency divider; 100-clock signal port; 200-a control signal port; 300-asynchronous frequency division module; 310-a frequency divider; 311-a set circuit; 3111-a second inverter; 312-reset switch control circuit; 313-a frequency divider circuit; 400-and operation module; a 500-D flip-flop; 600-a first inverter; 700-output port.
Detailed Description
The technical solutions in the embodiments of the present invention will be described below with reference to the drawings in the embodiments of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present invention, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
Referring to fig. 1 and fig. 2, fig. 1 is a schematic diagram of a topology structure of a CML high-speed wide-range asynchronous frequency divider according to an embodiment of the present invention; fig. 2 is a schematic diagram of a CML high-speed wide-range asynchronous frequency divider according to an embodiment of the present invention.
In one embodiment, the CML high-speed wide-range asynchronous frequency divider 10 provided by the embodiment of the present invention includes a clock signal port 100, a control signal port 200, an asynchronous frequency dividing module 300, an and operation module 400, a D flip-flop 500, a first inverter 600, and an output port 700; the asynchronous frequency division module 300 includes several dividers 310; the clock pin of the first frequency divider and the clock pin of the D flip-flop 500 are both connected to the clock signal port 100, the clock pin of each subsequent frequency divider is connected to the output pin of the previous frequency divider, and the output pins of each frequency divider are connected to the respective input terminals of the operation module 400 in a one-to-one correspondence manner; the output end of the and operation module 400 is connected with the input end of the D flip-flop 500; the input ends of the output port 700 and the first inverter 600 are both connected to the output end of the D flip-flop 500; the reset pin of each frequency halver and one input end of the operation module 400 are both connected with the output end of the first inverter 600; control signal port 200 includes a plurality of input pins; and the control pins of the two frequency dividers are correspondingly connected with the input pins one by one.
In the above manner, the output of each frequency divider is subjected to and logical operation, and then the output is sent to the D flip-flop 500; the output is output through the output port 700 on the one hand and through the first inverter 600 to the reset pin of each frequency divider and to one output pin of the and operation block 400 on the other hand.
In one embodiment, the and operation module includes a plurality of and gates; and the output of each frequency halver in the asynchronous frequency division module is subjected to AND operation through a plurality of AND gates and the output of the first phase inverter and then is input into the input end of the D trigger.
Illustratively, as shown in fig. 2, the asynchronous frequency division module 300 includes a first frequency divider, a second frequency divider, a third frequency divider, and a fourth frequency divider; the AND operation module comprises a first AND gate AND1 AND a second AND gate AND2; a clock pin of the first and second frequency dividers is connected with a clock port; a clock pin of the second frequency divider is connected with an output pin of the first frequency divider; a clock pin of the third frequency divider is connected with an output pin of the second frequency divider; a clock pin of the fourth frequency divider is connected with an output pin of the third frequency divider; the output pin of the first two-frequency divider, the output pin of the second two-frequency divider AND the output pin of the third two-frequency divider are connected with the input pins of the first AND gate AND1 in a one-to-one correspondence manner; an output pin of the fourth frequency divider, an output end of the first inverter, an output pin of the first AND gate AND1 AND an input pin of the second AND gate AND2 are connected in a one-to-one correspondence manner.
The division ratio of the frequency divider may be preset by a control word SEL < N > (N is a positive integer greater than 1) input through respective input pins of the control signal port 200. Specifically, 4 frequency dividers may be set according to the method shown in fig. 2, when a frequency division ratio of 10 needs to be set, the control word SEL < N > from the first frequency divider to the fourth frequency divider is 0101 from low to high, in a reset state of the frequency divider, the nth frequency divider will reset the output to the negation of the current control word SEL < N >, and then the initial state is 1010 from low to high. Each input clock can add 1 to the value, the output state of each output pin of the two frequency dividers after each clock period comes is subjected to AND operation, only when the output of all the two frequency dividers is high level, a rising edge is output to the D flip-flop 500, at the moment, the D flip-flop 500 outputs a high level, the high level is input to the reset pin of each two frequency divider after the output of all the two frequency dividers is inverted to low level through the first inverter 600, the reset pin is immediately reset to the initial state, when the next input clock comes, the D flip-flop 500 jumps to low level again, and one period is finished. The output end of the first inverter 600 is connected with the input end of the corresponding AND gate in the operation module, so that the delay from one clock to the output of the two-frequency divider is reduced. When the output of each frequency divider is high, the input of the D flip-flop 500 is high, the next clock comes to the output Fout of the D flip-flop 500 to be high, the output of the AND gate is low after passing through the inverter, the next clock comes to the output Fout of the D flip-flop 500 to be low, and the reset is finished. The reduced propagation delay is more pronounced with more stages of the frequency divider and more stages of the and gate.
It should be noted that the foregoing embodiment is only an example provided by the present invention, and the and operation module may select a required component according to an actual use requirement. For convenience of use, a chip with multiple AND gates may be selected. For example, when the number of the dividers of the asynchronous frequency division module 300 is 7, an 8-input 1-output and gate chip may be selected; an integrated chip with three 3-in 1-out AND gates (e.g., a 74X11 chip) may also be used. When an integrated chip with three 3-input-1-output and gates is used, the outputs of the first to third frequency dividers connected from the clock signal port 100 are connected with the respective input pins of the first 3-input-1-output and gate in a one-to-one correspondence; the outputs of the third frequency divider to the sixth frequency divider are correspondingly connected with the input pins of the second 3-input 1-output AND gate one by one; the output pin of the first 3-input-1-output AND gate, the output pin of the second 3-input-1-output AND gate and the output end of the first inverter are connected with the input pins of the third 3-input-1-output AND gate in a one-to-one correspondence manner; and the output pin of the third 3-input-1-output AND gate is connected with the input end of the D trigger.
Referring to fig. 3 and 4, fig. 3 is a schematic diagram of a frequency divider according to an embodiment of the present invention; fig. 4 is a schematic diagram of a latch according to an embodiment of the present invention.
As shown in fig. 3, in one embodiment, the divide-by-two divider 310 includes a set circuit 311; a reset switch control circuit 312 connected to the set circuit 311; a frequency dividing circuit 313 connected to the reset switch control circuit 312; the setting circuit 311 is used to control the reset switch control circuit 312; the reset switch control circuit 312 is used to reset the frequency dividing circuit 313.
In one embodiment, the frequency divider circuit 313 includes a first CML LATCH (CML-LATCH 1), a second CML LATCH (CML-LATCH 2), a first transistor Q1, a second transistor Q2, and a first constant current source ISS1 and a second constant current source ISS2; the positive phase output end of the second CML LATCH (CML-LATCH 2) is connected with the negative phase input end of the first CML LATCH (CML-LATCH 1); the negative phase output end of the second CML LATCH (CML-LATCH 2) is connected with the positive phase input end of the first CML LATCH (CML-LATCH 1); the positive phase input end of the second CML LATCH (CML-LATCH 2) is connected with the positive phase output end of the first CML LATCH (CML-LATCH 1); the negative phase input end of the second CML LATCH (CML-LATCH 2) is connected with the negative phase output end of the first CML LATCH (CML-LATCH 1); a clock input pin of the second CML LATCH (CML-LATCH 2) is connected with a clock input pin of the first CML LATCH (CML-LATCH 1); a current input pin of a first CML LATCH (CML-LATCH 1) is connected with a collector electrode of a first triode Q1; an emitting electrode of the first triode Q1 is connected with the anode of the first constant current source ISS 1; the negative electrode of the first constant current source ISS1 is grounded; a current input pin of a second CML LATCH (CML-LATCH 2) is connected with a collector of a second triode Q2; an emitting electrode of the second triode Q2 is connected with the anode of a second constant current source ISS2; the negative electrode of the second constant current source ISS2 is grounded; the base of the first transistor Q1 and the base of the second transistor Q2 are both connected to the output of the first inverter 600.
In one embodiment, the reset switch control circuit 312 includes a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, and an eighth transistor Q8; the collector of the third triode Q3 is connected with the negative phase output end of the first CML LATCH (CML-LATCH 1); a collector of the fourth triode Q4 is connected with a positive phase output end of the first CML LATCH (CML-LATCH 1); an emitting electrode of the third triode Q3 and an emitting electrode of the fourth triode Q4 are both connected with a collecting electrode of the fifth triode Q5; an emitting electrode of the fifth triode Q5 is connected with the positive electrode of the first constant current source ISS 1; a collector of the sixth triode Q6 is connected with the negative phase output end of the second CML LATCH (CML-LATCH 2); a collector of the seventh triode Q7 is connected with a non-inverting output end of the second CML LATCH (CML-LATCH 2); an emitting electrode of the sixth triode Q6 and an emitting electrode of the seventh triode Q7 are both connected with a collecting electrode of the eighth triode Q8; an emitting electrode of the eighth triode Q8 is connected with the anode of the second constant current source ISS2; the base of the third triode Q3 and the base of the sixth triode Q6 are both connected with the first output end of the setting circuit 311; the base of the fourth triode Q4 and the base of the seventh triode Q7 are both connected to the second output terminal of the set circuit 311.
In one embodiment, the setting circuit 311 includes a first resistor R1, a second resistor R2, a second inverter 3111, a first MOS transistor M1, a second MOS transistor M2, and a third constant current source ISS3; the first end of the first resistor R1 and the first end of the second resistor R2 are both connected with an input power supply VDD; the second end of the first resistor R1 is connected with the drain electrode of the first MOS transistor M1; the second end of the second resistor R2 is connected with the drain electrode of the second MOS transistor M2; the input end of the second inverter 3111 and the gate of the first MOS transistor are both connected to a control pin; the output end of the second inverter 3111 is connected to the gate of the second MOS transistor M2; the source electrode of the first MOS tube M1 and the source electrode of the second MOS tube M2 are both connected with the anode of a third constant current source ISS3; the negative electrode of the third constant current source ISS3 is grounded; a first output end of the setting circuit 311 is connected with a drain electrode of the first MOS transistor M1; a second output terminal of the setting circuit 311 is connected to the drain of the second MOS transistor M2.
The frequency divider uses a current mode structure with reset, and 4 BJT switching tubes Q1, Q2, Q5 and Q8 are added above a constant current source; the control signal is a RESET differential signal (comprising RESETP and RESETN), when the RESET signal RESETP is high, the halving frequency divider is RESET, and when the RESETN is high, the circuit normally works in a halving frequency dividing function. SEL < N > is a control word of the N-th-bit frequency divider, and is converted into differential signals through a first MOS tube M1, a second MOS tube M2 and resistors R1 and R2 to be connected to bases of a third switching tube Q3, a fourth switching tube Q4, a sixth switching tube Q6 and a seventh switching tube Q7 which are made of BJTs. When a reset signal RESETP is high and SEL < N > is high, a first MOS tube M1 is started, the drain voltage of the first MOS tube M1 is lower than the drain of a second MOS tube M2, a fourth switching tube Q4 and a seventh switching tube Q7 are started, the QP output by the frequency divider is pulled down, and the QN is pulled up; conversely, when SEL < N > is low, then the divide-by-two output QP is pulled high and QN is pulled low.
The structure of the CML latch is shown in FIG. 4, the bases CP and CN of the switch tubes Q9 and Q10 are differential clock inputs, the bases DP and DN of the switch tubes Q11 and Q12 are differential data inputs, and the switch tubes Q13 and Q14 form a latch structure. When CP is high, the switch tube Q9 is conducted, and the output QN is the inverse phase of DP. When CP jumps low, Q10 is opened, and the output of QN and QP in the last state is kept until CP jumps next time.
Further, an embodiment of the present invention further provides a frequency division apparatus, where the frequency division apparatus includes a controller; an input device connected to the controller; and the CML high-speed wide-range asynchronous frequency divider is connected with the controller.
Further, an embodiment of the present invention further provides an electronic device, which includes a package housing and the frequency dividing apparatus disposed in the package housing.
In summary, the embodiments of the present invention provide a CML high-speed wide-range asynchronous frequency divider, a frequency dividing apparatus, and an electronic device, including a clock signal port, a control signal port, an asynchronous frequency dividing module, an and operation module, a D flip-flop, a first inverter, and an output port; the asynchronous frequency division module comprises a plurality of frequency dividers; the clock pin of the first frequency divider and the clock pin of the D trigger are connected with the clock signal port, the clock pin of each subsequent frequency divider is connected with the output pin of the previous frequency divider, and the output pins of the frequency dividers are correspondingly connected with the input ends of the operation module one by one; the output end of the operation module is connected with the input end of the D trigger; the output port and the input end of the first inverter are both connected with the output end of the D flip-flop; the reset pin of each frequency halver and one input end of the operation module are connected with the output end of the first phase inverter; the control signal port comprises a plurality of input pins; and the control pins of the two frequency dividers are correspondingly connected with the input pins one by one. By the mode, the power consumption of the frequency divider is reduced while the working efficiency of the frequency divider is improved.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (9)
1. A CML high-speed wide-range asynchronous frequency divider is characterized by comprising a clock signal port, a control signal port, an asynchronous frequency dividing module, an AND operation module, a D trigger, a first inverter and an output port; the asynchronous frequency division module comprises a plurality of frequency dividers; the clock pin of the first frequency divider and the clock pin of the D trigger are both connected with the clock signal port, the clock pin of each subsequent frequency divider is connected with the output pin of the previous frequency divider, and the output pins of the frequency dividers are correspondingly connected with the input ends of the operation module one by one; the output end of the AND operation module is connected with the input end of the D trigger; the output port and the input end of the first phase inverter are both connected with the output end of the D flip-flop; the reset pin of each frequency divider and one input end of the AND operation module are connected with the output end of the first phase inverter; the control signal port comprises a plurality of input pins; and the control pins of the two frequency dividers are correspondingly connected with the input pins one by one.
2. The CML high speed wide range asynchronous frequency divider of claim 1, wherein the divide-by-two divider comprises a set circuit; the reset switch control circuit is connected with the setting circuit; the frequency division circuit is connected with the reset switch control circuit; the setting circuit is used for controlling the reset switch control circuit; the reset switch control circuit is used for resetting the frequency dividing circuit.
3. The CML high speed wide range asynchronous frequency divider of claim 2, the frequency dividing circuit comprising a first CML latch, a second CML latch, a first transistor, a second transistor, a first constant current source, and a second constant current source; the positive phase output end of the second CML latch is connected with the negative phase input end of the first CML latch; the negative phase output end of the second CML latch is connected with the positive phase input end of the first CML latch; the positive phase input end of the second CML latch is connected with the positive phase output end of the first CML latch; the negative phase input end of the second CML latch is connected with the negative phase output end of the first CML latch; a clock input pin of the second CML latch is connected with a clock input pin of the first CML latch in an inverted state; a current input pin of the first CML latch is connected with a collector of the first triode; the emitting electrode of the first triode is connected with the positive electrode of the first constant current source; the negative electrode of the first constant current source is grounded; the current input pin of the second CML latch is connected with the collector of the second triode; the emitting electrode of the second triode is connected with the positive electrode of the second constant current source; the negative electrode of the second constant current source is grounded; and the base electrode of the first triode and the base electrode of the second triode are both connected with the output end of the first phase inverter.
4. The CML high speed wide range asynchronous frequency divider of claim 3, wherein the reset switch control circuit comprises a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor; the collector of the third triode is connected with the negative phase output end of the first CML latch; a collector of the fourth triode is connected with a positive phase output end of the first CML latch; an emitting electrode of the third triode and an emitting electrode of the fourth triode are both connected with a collector electrode of the fifth triode; an emitting electrode of the fifth triode is connected with the positive electrode of the first constant current source; the collector of the sixth triode is connected with the negative phase output end of the second CML latch; a collector of the seventh triode is connected with a positive phase output end of the second CML latch; an emitter of the sixth triode and an emitter of the seventh triode are both connected with a collector of the eighth triode; an emitting electrode of the eighth triode is connected with the positive electrode of the second constant current source; the base electrode of the third triode and the base electrode of the sixth triode are both connected with the first output end of the setting circuit; and the base electrode of the fourth triode and the base electrode of the seventh triode are both connected with the second output end of the setting circuit.
5. The CML high-speed wide-range asynchronous frequency divider of claim 4, wherein the set circuit comprises a first resistor, a second inverter, a first MOS transistor, a second MOS transistor, and a third constant current source; the first end of the first resistor and the first end of the second resistor are both connected with an input power supply; the second end of the first resistor is connected with the drain electrode of the first MOS tube; the second end of the second resistor is connected with the drain electrode of the second MOS tube; the input end of the second phase inverter and the grid electrode of the first MOS tube are both connected with the control pin; the output end of the second phase inverter is connected with the grid electrode of the second MOS tube; the source electrode of the first MOS tube and the source electrode of the second MOS tube are both connected with the anode of the third constant current source; the negative electrode of the third constant current source is grounded; the first output end of the setting circuit is connected with the drain electrode of the first MOS tube; and the second output end of the setting circuit is connected with the drain electrode of the second MOS tube.
6. The CML high-speed wide-range asynchronous frequency divider of claim 1, wherein the and operation module comprises a plurality of and gates; and the output of each frequency divider in the asynchronous frequency division module is subjected to AND operation through the outputs of the plurality of AND gates and the first inverter and then is input into the input end of the D trigger.
7. The CML high speed wide range asynchronous frequency divider of claim 6, wherein the asynchronous frequency division module comprises a first frequency divider, a second frequency divider, a third frequency divider, and a fourth frequency divider; the AND operation module comprises a first AND gate and a second AND gate; a clock pin of the first frequency divider is connected with the clock port; a clock pin of the second frequency divider is connected with an output pin of the first frequency divider; a clock pin of the third frequency halver is connected with an output pin of the second frequency halver; a clock pin of the fourth frequency divider is connected with an output pin of the third frequency divider; the output pins of the first frequency divider, the second frequency divider and the third frequency divider are connected with the input pins of the first AND gate in a one-to-one correspondence manner; and the output pin of the fourth frequency divider, the output end of the first inverter, the output pin of the first AND gate and the input pin of the second AND gate are connected in a one-to-one correspondence manner.
8. A frequency-splitting apparatus, comprising a controller; an input device connected to the controller; and a CML high speed wide range asynchronous frequency divider as claimed in any one of claims 1 to 7 connected to the controller.
9. An electronic device comprising an enclosure and the crossover of claim 8 disposed within the enclosure.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0276794A2 (en) * | 1987-01-25 | 1988-08-03 | Nec Corporation | Data input circuit having latch circuit |
| US6411669B1 (en) * | 2000-05-25 | 2002-06-25 | C&S Technology Co., Ltd. | Dual-modulus prescaler for RF synthesizer |
| CN101378258A (en) * | 2007-08-29 | 2009-03-04 | 中国科学院电子学研究所 | Modularization frequency division unit and frequency divider |
| CN101944907A (en) * | 2010-09-09 | 2011-01-12 | 东南大学 | Glitch-eliminating programmable counter |
| CN102324930A (en) * | 2011-05-12 | 2012-01-18 | 西安电子科技大学 | Superspeed 8/9 bimodule prescaler based on GaAa hetero junction bipolar transistor (HBT) device |
| CN102739239A (en) * | 2012-06-15 | 2012-10-17 | 江苏物联网研究发展中心 | High-speed low power consumption true single-phase clock 2D type two-thirds dual-mode frequency divider |
| CN103825610A (en) * | 2013-11-27 | 2014-05-28 | 无锡芯响电子科技有限公司 | Dividing two frequency divider circuit based on current mirror switch logic |
| CN111684771A (en) * | 2017-09-18 | 2020-09-18 | 英特尔公司 | Time-coded data communication protocol, apparatus and method for generating and receiving data signals |
-
2020
- 2020-11-10 CN CN202011247752.XA patent/CN112636746B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0276794A2 (en) * | 1987-01-25 | 1988-08-03 | Nec Corporation | Data input circuit having latch circuit |
| US6411669B1 (en) * | 2000-05-25 | 2002-06-25 | C&S Technology Co., Ltd. | Dual-modulus prescaler for RF synthesizer |
| CN101378258A (en) * | 2007-08-29 | 2009-03-04 | 中国科学院电子学研究所 | Modularization frequency division unit and frequency divider |
| CN101944907A (en) * | 2010-09-09 | 2011-01-12 | 东南大学 | Glitch-eliminating programmable counter |
| CN102324930A (en) * | 2011-05-12 | 2012-01-18 | 西安电子科技大学 | Superspeed 8/9 bimodule prescaler based on GaAa hetero junction bipolar transistor (HBT) device |
| CN102739239A (en) * | 2012-06-15 | 2012-10-17 | 江苏物联网研究发展中心 | High-speed low power consumption true single-phase clock 2D type two-thirds dual-mode frequency divider |
| CN103825610A (en) * | 2013-11-27 | 2014-05-28 | 无锡芯响电子科技有限公司 | Dividing two frequency divider circuit based on current mirror switch logic |
| CN111684771A (en) * | 2017-09-18 | 2020-09-18 | 英特尔公司 | Time-coded data communication protocol, apparatus and method for generating and receiving data signals |
Non-Patent Citations (2)
| Title |
|---|
| Chip design of a 5.8-GHz fractional-N frequency synthesizer with a tunable G_m-C loop filter;Jingfang Huang等;《Chinese Physics B》;20120815(第08期);255-261 * |
| 一种2.4G的低功耗BiCMOS预置数分频器;汪猛等;《微电子学与计算机》;20060420(第03期);114-120 * |
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