CN112636732B - Power-off delay protection circuit and device - Google Patents
Power-off delay protection circuit and device Download PDFInfo
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- CN112636732B CN112636732B CN202011575732.5A CN202011575732A CN112636732B CN 112636732 B CN112636732 B CN 112636732B CN 202011575732 A CN202011575732 A CN 202011575732A CN 112636732 B CN112636732 B CN 112636732B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/28—Modifications for introducing a time delay before switching
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
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Abstract
The invention discloses a power-off delay protection circuit and a power-off delay protection device, which are used for solving the problem that power cannot be off when a main control chip is used for controlling delay power-off in the prior art. The circuit includes: the main control unit is used for receiving a trigger signal which is output by the trigger signal end and used for representing the power-off of the protected object, outputting a first switch signal for controlling the switch unit to be switched off after a first preset time, the auxiliary control unit is used for receiving the trigger signal, outputting a second switch signal for controlling the switch unit to be switched off after a second preset time, and the switch unit is used for switching off a path between a power supply end and the protected object according to the first switch signal and/or the second switch signal. Because the power-off delay protection circuit comprises the auxiliary control unit, the auxiliary control unit can output a second switching signal for controlling the switching-off of the switching unit after a second preset time, and therefore after the main control unit breaks down, the purpose of delaying power-off is achieved through the auxiliary control unit, and the failure rate is reduced.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a power-off delay protection circuit and a power-off delay protection device.
Background
The vehicle controller typically needs to save some of the data to the controller's data storage unit before powering down for recall the next time the controller is powered on. Therefore, after the user turns off the power switch of the controller, the controller cannot be powered off immediately, and the controller needs to continue to supply power for a period of time, so that the data is completely stored in the storage unit of the controller.
The current mode for controlling the delayed power-off of the vehicle controller is that a trigger signal of a trigger end is detected through a main control chip, if the level of the trigger signal of the trigger end is lower than a threshold value, the main control chip outputs a switch signal after delaying for a certain time so as to disconnect a channel between the controller and a power supply end and realize the power-off operation of the delayed controller.
However, when the main control chip cannot output a switching signal for disconnecting the path between the controller and the power supply terminal due to software or hardware problems, the controller cannot be powered off, and then the storage battery is exhausted, and the vehicle cannot be started again.
Disclosure of Invention
The invention provides a power-off delay protection circuit and a power-off delay protection device, which are used for solving the problem that a controller cannot be powered off when a main control chip is used for controlling delay power-off in the prior art.
In a first aspect, an embodiment of the present invention provides a power-down delay protection circuit, including: the system comprises a main control unit, an auxiliary control unit, a switch unit, a power supply end and a signal trigger end;
the main control unit is used for receiving a trigger signal which is output by the signal trigger end and used for representing the power-off of a protected object, and outputting a first switching signal for controlling the switching-off of the switching unit after a first preset time according to the trigger signal;
the auxiliary control unit is used for receiving the trigger signal and outputting a second switching signal for controlling the switching-off of the switching unit after a second preset time according to the trigger signal;
the switching unit is configured to break a path between the power source terminal and the protected object according to the first switching signal and/or the second switching signal.
In a possible implementation manner, the circuit further includes an and gate circuit, a first input end of the and gate circuit is connected to an output end of the main control unit, a second input end of the and gate circuit is connected to an output end of the auxiliary control unit, and an output end of the and gate circuit is connected to the switch unit, and is configured to output a third switch signal for controlling the switch unit to be turned off according to the first switch signal and the second switch signal.
In one possible implementation, the secondary control unit includes a timing control unit and a timing unit, wherein:
the timing control unit is used for receiving the trigger signal and generating a control signal for controlling the timing unit to work according to the trigger signal;
and the timing unit is used for starting to work after receiving the control signal and outputting the second switching signal after the second preset time length is reached.
In one possible implementation, the timing unit includes a timer, a resistive component, and a capacitive component, wherein:
the reset end of the timer is used as the reset end of the timing unit, the rising edge trigger input end of the timer is used as the first input end of the timing unit, the falling edge trigger input end of the timer is used as the second input end of the timing unit, and the threshold end of the timer is respectively connected with one end of the resistor assembly, the discharge end of the timer and one end of the capacitor assembly;
the other end of the resistor assembly is connected with a power supply;
the other end of the capacitor assembly is grounded.
In one possible implementation, the resistive component includes a resistor or a plurality of resistors; if the resistor comprises a plurality of resistors, the plurality of resistors are connected in parallel and/or in series; and/or
The capacitance component comprises one capacitance or a plurality of capacitances; if a plurality of capacitors are included, the plurality of capacitors are connected in parallel and/or in series.
In one possible implementation, the timing control unit includes a first switch component, a second switch component, a third switch component, and a fourth switch component, wherein:
the input end of the first switch component is connected with the signal trigger end, the power supply input end of the first switch component is connected with the power supply end, and the output end of the first switch component is connected with the input end of the second switch component and used for outputting a high-level signal according to the trigger signal;
the power supply input end of the second switch assembly is connected with the power supply end, and the output end of the second switch assembly is respectively connected with the input end of the third switch assembly and the reset end of the timing unit and used for outputting a low level signal according to the high level signal;
the power supply input end of the third switch assembly is connected with a power supply, and the output end of the third switch assembly is respectively connected with the input end of the fourth switch assembly and the first input end of the timing unit and used for outputting a high level signal according to the low level signal;
and the power input end of the fourth switch assembly is connected with the power supply, and the output end of the fourth switch assembly is connected with the second input end of the timing unit and used for outputting a low level signal according to the high level signal.
In a possible implementation manner, the first switch component includes a first switch tube, a first resistor, a second resistor, a third resistor, and a fourth resistor, the second switch component includes a second switch tube and a fifth resistor, the third switch component includes a third switch tube, a sixth resistor, a seventh resistor, and an eighth resistor, the fourth switch component includes a fourth switch tube, a ninth resistor, a tenth resistor, and an eleventh resistor, wherein,
one end of the first resistor is connected with the signal trigger end, and the other end of the first resistor is respectively connected with one end of the second resistor and the base electrode of the first switching tube;
the other end of the second resistor is grounded;
a collector of the first switch tube is connected with one end of the third resistor, and an emitter of the first switch tube is grounded;
the other end of the third resistor is respectively connected with one end of the fourth resistor and the base electrode of the second switching tube;
the other end of the fourth resistor is connected with the power supply end;
an emitting electrode of the second switching tube is connected with the power supply end, and a collector electrode of the second switching tube is connected with one end of the fifth resistor;
the other end of the fifth resistor is respectively connected with one end of the sixth resistor and the reset end of the timing unit and is grounded;
the other end of the sixth resistor is respectively connected with one end of the seventh resistor and the base electrode of the third switching tube;
the other end of the seventh resistor is grounded;
a collector of the third switching tube is respectively connected with one end of the eighth resistor, one end of the ninth resistor and the first input end of the timing unit, and a base of the third switching tube is grounded;
the other end of the eighth resistor is connected with the power supply;
the other end of the ninth resistor is connected with one end of the tenth resistor and the base electrode of the fourth switching tube respectively;
the other end of the tenth resistor is grounded;
a collector of the fourth switching tube is respectively connected with one end of the eleventh resistor and the second input end of the timing unit, and an emitter of the fourth switching tube is grounded;
the other end of the eleventh resistor is connected with the power supply.
In a possible implementation manner, the timing control unit is specifically configured to:
receiving the trigger signal, disconnecting the first switch tube, the second switch tube and the third switch tube, connecting the fourth switch tube, outputting a low level signal to a reset end of the timing unit, outputting a high level signal to a first input end of the timing unit, and outputting a low level signal to a second input end of the timing unit;
the timing unit is specifically configured to:
and outputting a low level signal after the second preset time.
In a possible implementation manner, the circuit further includes a diode, an anode of the diode is grounded, and a cathode of the diode is respectively connected to the other end of the fifth resistor, one end of the sixth resistor, and the first input end of the timing unit, so as to clamp a voltage to protect the timing unit.
In a second aspect, an embodiment of the present invention provides a power-off delay protection device, including the power-off delay protection circuit according to any one of the first aspect.
The invention has the following beneficial effects:
the embodiment of the invention provides a power-off delay protection circuit and a device, wherein the circuit comprises: the protection device comprises a main control unit, an auxiliary control unit, a switch unit, a power supply end and a signal trigger end, wherein the main control unit is used for receiving a trigger signal which is output by the trigger signal and used for representing the power-off of a protected object, outputting a first switch signal for controlling the switch unit to be disconnected after a first preset time according to the trigger signal, the auxiliary control unit is used for receiving the trigger signal, outputting a second switch signal for controlling the switch unit to be disconnected after a second preset time according to the trigger signal, and the switch unit is used for disconnecting a path between the power supply end and the protected object according to the first switch signal and/or the second switch signal. The power-off delay protection circuit provided by the embodiment of the invention comprises the auxiliary control unit, and the auxiliary control unit can output the second switching signal for controlling the switching-off of the switching unit after the second preset time, so that the double protection can be realized for the protected object by delaying power-off, and after the main control unit breaks down, the purpose of delaying power-off is realized through the auxiliary control unit, and the failure rate is reduced.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic diagram of a power-down delay protection circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another power-down delay protection circuit according to an embodiment of the present invention;
fig. 3 is a schematic diagram of an auxiliary control unit in a power-down delay protection circuit according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating a timing control unit according to an embodiment of the present invention;
FIG. 5 is a diagram of another timing control unit according to an embodiment of the present invention;
fig. 6 is a schematic diagram of another power-down delay protection circuit according to an embodiment of the present invention;
fig. 7 is a timing diagram of a power-down delay protection circuit according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the present invention will be described in further detail with reference to the accompanying drawings, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the automobile transmitter controller, a relay is connected between a power supply and the controller, and the power supply supplies power to and cuts off the power of the controller by controlling the on and off of the relay. Generally, a single chip microcomputer is adopted to control the on and off of a relay, the single chip microcomputer detects an electric signal under a controller, and then after a certain time delay, a signal for controlling the off of the relay is output, so that the relay is disconnected from a channel between a power supply and the controller.
If the singlechip breaks down, for example the procedure goes wrong, or hardware itself goes wrong, then can not output the signal of control relay disconnection, if the relay does not break off always, then the power can be for the controller power supply always, and the power for the controller power supply usually is the battery, and the power supply always then can lead to the battery electric quantity to exhaust, can't get off the car once more.
In view of the foregoing problems, an embodiment of the present invention provides a power-off delay protection circuit, as shown in fig. 1, including a main control unit 101, an auxiliary control unit 102, a switch unit 103, a power supply terminal, and a signal trigger terminal, where:
the main control unit 101 is configured to receive a trigger signal, which is output by the signal trigger end and used for representing power-off of the protected object, and output a first switching signal for controlling the switching unit 103 to be switched off after a first preset time period according to the trigger signal;
the auxiliary control unit 102 is configured to receive a trigger signal output by the trigger end, and output a second switching signal for controlling the switching unit 103 to be turned off after a second preset time according to the trigger signal;
a switching unit 103 for breaking a path between the power source terminal and the object to be protected according to the first switching signal and/or the second switching signal.
The power-off delay protection circuit provided by the embodiment of the invention comprises the auxiliary control unit, and the auxiliary control unit can output the second switching signal for controlling the switching-off of the switching unit after the second preset time, so that the double protection can be realized for the protected object by delaying power-off, and after the main control unit breaks down, the purpose of delaying power-off is realized through the auxiliary control unit, and the failure rate is reduced.
The trigger signal in the embodiment of the present invention may be a level signal, the main control unit 101 may be a single chip microcomputer, a first preset time is configured in the single chip microcomputer, and when the single chip microcomputer detects that the level signal of the trigger end is lower than a preset value, a first switch signal is output after the first preset time; the switching unit 103 may be a relay.
As shown in fig. 2, a first input end of the and circuit 201 is connected to an output end of the main control unit 101, a second input end of the and circuit 201 is connected to an output end of the auxiliary control unit 102, an output end of the and circuit 201 is connected to the switch unit 103, and the and circuit 201 is configured to output a third switch signal for controlling the switch unit 103 to be turned off according to the first switch signal and the second switch signal.
In a specific implementation, the control relay may disconnect the path between the power source terminal and the protected object when the switching signal is a low-level signal. That is, the relay can be controlled to be turned off when the first switching signal is at a low level, the relay can be controlled to be turned off when the second switching signal is at a low level, and the relay can be controlled to be turned off when the third switching signal is at a low level.
If the power-off delay protection circuit provided by the embodiment of the present invention includes the and circuit 201, when one of the first switch signal and the second switch signal is a low level signal, the third switch signal is a low level signal, and the relay may be controlled to be turned off.
In the embodiment of the present invention, the first preset time period may be less than the second preset time period, that is, when the first preset time period arrives, the main control unit outputs the first switch signal, and if the first switch signal is a low level signal, the relay is controlled to be turned off, if the main control unit 101 fails, the low level signal cannot be output, but a high level signal is output, when the second preset time period arrives, the auxiliary control unit 102 outputs the second switch signal, and if the second switch signal is a low level, the high level input by the first input end and the low level input by the second input end of the and gate circuit 201, and the third switch signal is a low level, the relay is controlled to be turned off.
The method is adopted to control the relay to be disconnected, so that a path between a power supply and a protected object is disconnected in a delayed mode, the purpose of delayed power-off can be achieved through the auxiliary control unit after the main control unit breaks down, and failure rate is reduced.
As shown in fig. 3, the auxiliary control unit 102 in the power-down delay protection circuit provided in the embodiment of the present invention may include a timing control unit 301 and a timing unit 302, where:
a timing control unit 301, configured to receive a trigger signal, and generate a control signal for controlling the timing unit to operate according to the trigger signal;
the timing unit 302 is configured to start working after receiving the control signal, and output a second switching signal after a second preset time length is reached.
The second preset duration here may be set according to the structure of the timing unit itself.
The timing unit 302 may include a timer 3021, a resistive component 3022, and a capacitive component 3023, wherein:
a reset terminal MR of the timer 3021 serves as a reset terminal of the timing unit 302, a rising edge trigger input terminal a of the timer 3021 serves as a first input terminal of the timing unit 302, a falling edge trigger input terminal B of the timer 3021 serves as a second input terminal of the timing unit 302, and a threshold terminal TH of the timer is respectively connected to one terminal of the resistor component 3022, the discharge terminal DIS of the timer, and one terminal of the capacitor component 3023;
the other end of the resistor assembly 3022 is connected to a 5V power supply, and the other end of the capacitor assembly 3023 is grounded.
The second preset time period in the embodiment of the present invention may be determined according to the parameter of the resistor in the resistor assembly 3022 and the parameter of the capacitor in the capacitor assembly 3023, and may be determined by the charging and discharging time of the capacitor in the capacitor assembly 3023. That is, the time period for charging the capacitor is the second preset time period.
In one possible implementation, as shown in fig. 4, the timing control unit 301 may include a first switch component 401, a second switch component 402, a third switch component 403, and a fourth switch component 404, where:
the input end of the first switch component 401 is connected with the signal trigger end, the power input end of the first switch component 401 is connected with the power end, and the output end of the first switch component 401 is connected with the input end of the second switch component 402, and is used for outputting a high-level signal according to the trigger signal;
a power input end of the second switching component 402 is connected with a power end, and an output end of the second switching component 402 is respectively connected with an input end of the third switching component 403 and a reset end MR of the timing unit 302, and is configured to output a low-level signal according to a high-level signal;
a power input end of the third switching component 403 is connected with a 5V power supply, and an output end of the third switching component 403 is respectively connected with an input end of the fourth switching component 404 and a first input end of the timing unit 302, and is configured to output a high level signal according to the low level signal;
the power input terminal of the fourth switch component 404 is connected to the 5V power supply, and the output terminal of the fourth switch component 404 is connected to the second input terminal of the timing unit 302, and is configured to output a low level signal according to the high level signal.
It should be noted that, in the embodiment of the present invention, the trigger signal is a low level signal.
Specifically, as shown in fig. 4, the first switch assembly 401 includes a first switch tube Q1, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4, the second switch assembly 402 includes a second switch tube Q2 and a fifth resistor R5, the third switch assembly 403 includes a third switch tube Q3, a sixth resistor R6, a seventh resistor R7, and an eighth resistor R8, and the fourth switch assembly 404 includes a fourth switch tube Q4, a ninth resistor R9, a tenth resistor R10, and an eleventh resistor R11, wherein,
one end of the first resistor R1 is connected with the signal trigger end, and the other end of the first resistor R1 is respectively connected with one end of the second resistor R2 and the base electrode of the first switching tube Q1;
the other end of the second resistor R2 is grounded;
a collector of the first switch tube Q1 is connected with one end of the third resistor R3, and an emitter of the first switch tube Q1 is grounded;
the other end of the third resistor R3 is respectively connected with one end of the fourth resistor R4 and the base electrode of the second switching tube Q2;
the other end of the fourth resistor R4 is connected with a power supply end;
an emitting electrode of the second switching tube Q2 is connected with a power supply end, and a collector electrode of the second switching tube Q2 is connected with one end of the fifth resistor R5;
the other end of the fifth resistor R5 is connected to one end of the sixth resistor R6 and the reset end MR of the timing unit 302, and is grounded;
the other end of the sixth resistor R6 is connected with one end of the seventh resistor R7 and the base of the third switching tube Q3 respectively;
the other end of the seventh resistor R7 is grounded;
a collector of the third switching tube Q3 is connected to one end of the eighth resistor R8, one end of the ninth resistor R9, and the first input end of the timing unit 302, respectively, and a base of the third switching tube Q3 is grounded;
the other end of the eighth resistor R8 is connected with a 5V power supply;
the other end of the ninth resistor R9 is connected with one end of the tenth resistor R10 and the base of the fourth switching tube Q4 respectively;
the other end of the tenth resistor R10 is grounded;
a collector of the fourth switching tube Q4 is connected to one end of the eleventh resistor R11 and the second input end of the timing unit 302, respectively, and an emitter of the fourth switching tube Q4 is grounded;
the other end of the eleventh resistor R11 is connected to a 5V power supply.
The first switching tube Q1 is an NPN-type triode, and the second switching tube Q2, the third switching tube Q3 and the fourth switching tube Q4 are PNP-type triodes.
Based on the structure of the timing control unit 301 disclosed in fig. 4, the timing control unit 301 is specifically configured to:
when a trigger signal (low level) is received, the first switching tube Q1, the second switching tube Q2 and the third switching tube Q3 are turned off, the fourth switching tube Q4 is turned on, a low level signal is output to the reset terminal MR of the timing unit 302, a high level signal is output to the first input terminal of the timing unit 302, and a low level signal is output to the second input terminal of the timing unit 302.
The timing unit 302 is specifically configured to:
and outputting a low level signal after a second preset time.
As shown in fig. 5, the power-down delay protection circuit according to the embodiment of the present invention may further include a diode D, an anode of the diode D is grounded, and a cathode of the diode D is respectively connected to the other end of the fifth resistor R5, one end of the sixth resistor R6, and the first input end of the timing unit 302, so as to clamp a voltage and prevent the voltage at the MR from being too large and damaging the timer.
For ease of understanding, the present invention is described below in terms of specific examples.
1. And (3) electrifying control process:
as shown in fig. 6, the signal trigger terminal outputs a high level, the MCU is powered on, and the power module starts to operate to generate a 5V power supply voltage.
The signal trigger end outputs the high level, MCU outputs the high level, and the relay switches on, and the power of being connected with the power end is the controller power supply.
The signal trigger end outputs high level, the triodes Q1, Q2 and Q3 are sequentially conducted, the MR voltage is high level, the A position is low level, the B position is high level, and the timer outputs high level.
The high level output by the MCU and the high level output by the timer output through the AND gate circuit, the relay is controlled to be switched on, and a path between a power supply end and the controller is switched on, so that the controller is powered on.
2. Hardware power-down delay.
Signal trigger end output low level, triode Q1, Q2, Q3 closes in proper order, triode Q4 switches on, MR department voltage becomes the low level by the high level, A department voltage becomes the high level by the low level, B department voltage becomes the low level by the high level, the timer produces high level square wave pulse, after holding time second preset duration T2, output low level, the low level passes through AND gate circuit after, output low level, the disconnection of control relay, break off the route between power supply end and the controller, make the controller outage.
3. And (5) delaying the power-off of software.
The signal trigger end outputs a low level, the MCU identifies the signal trigger end as a low level signal and then enters a software delay stage, the delay time is a first preset time length T1, and T1 can be smaller than T2. And in the T1 time, the controller performs data storage and other operations, after the operation is finished, the MCU outputs a low level, the low level output by the MCU outputs a low level after passing through the AND gate circuit, the relay is controlled to be disconnected, and a path between a power supply end and the controller is disconnected, so that the controller is powered off.
4. The hardware forces the power down.
In the software delay process, due to software reasons or hardware reasons, the MCU detects that the signal trigger end cannot output a low level after a first preset time length T1 after outputting a low level signal, due to the existence of the hardware timing control unit and the timing unit, the timer outputs a low level after the time length T2-T1, the low level output by the timer outputs a low level after passing through the AND gate circuit, the relay is controlled to be disconnected, a passage between a power supply end and the controller is disconnected, and the controller is powered off.
FIG. 7 is a timing comparison diagram of power-down delay. As can be seen from fig. 7, when the signal trigger terminal is at a high level, the timer MR is at a high level, the input terminal a is at a low level, the input terminal B is at a high level, the MCU outputs a high level, and the timer outputs a high level;
when the signal trigger end is changed from high level to low level, MR is changed from high level to low level, A is changed from low level to high level, B is changed from high level to low level, MCU outputs low level after delay time T1, and the timer outputs low level after delay time T2, wherein T1 is less than T2.
After the power-off delay circuit disclosed by the invention is used, the probability that the controller cannot be powered off due to software or hardware of the MCU can be greatly reduced, and the fault tolerance of the software and hardware of the controller is reduced while the reliability of the controller is improved.
Further, an embodiment of the present invention further provides a power-off delay protection device, including any one of the power-off delay protection circuits described above.
It should be noted that the power-off delay protection device may be an engine controller.
The present application is described above with reference to block diagrams and/or flowchart illustrations of methods, apparatus (systems) and/or computer program products according to embodiments of the application. It will be understood that one block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, and/or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer and/or other programmable data processing apparatus, create means for implementing the functions/acts specified in the block diagrams and/or flowchart block or blocks.
Accordingly, the present application may also be embodied in hardware and/or in software (including firmware, resident software, micro-code, etc.). Furthermore, the present application may take the form of a computer program product on a computer-usable or computer-readable storage medium having computer-usable or computer-readable program code embodied in the medium for use by or in connection with an instruction execution system. In the context of this application, a computer-usable or computer-readable medium may be any medium that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A power down delay protection circuit, comprising: the system comprises a main control unit, an auxiliary control unit, a switch unit, a power supply end and a signal trigger end;
the main control unit is used for receiving a trigger signal which is output by the signal trigger end and used for representing the power-off of a protected object, and outputting a first switching signal for controlling the switching-off of the switching unit after a first preset time according to the trigger signal;
the auxiliary control unit is used for receiving the trigger signal and outputting a second switching signal for controlling the switching-off of the switching unit after a second preset time according to the trigger signal;
the switching unit for breaking a path between the power source terminal and the protected object according to the first switching signal and/or the second switching signal;
the first preset time length is less than the second preset time length.
2. The circuit of claim 1, further comprising an and circuit, wherein a first input terminal of the and circuit is connected to the output terminal of the main control unit, a second input terminal of the and circuit is connected to the output terminal of the auxiliary control unit, and an output terminal of the and circuit is connected to the switching unit, and configured to output a third switching signal for controlling the switching unit to be turned off according to the first switching signal and the second switching signal.
3. The circuit of claim 1, wherein the secondary control unit comprises a timing control unit and a timing unit, wherein:
the timing control unit is used for receiving the trigger signal and generating a control signal for controlling the timing unit to work according to the trigger signal;
and the timing unit is used for starting to work after receiving the control signal and outputting the second switching signal after the second preset time length is reached.
4. The circuit of claim 3, wherein the timing unit comprises a timer, a resistive component, and a capacitive component, wherein:
the reset end of the timer is used as the reset end of the timing unit, the rising edge trigger input end of the timer is used as the first input end of the timing unit, the falling edge trigger input end of the timer is used as the second input end of the timing unit, and the threshold end of the timer is respectively connected with one end of the resistor assembly, the discharge end of the timer and one end of the capacitor assembly;
the other end of the resistor assembly is connected with a power supply;
the other end of the capacitor assembly is grounded.
5. The circuit of claim 4, wherein the resistive component comprises one resistor or a plurality of resistors; if the resistor comprises a plurality of resistors, the plurality of resistors are connected in parallel and/or in series; and/or
The capacitance component comprises one capacitance or a plurality of capacitances; if a plurality of capacitors are included, the plurality of capacitors are connected in parallel and/or in series.
6. The circuit of claim 3, wherein the timing control unit comprises a first switching component, a second switching component, a third switching component, and a fourth switching component, wherein:
the input end of the first switch component is connected with the signal trigger end, the power supply input end of the first switch component is connected with the power supply end, and the output end of the first switch component is connected with the input end of the second switch component and used for outputting a high-level signal according to the trigger signal;
a power input end of the second switch assembly is connected with the power end, and an output end of the second switch assembly is respectively connected with an input end of the third switch assembly and a reset end of the timing unit and used for outputting a low-level signal according to the high-level signal;
the power supply input end of the third switch assembly is connected with a power supply, and the output end of the third switch assembly is respectively connected with the input end of the fourth switch assembly and the first input end of the timing unit and used for outputting a high level signal according to the low level signal;
and the power input end of the fourth switch assembly is connected with the power supply, and the output end of the fourth switch assembly is connected with the second input end of the timing unit and used for outputting a low level signal according to the high level signal.
7. The circuit of claim 6, wherein the first switch assembly comprises a first switch tube, a first resistor, a second resistor, a third resistor, and a fourth resistor, wherein the second switch assembly comprises a second switch tube, a fifth resistor, wherein the third switch assembly comprises a third switch tube, a sixth resistor, a seventh resistor, and an eighth resistor, wherein the fourth switch assembly comprises a fourth switch tube, a ninth resistor, a tenth resistor, and an eleventh resistor, wherein,
one end of the first resistor is connected with the signal trigger end, and the other end of the first resistor is respectively connected with one end of the second resistor and the base electrode of the first switching tube;
the other end of the second resistor is grounded;
a collector of the first switch tube is connected with one end of the third resistor, and an emitter of the first switch tube is grounded;
the other end of the third resistor is respectively connected with one end of the fourth resistor and the base electrode of the second switching tube;
the other end of the fourth resistor is connected with the power supply end;
an emitting electrode of the second switching tube is connected with the power supply end, and a collector electrode of the second switching tube is connected with one end of the fifth resistor;
the other end of the fifth resistor is respectively connected with one end of the sixth resistor and the reset end of the timing unit and is grounded;
the other end of the sixth resistor is respectively connected with one end of the seventh resistor and the base electrode of the third switching tube;
the other end of the seventh resistor is grounded;
a collector of the third switching tube is respectively connected with one end of the eighth resistor, one end of the ninth resistor and the first input end of the timing unit, and a base of the third switching tube is grounded;
the other end of the eighth resistor is connected with the power supply;
the other end of the ninth resistor is connected with one end of the tenth resistor and the base of the fourth switching tube respectively;
the other end of the tenth resistor is grounded;
a collector of the fourth switching tube is respectively connected with one end of the eleventh resistor and the second input end of the timing unit, and an emitter of the fourth switching tube is grounded;
the other end of the eleventh resistor is connected with the power supply.
8. The circuit of claim 7, wherein the timing control unit is specifically configured to:
receiving the trigger signal, disconnecting the first switch tube, the second switch tube and the third switch tube, connecting the fourth switch tube, outputting a low level signal to a reset end of the timing unit, outputting a high level signal to a first input end of the timing unit, and outputting a low level signal to a second input end of the timing unit;
the timing unit is specifically configured to:
and outputting a low level signal after the second preset time.
9. The circuit of claim 7, further comprising a diode, wherein an anode of the diode is grounded, and a cathode of the diode is connected to the other end of the fifth resistor, one end of the sixth resistor, and the first input terminal of the timing unit, respectively, for voltage clamping to protect the timing unit.
10. A power-down delay protection device, comprising a power-down delay protection circuit according to any one of claims 1 to 9.
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| CN202011575732.5A CN112636732B (en) | 2020-12-28 | 2020-12-28 | Power-off delay protection circuit and device |
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| CN202011575732.5A CN112636732B (en) | 2020-12-28 | 2020-12-28 | Power-off delay protection circuit and device |
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| CN114583813A (en) * | 2022-03-15 | 2022-06-03 | 重庆海尔滚筒洗衣机有限公司 | Power supply circuit |
| CN116674483B (en) * | 2023-06-30 | 2024-02-13 | 东风电驱动系统有限公司 | Automobile delay power-off control system and control method |
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| US6661123B2 (en) * | 2001-12-17 | 2003-12-09 | Mitac International Corp. | Power control circuit with power-off time delay control for microprocessor-based system |
| CN201472275U (en) * | 2009-08-31 | 2010-05-19 | 比亚迪股份有限公司 | Vehicle power-off control system |
| US8437112B2 (en) * | 2010-05-06 | 2013-05-07 | Hubei Shengjia Electric Apparatus Co., Ltd. | Circuit breaker with time-delay function |
| CN102756701B (en) * | 2012-05-22 | 2014-11-05 | 奇瑞汽车股份有限公司 | Power delay system for automobile electric control unit |
| CN103532536B (en) * | 2012-07-04 | 2016-04-20 | 福建巨力电子装备工业有限公司 | The power on-off control circuit of vehicle electronic device |
| CN110768650A (en) * | 2018-07-27 | 2020-02-07 | 台达电子工业股份有限公司 | Abnormal voltage protection device and operation method thereof |
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