CN112559429A - USB data interception system and method - Google Patents

Abstract

The invention relates to a data interception system and method based on a USB, belonging to the technical field of electronics and communication. The invention extracts the signal on the USB data differential line directly from the middle lead of the USB bus connecting the master and slave devices without interfering the data flow between the original USB master and slave devices; receiving the differential signal through a special USB2.0 PHY chip, restoring the differential signal into a level signal, further converting the level signal into parallel data and sending the parallel data into an FPGA; and a specially designed FPGA internal logic circuit analyzes and processes the data packet, and unpacked and integrated master and slave equipment transmission data are output through an 8-bit parallel bus. The invention intercepts signals without intruding through the USB PHY and processes data packets through the FPGA, and can directly output data transmitted between the USB master device and the USB slave device through the parallel IO port without other special devices (such as a PC).

Description

USB data interception system and method

Technical Field

The invention relates to a data interception system and method based on a USB (universal serial bus), belongs to the technical field of electronics and communication, and particularly provides a method for processing intercepted image data in real time by using a base plate based on a single chip microcomputer, a CPLD (complex programmable logic device) or an FPGA (field programmable gate array).

Background

As digital products are developed and popularized, data communication between devices is becoming higher in frequency and higher in speed, and the USB protocol is one of the mainstream protocols for data transmission between various devices. Devices that support the USB protocol are not only common in our daily lives, but are also very common in scientific research, for example: various external detection devices, instruments and meters, telescopes, various signal analyzers and the like are provided with interfaces conforming to the USB standard. The USB bus is one of the common external bus standards for data exchange and communication between a host and a device in the USB bus model. The USB interface is one of the mainstream trends of modern data transmission because of its advantages of high speed, stability, plug and play, unified interface specification, and convenience for use. The USB interface standards have three types: USB 1.1, USB2.0 and USB 3.0. Although the number of devices of the USB3.0 interface is large at present, the share of the USB2.0 devices in the market is higher than 3.0.

USB is a convenient, point-to-point data transfer, but the protocol does not support data transfer between three devices. If the real-time interception and acquisition functions of data on the USB2.0 bus need to be realized, a specific device or system needs to be developed to complete the task. The USB protocol analyzer sold in the market at present can realize the data monitoring and analyzing function based on a computer. In a few documents, the sensed data is finally uploaded to the PC. The monitoring and the acquisition of the real-time transceiving data of the USB interface are realized on the computer through software, so that the portability and the universality are not good, and different computers need to be configured and debugged for many times; and the auxiliary of upper computer software is separated, and the normal work can not be realized. At present, no system exists for monitoring and collecting data in two directions on a USB2.0 bus in real time, processing and combining the data into a USB transaction which is sent to a bottom board circuit for the bottom board circuit to use.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: the invention provides a USB data interception system and a method thereof, wherein the system uses a USB interface chip to intercept bidirectional data of a bus, and uses FPGA to combine the data into a USB transaction to be sent to a bottom board circuit.

The technical scheme of the invention is as follows: a data interception system based on USB comprises an FPGA module 1, a USB interface chip module 2, an IO expansion port module 3, a USB interface A11 and a USB interface B12;

the USB interface chip module 2 is connected with the master device 9 and the slave device 10 through a USB interface A11 and a USB bus of a USB interface B12 in a non-intrusive mode; the USB interface chip module 2 is also connected with the FPGA module 1, and the FPGA module 1 comprises an ULPI interface module 4, a packet decomposition module 5, an affair combination module 6, a transmission module 7 and a clock module 8; the clock module 8 is respectively connected with the USB interface chip module 2, the ULPI interface module 4, the packet decomposition module 5, the transaction combination module 6 and the transmission module 7; the IO expansion port module 3 is connected with a transmission module 7 of the FPGA module 1; the IO expansion port module 3 is in butt joint with a bottom plate circuit.

As a further scheme of the present invention, the ULPI interface module 4 is an ULPI PHY interface module, establishes a protocol layer connection with the USB interface chip module 2, and completely outputs data to the packet decomposition module 5; the packet decomposition module 5 is used for caching the USB data packet into the RAM and storing the packet information into the FIFO for caching; the transaction combination module 6 is used for USB transaction processing, combines a plurality of associated token packets, data packets and handshake packets into a USB transaction and provides an EN signal; the clock module 8 is input by the USB interface chip module 2 and controls clocks of the ULPI interface module 4, the packet decomposition module 5, the transaction combination module 6 and the transmission module 7; the transmission module 7 is configured to output the combined USB transaction, the synchronous clock provided to the backplane circuit, and the EN signal to the backplane circuit through the IO expansion port module 3, and when the EN signal is high, one byte in the USB transaction is output every synchronous clock cycle.

A USB-based data interception method, the method comprising:

the USB interface chip module 2 intercepts signals between the master device 9 and the slave device 10 in a non-invasive manner through a USB interface A11 and a USB bus of a USB interface B12 and sends the signals to the FPGA module 1 for processing, and the FPGA module 1 combines the processed data into a USB transaction and outputs the USB transaction from the IO expansion port module 3 to the bottom board circuit; the backplane circuit screens the required data for use based on the header file of the transaction.

As a further scheme of the present invention, when each USB transaction is output, the first 4 bytes are a transaction header, and the format of the transaction header of 4 bytes is:

byte 1: tid [7:0], which represents the type of the transaction;

byte 2: addr [6:0] representing the device address corresponding to the transaction;

byte 3: the lower 4 bits are ep [3:0] which represents the endpoint number corresponding to the transaction, and the upper 4 bits are len [3:0 ];

byte 4: len [11:4], len [11:0] represents the data length corresponding to the transaction;

followed by 0-1024 bytes of transaction data.

The working principle of the invention is as follows:

the USB-based data interception system and method use a bottom plate 5V for power supply. Because the voltage used by each module is different, the 2-path AMS1117 low-voltage-drop linear power supply chip is used for generating 3.3V and 1.2V respectively for the whole use.

The USB interface a11 is used to connect a master device 9 for USB communication, and the USB interface B12 is used to connect a slave device 10 for USB communication. DM and DP of two USB interfaces are directly connected with a USB interface chip module 2, and a protection resistor of 1k omega is added to be connected with the FPGA; VBUS adds 100k omega resistance and links to each other with FPGA module 1 to add 100k omega pull-down resistance.

The chip used by the USB interface chip module 2 is a USB3300 with an interface being an ULPI interface packaged based on UTMI + level 3; ULPI connects a complete OTG host/device PHY to a system on a chip using 12 pins. An 8-bit bidirectional data bus, clocked at 60MHz, allows FPGA module 1 to access this internal register array and transfer USB packets to the physical layer. The remaining 3 pins are used for control data flow and arbitration of the data bus. The direction of the 8-bit data bus is controlled by the DIR output of ULPI interface module 4. The other output NXT is used to control the flow of data into and out of the device. Finally, the STP input to ULPI interface module 4 terminates the transfer and is used to initiate and resume from the suspended state.

The USB3300 uses an internal crystal driver and phase-locked loop subsystem to provide a noise-free, stable 480MHz reference clock that the PHY uses during transmission and reception. USB3300 requires a stable, noiseless 24MHz crystal or clock as a frequency reference. USB3300 may use a crystal or external clock oscillator as the 24MHz reference. The crystal is connected to the USB3300 pin. Once the 480MHz phase locked loop locks to the correct frequency, it will drive the CLKOUT pin with the 60MHz clock. The signal level of the chip ULPI interface is 3.3V. Operating in a high speed 480Mbps speed mode.

DIR (direct) for controlling the transmission Direction of the data bus; when the USB interface chip transmits data to the FPGA, the DIR is driven to be high; when no data is transmitted, driving to be low and monitoring a control signal at the FPGA end; meanwhile, the USB interface chip will drive DIR high when it is unable to receive data. NXT, the USB interface chip controls the signal when transmitting data; when the FPGA sends data to the USB interface chip, the USB interface chip immediately pulls up NXT when receiving the data; then the FPGA puts the next byte on the data bus in the next clock cycle; correspondingly, when the USB interface chip is sending data to the FPGA, NXT represents that there is new byte data to send to the FPGA at this time. STP is Stop, when FPGA sets STP to be effective, the current data flow on the bus is stopped in a clock period; if the FPGA is transferring data to the USB interface chip, the STP will hold the data for the last bit of each packet.

The ULPI interface supports two basic modes of operation: a synchronous mode and a low power mode. Synchronous mode, all signals are varying with respect to the 60MHz clock. In low power mode, the clock is off in the suspend state and the next two bits of the data bus contain the line state [1:0] signals. ULPI adds a low power mode, which is an interrupt output, allowing the link to receive asynchronous interrupts when the OTG comparator or ID pin changes state. In the synchronous mode, data is transmitted on the rising edge of CLKOUT. The direction of the data bus is determined by the state of the DIR. When DIR is high, the PHY is driving data [7:0 ]. When DIR is low, the link is driving data [7:0 ]. Because USB uses bit-stuffing coding, some method is needed to allow the PHY to limit the USB to transmit data. ULPI signal NXT is used to request the link layer to place the next byte on the data bus. When the link addresses the PHY, a single ULPI protocol block decodes the ULPI 8-bit bidirectional bus. The link must use the DIR output to determine the direction of the ULPI data bus. USB3300 is the "bus arbiter". The ULPI protocol block routes data/commands to the sender or ULPI register array.

The USB interface chip module 2 restores the data differential signal into a level signal and needs to decode the NRZI code stream, and then identifies the filling bit. And converting the data into data with the bit width of 8 bits, and sending the data to the FPGA module 1 through D0-D7 of the USB interface chip module 2.

The core chip used by the FPGA module 1 is an XC6SLX9-2TQG144C chip of the Xilinx company Spartan6 series, and is connected to the FPGA chip by matching with an FPGA peripheral circuit. The configuration chip SPI-Flash like FPGA is used for storing FPGA configuration bit stream; the power supply circuit mainly provides +5V, +3.3V and +1.2V voltages required by the FPGA chip and the SPI-Flash; the clock uses the 60MHz clock output by the USB interface chip module 2 as the system clock of the module. And two indicator lamps are configured, and the LED _1 power supply lights a red indicator lamp to remind the power supply after the power supply is switched on. LED _2 transaction indicator lights, blue indicator lights once every time a valid USB transaction is output. One end of the FPGA module 1 is connected with the IO expansion port module 3, and the other end is connected with the USB interface chip module 2. The device is connected to a bottom plate, and after the bottom plate is electrified, the bottom plate provides 5V voltage and a reset signal. ULPI interface module 4 in FPGA module 1 writes initial control command TX CMD to the register of USB interface chip module 2. The USB interface a11 is connected to a master device 9 that performs USB communication, and the USB interface B12 is used to connect a slave device 10 that performs USB communication. The USB interface chip module 2 starts to listen to the differential circuit on the bus, and restores the differential signal to a level signal and transmits the level signal to the FPGA module 1. The ULPI interface module 4 is an ULPI PHY interface module, establishes a protocol layer connection with the USB interface chip module 2, and completely outputs data to the packet decomposition module 5. The packet decomposition module 5 buffers the USB data packet into the RAM and stores the packet information into the FIFO for buffering. The transaction combination module 6 is used for USB transaction processing, combines a plurality of associated token packets, data packets and handshake packets into a USB transaction and provides an EN signal; the clock module 8 is input by the USB interface chip module 2, uses a basic clock management module (DCM) and a global clock distribution network in the FPGA to be tightly combined, can be used for frequency division and frequency multiplication, eliminates clock delay difference, controls clocks of the ULPI interface module 4, the packet decomposition module 5, the transaction combination module 6 and the transmission module 7, outputs clock signals, and can adjust the phase of the output clock signals to enable the time sequence of the signals output to the bottom plate to be optimal. The transmission module 7 is configured to output the combined USB transaction, the synchronous clock provided to the backplane, and the EN signal to the backplane through the IO expansion port module 3, and when the EN signal is high, there is a byte of USB transaction output in each synchronous clock cycle.

The working process of the invention is as follows:

the device is connected to a bottom plate, and after the bottom plate is electrified, the bottom plate provides 5V voltage and a reset signal. The 2-path LDO low-dropout linear power supply chip is used for generating 3.3V and 1.2V voltages respectively for the device to use. After resetting, ULPI interface module 4 in FPGA module 1 writes initial control command TX CMD to the register of USB interface chip module 2. To write to the register, ULPI interface module 4 in FPGA module 1 needs to wait until DIR low, driving TXD CMD on the data bus in the first clock cycle. In the third clock cycle, the USB interface chip module 2 will drive NXT high. At the next rising clock edge, ULPI interface module 4 will write the register data. On the fifth clock cycle, USB interface chip module 2 will accept the register data and ULPI interface module 4 will drive idle on the bus and drive STP high to signal the end of the send packet. Finally, on the sixth clock cycle, the USB interface chip module 2 will latch the data into the register and drive NXT low. ULPI interface module 4 will pull down STP. NXT is used to control when ULPI interface module 4 drives register data on the bus. DIR is low throughout the transaction because USB interface chip module 2 receives data from ULPI interface module 4. STP is used to end the transaction and data is registered after STP low. After the write operation is completed, ULPI interface module 4 must drive ULPI idle 00h on the data bus, otherwise USB interface chip module 2 may decode the bus value into an ULPI command.

The master device 9 performing USB communication is connected to the USB interface a11, and the slave device 10 performing USB communication is connected to the USB interface B12. The USB interface chip module 2 starts to monitor the differential circuit on the bus and restores the differential signal into a level signal and transmits the level signal into the FPGA. During transmission, the USB interface chip module 2 will use NXT to control the data flow rate into the USB interface chip module 2. If USB interface chip module 2 pipe is full or bit-filling causes the data pipe to overfill, NXT is invalid (low) and ULPI interface module 4 will retain the value on the data until NXT is valid (high). USB transfer ends when STP is active and NXT is inactive in ULPI interface module 4. Since USB interface chip module 2 expects another byte to be fetched from ULPI interface module 4 in this state, ULPI interface module 4 cannot have an NXT invalid STP valid signal,

once the USB interface chip module 2 completes the transmission, the DP/DM line returns to idle state and the RXD CMD returns to the link, so that the internal packet timing can be updated by the line state.

At full speed or low speed, once STP is active, each FS/LS bit transition will generate one RXD CMD because the bit time is relatively slow.

USB interface chip module 2 validates the DIR to enable USB interface chip module 2 to control the data bus from ULPI interface module 4. In the same cycle, DIR and NXT contain additional information that Rxactive is valid. When NXT is not active and DIR is active, RXD CMD data is transmitted to FPGA module 1. After the last byte of the USB receive data packet is transmitted to the USB interface chip module 2, the line state returns to the idle state.

The ULPI full speed receiver operates according to the UTMI/ULPI specification. At full speed, the NXT signal will only be valid if the data bus has valid received data bytes. When NXT is low and DIR is high, the RXD command is driven on the data bus.

At full speed, the USB interface chip module 2 does not signal Rxactive invalid in RXD CMD before the DP/DM line state transitions to the idle state. This prevents the FPGA module 1 from violating the minimum change time of two full-speed bit times.

When ULPI interface module 4 transmits the packet start signal to packet decomposition module 5, 8-bit parallel data is stored in 8-bit wide RAM, and the length of the packet can be obtained by counting once every time one byte is stored. The first three groups of 8-bit data are stored in three registers with the width of 8, and after the transmission of a complete packet is finished, the information of each packet is combined into a data to be stored in an FIFO for buffering. If the packet length is three and the first set of data is the PID (packet identification field) of the token packet, and the packet is judged to be a token packet, the first three sets of 8-bit data stored in the register are stored in the first 24-bit buffer in the 64-bit FIFO. The first 1-8 bits are the PID of the packet, 9-15 bits are the address of the device, 16-19 bits are the endpoint data of the device, and the remaining 5 bits are the CRC check bits. If the length of the packet is greater than 3 and the first set of data is the PID of the packet, then the packet is determined to be a packet. Storing a first set of data (PID) to 1-8 bits of a 64-bit FIFO; the length of the packet is reduced by three (the PID of one byte and the CRC check bit of two bytes are removed, and the length of the packet data is the length) and the packet is stored into 25-36 bits in a 64-bit FIFO; the first address of the packet in RAM plus one (the first byte is PID, the second byte is the data of the packet and the last two bytes are CRC of the packet) is stored in 37-48 bits in a 64-bit FIFO. If the packet length is one and the first set of data is the PID of the handshake packet, the packet is determined to be a handshake packet and the first set of data (PID) is stored in the first bit of the 64-bit FIFO. These data are buffered in the FIFO for subsequent processing by the transaction combination module 6.

In the transaction combination module 6, after the data of the previous transaction is processed and transmitted to the backplane, if there is data in the FIFO, the first 8 bits of the 64-bit data in the FIFO are determined, and the first 8 bits are PID (packet identification code). If the packet is a PID of the token packet, PID data is put into a PID register of the token packet, the address in the 64-bit data is put into an address register, and the endpoint data is put into an endpoint register. If the data packet is PID, the PID data is put into the PID register of the data packet, the data length of the 64-bit data is put into the data length register, and the address of the data in the RAM is put into the address register of the data RAM. If the packet is the PID of the handshake packet, the PID data is put into a handshake packet PID register. From the three PID registers it is possible to determine what transaction is being transmitted this time and to name this time as a corresponding 8-bit Transaction Identifier (TID) code and to combine the address, endpoint, length of this transaction into a transaction header. The transmission module 7 is configured to combine the combined USB transaction, the synchronous clock provided to the backplane, and the EN signal and output the combination to the backplane through the IO expansion port module 3, and when the EN signal is high, one byte in the USB transaction is output in each synchronous clock cycle, the first 4 bytes are a transaction header, and the format of the transaction header of the 4 bytes is:

byte 1: tid [7:0], which represents the type of the transaction;

byte 2: addr [6:0] representing the device address corresponding to the transaction;

byte 3: the lower 4 bits are ep [3:0] which represents the endpoint number corresponding to the transaction, and the upper 4 bits are len [3:0 ];

byte 4: len [11:4], len [11:0] represents the data length corresponding to the transaction;

followed by transaction data of corresponding length read out through the data RAM address register. And registers such as address, endpoint, PID, etc. are cleared.

After the data is output to the bottom plate, the bottom plate can screen required information according to the head information, and the design is specially used for screening image information.

The invention has the beneficial effects that:

1. when image data is transmitted from master and slave devices of the USB communication, if the data needs to be analyzed, processed or temporarily stored in real time by a base plate based on a single chip microcomputer, a CPLD or an FPGA, the system can be connected with the base plate system for use. And a circuit of a bottom plate is transmitted from the PC end, so that the speed is improved, and the labor waste is reduced.

2. The invention can carry out non-invasive USB data real-time interception on the data on the USB bus and transmit the data to the bottom plate for use after the USB transmission line is accessed without a PC.

3. The invention has the advantages of simple and easy use of equipment, lower cost, smaller area, portability and strong practicability.

4. The invention can also listen to other data, only requiring slight modifications in the code.

5. The invention integrates several packets into one transaction, discards useless data, classifies all transactions, and the backplane circuit can clearly obtain the type of the transaction, the device address corresponding to the transaction, the endpoint number corresponding to the transaction and the data length corresponding to the transaction. The backplane circuit can obtain the data required by the backplane circuit according to the conditions, and the result required by the backplane circuit can be conveniently obtained.

Drawings

FIG. 1 is a functional block diagram of the present invention;

FIG. 2 is a circuit diagram of the bi-directional communication of the USB interface chip of the present invention to DATA DATA in the FPGA chip;

FIG. 3 is a flow diagram of the packet disassembly module and transaction combination module data transfer of the present invention;

fig. 4 is a backplane reception state machine of the present invention transmitting to a backplane.

The respective reference numerals in fig. 1: the system comprises a 1-FPGA module, a 2-USB interface chip module, a 3-IO expansion port module, a 4-ULPI interface module, a 5-packet decomposition module, a 6-transaction combination module, a 7-transmission module, an 8-clock module, a 9-master device, a 10-slave device, an 11-USB interface A and a 12-USB interface B.

Detailed Description

The invention is further described with reference to the following figures and specific examples.

Example 1: as shown in fig. 1-4, a USB-based data interception system includes an FPGA module 1, a USB interface chip module 2, an IO expansion port module 3, a USB interface a11, and a USB interface B12;

the USB interface chip module 2 is connected with the master device 9 and the slave device 10 through a USB interface A11 and a USB bus of a USB interface B12 in a non-intrusive mode; the USB interface chip module 2 is also connected with the FPGA module 1, and the FPGA module 1 comprises an ULPI interface module 4, a packet decomposition module 5, an affair combination module 6, a transmission module 7 and a clock module 8; the clock module 8 is respectively connected with the USB interface chip module 2, the ULPI interface module 4, the packet decomposition module 5, the transaction combination module 6 and the transmission module 7; the IO expansion port module 3 is connected with a transmission module 7 of the FPGA module 1; the IO expansion port module 3 is in butt joint with a bottom plate circuit.

As a further scheme of the present invention, the ULPI interface module 4 is an ULPI PHY interface module, establishes a protocol layer connection with the USB interface chip module 2, and completely outputs data to the packet decomposition module 5; the packet decomposition module 5 is used for caching the USB data packet into the RAM and storing the packet information into the FIFO for caching; the transaction combination module 6 is used for USB transaction processing, combines a plurality of associated token packets, data packets and handshake packets into a USB transaction and provides an EN signal; the clock module 8 is input by the USB interface chip module 2 and controls clocks of the ULPI interface module 4, the packet decomposition module 5, the transaction combination module 6 and the transmission module 7; the transmission module 7 is configured to output the combined USB transaction, the synchronous clock provided to the backplane circuit, and the EN signal to the backplane circuit through the IO expansion port module 3, and when the EN signal is high, one byte in the USB transaction is output every synchronous clock cycle.

A USB-based data interception method, the method comprising:

the USB interface chip module 2 intercepts signals between the master device 9 and the slave device 10 in a non-invasive manner through a USB interface A11 and a USB bus of a USB interface B12 and sends the signals to the FPGA module 1 for processing, and the FPGA module 1 combines the processed data into a USB transaction and outputs the USB transaction from the IO expansion port module 3 to the bottom board circuit; the backplane circuit screens the required data for use based on the header file of the transaction.

As a further scheme of the present invention, when each USB transaction is output, the first 4 bytes are a transaction header, and the format of the transaction header of 4 bytes is:

byte 1: tid [7:0], which represents the type of the transaction;

byte 2: addr [6:0] representing the device address corresponding to the transaction;

byte 3: the lower 4 bits are ep [3:0] which represents the endpoint number corresponding to the transaction, and the upper 4 bits are len [3:0 ];

byte 4: len [11:4], len [11:0] represents the data length corresponding to the transaction;

followed by 0-1024 bytes of transaction data.

Specifically, the FPGA module 1 is connected to the USB interface chip module 2 and the IO expansion port module 3 through different I/O ports. The data transmission between the FPGA module 1 and the USB interface chip module 2 and the IO expansion port module 3 is realized by data lines D0-D7 with 8-bit width. DIR (direct) for controlling the transmission Direction of the data bus; when the USB interface chip module 2 transmits data to the FPGA module 1, the DIR is driven to be high; when no data is transmitted, driving to be low and monitoring a control signal at the 1 end of the FPGA module; meanwhile, the USB interface chip module 2 drives DIR high when it cannot receive data. NXT, Next, the USB interface chip module 2 will control the signal when transmitting data; when the FPGA module 1 sends data to the USB interface chip module 2, the USB interface chip module 2 immediately raises NXT when receiving the data; subsequently, the FPGA module 1 puts the next byte on the data bus in the next clock cycle; correspondingly, when the USB interface chip module 2 is sending data to the FPGA module 1, NXT represents that there is new byte data to send to the FPGA module 1 at this time. STP is Stop, when the FPGA module 1 sets STP to be effective, the current data flow on the bus is stopped in a clock period; if the FPGA module 1 is transferring data to the USB interface chip module 2, the STP will hold the data for the last bit of each packet.

As shown in fig. 1, the USB interface a11 is a USB port for connecting the master device 9, and the USB interface B12 is another USB port for connecting the slave device 10, and two lines are pulled out from the differential pair by the middle lead of the USB bus of the two interfaces, so that the signals can directly flow out, and the original connection can be restored, thereby achieving the purpose of not interfering with the original transmission line on the hardware level.

As shown in fig. 1, the USB interface chip module 2 intercepts signals between the master device 9 and the slave device 10 through USB buses of the USB interface a11 and the USB interface B12 without intruding, and sends the signals to the FPGA module 1 for processing, and the FPGA module 1 combines the processed data into a USB transaction, and sends the USB transaction from the IO expansion port module 3 to the backplane circuit. The backplane circuit may filter the data needed for use based on the header file of the transaction.

The circuit schematic shown in fig. 2 solves the main difficulty, and realizes bidirectional conduction of DATA from the USB interface chip module 2 to the FPGA module 1. Where the MUX is a data selector and the buff is a tri-state output buffer. When DIR is high-order, the tri-state output buffer is in high impedance state; the DATA selector turns on DATA and DATA _ IN. When the USB interface chip module 2 transmits data to the FPGA module 1, the DIR is driven to be high, and the FPGA module 1 starts to receive the data transmitted by the USB interface chip module 2. The tri-state output buffer transfers the DATA _ OUT DATA to DATA when DIR is low. When there is no data transfer, the USB interface chip module 2 drives DIR low and monitors the control signal of the FPGA module 1, so that the FPGA module 1 can write a command into the register of the USB interface chip module 2.

As shown in fig. 1, the FPGA module 1 includes: the system comprises an ULPI interface module 4, a packet decomposition module 5, a transaction combination module 6, a transmission module 7 and a clock module 8; the ULPI interface module 4 is an ULPI PHY interface module, establishes the relation of a protocol layer with the USB interface chip module 2, and completely outputs data to the packet decomposition module 5; the packet decomposition module 5 caches the USB data packet in the RAM and stores the packet information into the FIFO for caching; the transaction combination module 6 is used for USB transaction processing, combines a plurality of associated token packets, data packets and handshake packets into a USB transaction and provides an EN signal; the clock module 8 is input by the USB interface chip module 2 and controls clocks of the ULPI interface module 4, the packet decomposition module 5, the transaction combination module 6 and the transmission module 7; the transmission module 7 is configured to combine the combined USB transaction, the synchronous clock provided to the backplane, and the EN signal and output the combined USB transaction, the synchronous clock provided to the backplane, and the EN signal to the backplane through the IO expansion port module 3.

As shown in fig. 3, when ULPI interface module 4 transmits a packet start signal to packet decomposition module 5, 8-bit parallel data is stored in 8-bit wide RAM, and after a complete packet transmission is finished, data with bit width of 64, which is composed of PID, endpoint, device address information, packet length, and location in RAM, is stored in 64-bit wide FIFO for buffering. When no data is transferred to the backplane, the data in the FIFO is processed. When one transaction transmission is complete, the PID of several packets is integrated into TID of one transaction, CRC is discarded, and then the information of several packets is integrated into a transaction packet information head.

As shown in fig. 1, the USB interface chip module 2 needs to write a USB protocol into the USB3300 chip so that it can restore the differential signal to a level signal and translate the level signal into a signal conforming to the ULPI protocol, and then convert the data into data with a bit width of 8 bits by the ULPI protocol and transmit the data into the FPGA for processing. And passes the CLK signal into the FPGA.

As shown in fig. 1, the IO expansion port module 3 is connected to the transmission module 7 of the FPGA module 1; the IO expansion port module 3 outputs a clock signal to the bottom plate to synchronize the bottom plate clock; the transaction valid signal EN and the USB transaction are output to the backplane.

As shown in fig. 4, a backplane reception state machine of the present invention is transmitted to a backplane. When each USB transaction is output and EN is effective, the transaction packet is output in sequence, the first 4 bytes are transaction information heads, and the format of the 4-byte transaction information head is as follows:

byte 1: tid [7:0], which represents the type of the transaction;

byte 2: addr [6:0] representing the device address corresponding to the transaction;

byte 3: the lower 4 bits are ep [3:0] which represents the endpoint number corresponding to the transaction, and the upper 4 bits are len [3:0 ];

byte 4: len [11:4], len [11:0] represents the data length corresponding to the transaction;

followed by 0-1024 bytes of transaction data.

The backplane enters an initial state (IDLE) after being powered on, and receives a HEADER of the first eight bits of data and enters a HEADER _1 state when the enable signal EN is 1 and the previous clock EN is 0, that is, when a USB transaction is transmitted from the system to the backplane. HEADER _1 state EN is 1 receiving the second eight bits of data and enters HEADER _2 state. HEADER _2 state EN is 1 receiving the HEADER of the third eight bits of data and enters the HEADER _3 state. HEADER _3 state EN is 1 receiving the HEADER of the fourth eight bits of DATA and enters the DATA state. The DATA state continues as long as EN is 1 until EN is 0, returning to the initial state machine (IDLE). The backplane can filter the desired data based on the state machine plus header constraints.

While the present invention has been described in detail with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, and various changes and modifications can be made within the knowledge of those skilled in the art without departing from the spirit of the present invention.

Claims (4)

1. A data interception system based on USB is characterized in that: the system comprises an FPGA module (1), a USB interface chip module (2), an IO expansion port module (3), a USB interface A (11) and a USB interface B (12);

the USB interface chip module (2) is connected with the master device (9) and the slave device (10) in a non-invasive manner through USB buses of a USB interface A (11) and a USB interface B (12); the USB interface chip module (2) is also connected with the FPGA module (1), and the FPGA module (1) comprises an ULPI interface module (4), a packet decomposition module (5), a transaction combination module (6), a transmission module (7) and a clock module (8); the clock module (8) is respectively connected with the USB interface chip module (2), the ULPI interface module (4), the packet decomposition module (5), the transaction combination module (6) and the transmission module (7); the IO expansion port module (3) is connected with a transmission module (7) of the FPGA module (1); the IO expansion port module (3) is in butt joint with the bottom board circuit.

2. The USB data-based interception system according to claim 1, wherein: the ULPI interface module (4) is an ULPI PHY interface module, establishes the relation of a protocol layer with the USB interface chip module (2), and completely outputs data to the packet decomposition module (5); the packet decomposition module (5) is used for caching the USB data packet into the RAM and storing the packet information into the FIFO for caching; the transaction combination module (6) is used for USB transaction processing, combines a plurality of associated token packets, data packets and handshake packets into a USB transaction and provides an EN signal; the clock module (8) is input by the USB interface chip module (2) and controls clocks of the ULPI interface module (4), the packet decomposition module (5), the transaction combination module (6) and the transmission module (7); the transmission module (7) is used for combining the combined USB transaction, the synchronous clock provided for the bottom board circuit and the EN signal and outputting the combination to the bottom board circuit through the IO expansion port module (3), and when the EN signal is high, one byte in the USB transaction can be output in each synchronous clock period.

3. A data interception method based on USB is characterized in that the method comprises the following steps:

the USB interface chip module (2) intercepts signals between the master device (9) and the slave device (10) through USB buses of a USB interface A (11) and a USB interface B (12) in a non-invasive manner and sends the signals to the FPGA module (1) for processing, and the FPGA module (1) combines the processed data into a USB transaction and outputs the USB transaction from the IO expansion port module (3) to the bottom board circuit; the backplane circuit screens the required data for use based on the header file of the transaction.

4. The USB-based data interception method according to claim 3, wherein:

when each USB transaction is output, the first 4 bytes are transaction information heads, and the format of the transaction information head of the 4 bytes is as follows:

byte 1: tid [7:0], which represents the type of the transaction;

byte 2: addr [6:0] representing the device address corresponding to the transaction;

byte 3: the lower 4 bits are ep [3:0] which represents the endpoint number corresponding to the transaction, and the upper 4 bits are len [3:0 ];

byte 4: len [11:4], len [11:0] represents the data length corresponding to the transaction;

followed by 0-1024 bytes of transaction data.

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