CN112559041A - Compatible processing method for ground direct instruction and satellite autonomous instruction - Google Patents
Compatible processing method for ground direct instruction and satellite autonomous instruction Download PDFInfo
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- CN112559041A CN112559041A CN202011417409.5A CN202011417409A CN112559041A CN 112559041 A CN112559041 A CN 112559041A CN 202011417409 A CN202011417409 A CN 202011417409A CN 112559041 A CN112559041 A CN 112559041A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/20—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
- G06F11/202—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant
- G06F11/2035—Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements where processing functionality is redundant without idle spare hardware
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- H04B7/14—Relay systems
- H04B7/15—Active relay systems
- H04B7/185—Space-based or airborne stations; Stations for satellite systems
- H04B7/1851—Systems using a satellite or space-based relay
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Abstract
The invention discloses a compatible processing method of a ground direct instruction and an on-satellite autonomous instruction, which comprises the following steps: (1) the satellite-borne remote control unit comprises a master remote control module and a backup remote control module, wherein the master remote control module and the backup remote control module work in a hot backup mode and receive direct instruction codes sent by the ground and on-satellite self-master instruction codes sent by the satellite-borne computer. A direct instruction interval is set between the two direct instruction codes sent by the ground, an autonomous instruction interval is set between the two autonomous instruction codes sent by the spaceborne computer, and the direct instruction interval and the autonomous instruction interval are set to be not less than the pulse width of an output instruction; (2) the channel control of the autonomous instruction, the priority selection of the ground direct instruction, the decoding of the autonomous instruction and the direct instruction are realized in an FPGA (field programmable gate array) (or ASIC), the output of the ground direct instruction and the satellite autonomous instruction is controlled through an instruction queue controller, and the compatibility and the ordered output of the ground direct instruction and the satellite autonomous instruction are realized.
Description
Technical Field
The invention belongs to the technical field of satellite remote control, and particularly relates to a compatible processing method of a ground direct instruction and an on-satellite autonomous instruction.
Background
The satellite-borne remote control unit (or satellite-borne remote control equipment) receives a ground direct instruction (or a ground remote control instruction) and an on-satellite autonomous instruction (or a satellite program control instruction) from two channels respectively, and outputs the instructions to control the spacecraft to act after analysis and decoding.
In addition, because two sets of instruction driving circuits are adopted, the ground direct instruction and the satellite autonomous instruction have the condition of sending simultaneously, the requirement on the output power of an instruction power supply is doubled, and the actual use is poor;
in addition, the problem of conflict between a ground direct instruction and an on-board autonomous instruction is solved by adding the CPU coprocessor, using an 'permit' mark and a 'forbid' mark between the core CPU circuit and the CPU coprocessor and a 'busy and idle' mark between the CPU coprocessor and the on-board remote control equipment as handshake signals, but the mode increases an instruction transmission link of the on-board computer and the on-board remote control equipment, increases the complexity of a hardware circuit and further reduces the reliability of the hardware circuit.
Therefore, a new method is needed to effectively solve the conflict between the ground direct command and the on-board autonomous command.
Disclosure of Invention
The invention provides a compatible processing method of a ground direct instruction and an on-satellite autonomous instruction, which aims to overcome the defects in the prior art, reduces the hardware circuit overhead, reduces the equipment volume and realizes the compatibility and ordered output of the ground direct instruction and the on-satellite autonomous instruction.
The invention is realized by adopting the following technical scheme: a compatible processing method of a ground direct instruction and an on-board autonomous instruction is used for a satellite-borne remote control unit and comprises the following steps:
step 1, the satellite-borne remote control unit comprises a master remote control module and a backup remote control module, wherein the master remote control module and the backup remote control module work in a hot backup mode and receive direct instruction codes sent by the ground and on-satellite autonomous instruction codes sent by a satellite-borne computer;
a direct instruction interval is set between two adjacent direct instructions sent to the ground, an autonomous instruction interval is set between two adjacent autonomous instructions sent to the satellite-borne computer, the direct instruction interval and the autonomous instruction interval are not smaller than the pulse width of an output instruction, and the pulse width of the output instruction refers to the pulse width of an output instruction of the satellite-borne remote control unit;
and 2, respectively outputting corresponding main command and backup command through the analysis processing of the main remote control module and the backup remote control module, and driving command load actions, wherein the command load actions comprise priority selection of ground direct commands, direct command decoding and output control, channel control of satellite autonomous commands and autonomous command decoding and output control:
priority selection of ground direct command: according to the universal rule of the spacecraft, different priority orders are set for the master remote control module and the backup remote control module, and one path of direct instruction with the highest priority is selected for subsequent direct instruction decoding and output control;
channel control of on-board autonomous commands: setting an autonomous instruction channel control switch, and sending an 'autonomous instruction forbidding' instruction when an autonomous instruction on the satellite fails to influence the normal work of the satellite; when the fault is eliminated, sending an 'enabling autonomous instruction' instruction to enable the autonomous instruction to be transmitted to an instruction queue controller;
the command queue controller adopts a first-come first-output principle for the ground direct command and the satellite autonomous command, and if the ground direct command and the satellite autonomous command arrive at the same time, the ground direct command is output preferentially.
Further, in step 1, the backup remote control module and the master remote control module have the same structural composition:
the master remote control module comprises two level conversion modules, a master FPGA/ASIC module, a latch and an instruction driving circuit module, wherein the two level conversion modules respectively and correspondingly receive an on-satellite autonomous instruction and a ground direct instruction sent by an on-board computer and the ground, and the master instruction is output through the latch and the instruction driving circuit module after being processed by the master FPGA/ASIC module;
the backup remote control module comprises two level conversion modules, a backup FPGA/ASIC module, a latch and an instruction driving circuit module, wherein the two level conversion modules respectively and correspondingly receive an on-board autonomous instruction and a ground direct instruction sent by the on-board computer and the ground, and the backup instruction is output through the latch and the instruction driving circuit module after being processed by the backup FPGA/ASIC module.
Further, in the step 2:
a corresponding instruction code buffer is respectively designed for a ground direct instruction and an on-satellite autonomous instruction in the master FPGA/ASIC module and the backup FPGA/ASIC module, so that a ground direct instruction and an on-satellite autonomous instruction are allowed to be buffered;
the instruction output control logic is multiplexed, an output channel occupation identifier is arranged on the master FPGA/ASIC module and the backup FPGA/ASIC module, the channel occupation identifier is effective in the instruction output process, and the channel occupation identifier is released to be in an idle state after the instruction output is finished; and when a new instruction comes, judging whether the channel occupation mark is idle, executing the channel occupation mark when the channel occupation mark is idle, and waiting for releasing the channel occupation mark when the channel occupation mark is occupied.
Compared with the prior art, the invention has the advantages and positive effects that:
according to the scheme, a direct instruction interval is set between two pieces of ground direct instruction codes, an autonomous instruction interval is set between the two pieces of satellite autonomous instruction codes, and the direct instruction interval and the autonomous instruction interval are not smaller than the pulse width of an output instruction; the output of the ground direct instruction and the on-satellite autonomous instruction is controlled by the instruction queue controller, so that the ground direct instruction and the on-satellite autonomous instruction can be output in order without losing the instructions, the hardware circuit overhead and the equipment volume are reduced, and the integration level and the reliability are improved;
the command queue controller firstly serves the ground direct command code and the on-satellite autonomous command code, utilizes an FPGA (or ASIC) in the remote control unit to realize the compatibility and ordered output of the ground direct command and the on-satellite autonomous command through software, avoids unexpected results such as command loss and the like, and the on-satellite computer only needs to send the autonomous command to the on-satellite remote control unit in a single direction and does not need to receive a sending command control signal sent by the remote control unit for logic control, thereby reducing the complexity of the on-satellite computer and further realizing the compatibility and ordered output of the ground direct command and the on-satellite autonomous command.
Drawings
Fig. 1 is a block diagram of a system of a master remote control module and a backup remote control module according to an embodiment of the present invention;
FIG. 2 is a block diagram of an embodiment of an instruction queue controller;
FIG. 3 is a diagram of an output instruction queue under instruction conditions of the present invention;
FIG. 4 is a diagram of an output instruction queue under the instruction condition of the embodiment of the present invention;
FIG. 5 is a diagram of an output instruction queue according to an embodiment of the present invention.
Detailed Description
In order to make the above objects, features and advantages of the present invention more clearly understood, the present invention will be further described with reference to the accompanying drawings and examples. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced in other ways than those described herein, and thus, the present invention is not limited to the specific embodiments disclosed below.
The embodiment provides a compatible processing method of a ground direct instruction and an on-board autonomous instruction, which is suitable for a satellite-borne remote control unit, wherein the satellite-borne remote control unit comprises a master remote control module and a backup remote control module, and the compatible processing method specifically comprises the following steps:
step 1, a master remote control module and a backup remote control module work in a hot backup mode, and receive direct instruction codes sent by the ground and on-board autonomous instruction codes sent by an on-board computer;
and 2, respectively outputting a primary command and a backup command through analysis processing, and driving a command load to act.
In step 1, the master remote control module and the backup remote control module have the same function, a system composition block diagram is shown in fig. 1, the master remote control module includes a level conversion module, a master FPGA (or ASIC) module, a latch, and an instruction driving circuit module, the two level conversion modules respectively and correspondingly receive an on-board autonomous instruction and a ground direct instruction sent by an on-board computer and the ground, the on-board autonomous instruction and the ground direct instruction are output after being processed by the master FPGA (or ASIC), and the backup remote control module and the master remote control module have the same structure composition and are not described herein again:
a direct instruction interval is set between two adjacent direct instructions sent to the ground, an autonomous instruction interval is set between two adjacent autonomous instructions sent to the satellite-borne computer, the direct instruction interval and the autonomous instruction interval are not smaller than the pulse width of an output instruction, and the pulse width of the output instruction refers to the pulse width of an output instruction of the satellite-borne remote control unit; after level conversion, the ground direct instruction and the satellite autonomous instruction become levels which can be recognized by an FPGA (field programmable gate array) (or ASIC);
in the step 2, the remote control logic function is specifically realized by an FPGA (or ASIC), and includes: the priority selection of the ground direct instruction, the direct instruction decoding and output control, the channel control of the satellite autonomous instruction and the autonomous instruction decoding and output control are carried out, and the control signals are output to the latch through the instruction queue controller;
(1) the priority of the ground direct instruction is selected according to the general rule of the spacecraft, the priority sequence of the master remote control module is different from that of the backup remote control module, four answering machines are taken as examples, the priority of the master remote control module is set to be answering machine 1- > answering machine 2- > program control- > answering machine 3- > answering machine 4, then the priority of the backup remote control module is set to be answering machine 4- > answering machine 3- > program control- > answering machine 2- > answering machine 1, namely, one path of direct instruction with the highest priority is selected, and the direct instruction is transmitted to be decoded and output for subsequent control.
(2) An autonomous instruction channel control switch is arranged on a channel control module of an on-satellite autonomous instruction, and when the on-satellite autonomous instruction fails to influence the normal work of a satellite, an 'autonomous instruction forbidding' instruction is sent, so that the autonomous instruction is not transmitted to an instruction queue controller any more, and the on-satellite fault diffusion is prevented; and when the fault is eliminated, sending an 'enable autonomous instruction' instruction, so that the autonomous instruction is transmitted to the instruction queue controller.
The command queue controller adopts a first-come first-output principle for the ground direct command and the satellite autonomous command, and if the ground direct command and the satellite autonomous command arrive at the same time, the ground direct command is output preferentially. An instruction code buffer is designed in the FPGA (or ASIC) for the direct instruction and the on-satellite autonomous instruction respectively, and a ground direct instruction and an on-satellite autonomous instruction are allowed to be buffered. The instruction output control logic is multiplexed, an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit) sets an output channel occupation identifier, the channel occupation identifier is effective in the instruction output process, and the channel occupation identifier is released to be in an idle state after the instruction output is finished. When a new instruction comes, whether the channel occupation mark is idle or not needs to be judged, the channel occupation mark is executed when the channel occupation mark is idle, and the channel occupation mark is waited for releasing when the channel occupation mark is occupied so as to ensure the sequential output of the instruction. The instruction queue controller flow is shown in figure 2.
(3) The latch module receives the output signal of the instruction queue controller and transmits the output signal to the instruction driving circuit:
the reset end of the latch module is connected with a reset signal, and the reset signal is generated when power is on and voltage is jittered, so that the output of an error instruction is effectively prevented; in addition, the command driving circuit increases the driving capability of the output command.
According to the scheme, the output of the ground direct instruction and the on-satellite autonomous instruction is controlled by the instruction queue controller, so that the ground direct instruction and the on-satellite autonomous instruction can be output in order without losing the instructions; the command queue controller allows for the caching of a ground direct command code and an on-board autonomous command code. The command queue controller firstly serves the ground direct command and the on-satellite autonomous command, and preferentially outputs the ground direct command if the ground direct command and the on-satellite autonomous command arrive at the same time.
Specifically, taking four direct instructions and four autonomous instructions as an example, the following description is divided into three cases, which are:
firstly, receiving an autonomous instruction code in the process of outputting a direct instruction by an instruction queue controller;
firstly, receiving a direct instruction code in the process of outputting an autonomous instruction by an instruction queue controller;
firstly, the instruction queue controller receives a direct instruction code and an autonomous instruction code at the same time;
in this embodiment, the pulse widths of the direct command and the autonomous command are both in the order of hundred milliseconds, so there is no strict requirement for real-time performance, and the pulse widths of the direct command and the autonomous command are taken as 100ms as an example, and the command intervals are both taken as 100ms as an example.
The following conditions are: in the process of outputting a direct instruction by the instruction queue controller, receiving an autonomous instruction code:
according to the principle of first come and first serve, for the situation that firstly, the instruction queue controller sequentially outputs a direct instruction 1, an autonomous instruction 1, a direct instruction 4 and an autonomous instruction 4, as shown in FIG. 2;
the following conditions are: in the process of outputting the autonomous instruction by the instruction queue controller, receiving a direct instruction code:
according to the principle of first come and first serve, for the situation (i), the instruction queue controller sequentially outputs an autonomous instruction 1, a direct instruction 1, an autonomous instruction 4 and a direct instruction 4, as shown in fig. 3.
The following conditions are: the instruction queue controller receives the direct instruction code and the autonomous instruction code at the same time:
the instruction queue controller outputs a direct instruction 1, an autonomous instruction 1, a direct instruction 4 and an autonomous instruction 4 in sequence for the case (i), as shown in fig. 4, according to the principle that the direct instructions on the ground are preferentially output when two instructions are received simultaneously.
The above description is only a preferred embodiment of the present invention, and not intended to limit the present invention in other forms, and any person skilled in the art may apply the above modifications or changes to the equivalent embodiments with equivalent changes, without departing from the technical spirit of the present invention, and any simple modification, equivalent change and change made to the above embodiments according to the technical spirit of the present invention still belong to the protection scope of the technical spirit of the present invention.
Claims (3)
1. A compatible processing method of a ground direct instruction and an on-board autonomous instruction is used for a satellite-borne remote control unit and is characterized by comprising the following steps:
step 1, the satellite-borne remote control unit comprises a master remote control module and a backup remote control module, wherein the master remote control module and the backup remote control module work in a hot backup mode and receive direct instruction codes sent by the ground and on-satellite autonomous instruction codes sent by a satellite-borne computer;
a direct instruction interval is set between two adjacent direct instructions sent to the ground, an autonomous instruction interval is set between two adjacent autonomous instructions sent to the satellite-borne computer, the direct instruction interval and the autonomous instruction interval are not smaller than the pulse width of an output instruction, and the pulse width of the output instruction refers to the pulse width of an output instruction of the satellite-borne remote control unit;
and 2, respectively outputting corresponding main command and backup command through the analysis processing of the main remote control module and the backup remote control module, and driving command load actions, wherein the command load actions comprise priority selection of ground direct commands, direct command decoding and output control, channel control of satellite autonomous commands and autonomous command decoding and output control:
priority selection of ground direct command: according to the universal rule of the spacecraft, different priority orders are set for the master remote control module and the backup remote control module, and one path of direct instruction with the highest priority is selected for subsequent direct instruction decoding and output control;
channel control of on-board autonomous commands: setting an autonomous instruction channel control switch, and sending an 'autonomous instruction forbidding' instruction when an autonomous instruction on the satellite fails to influence the normal work of the satellite; when the fault is eliminated, sending an 'enabling autonomous instruction' instruction to enable the autonomous instruction to be transmitted to an instruction queue controller;
the command queue controller adopts a first-come first-output principle for the ground direct command and the satellite autonomous command, and if the ground direct command and the satellite autonomous command arrive at the same time, the ground direct command is output preferentially.
2. The method for compatible processing of the ground direct instruction and the on-board autonomous instruction according to claim 1, characterized in that: in the step 1, the backup remote control module and the master remote control module have the same structural composition:
the master remote control module comprises two level conversion modules, a master FPGA/ASIC module, a latch and an instruction driving circuit module, wherein the two level conversion modules respectively and correspondingly receive an on-satellite autonomous instruction and a ground direct instruction sent by an on-board computer and the ground, and the master instruction is output through the latch and the instruction driving circuit module after being processed by the master FPGA/ASIC module;
the backup remote control module comprises two level conversion modules, a backup FPGA/ASIC module, a latch and an instruction driving circuit module, wherein the two level conversion modules respectively and correspondingly receive an on-board autonomous instruction and a ground direct instruction sent by the on-board computer and the ground, and the backup instruction is output through the latch and the instruction driving circuit module after being processed by the backup FPGA/ASIC module.
3. The method for compatible processing of the ground direct instruction and the on-board autonomous instruction according to claim 2, wherein: in the step 2:
a corresponding instruction code buffer is respectively designed for a ground direct instruction and an on-satellite autonomous instruction in the master FPGA/ASIC module and the backup FPGA/ASIC module, so that a ground direct instruction and an on-satellite autonomous instruction are allowed to be buffered;
the instruction output control logic is multiplexed, an output channel occupation identifier is arranged on the master FPGA/ASIC module and the backup FPGA/ASIC module, the channel occupation identifier is effective in the instruction output process, and the channel occupation identifier is released to be in an idle state after the instruction output is finished; and when a new instruction comes, judging whether the channel occupation mark is idle, executing the channel occupation mark when the channel occupation mark is idle, and waiting for releasing the channel occupation mark when the channel occupation mark is occupied.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113204188A (en) * | 2021-04-26 | 2021-08-03 | 中国人民解放军国防科技大学 | Multimode-driven quick-response satellite switching instruction system and design and application method thereof |
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