CN112526904A - Working mode switching control method of electronic product circuit containing FPGA - Google Patents
Working mode switching control method of electronic product circuit containing FPGA Download PDFInfo
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- CN112526904A CN112526904A CN202011349198.6A CN202011349198A CN112526904A CN 112526904 A CN112526904 A CN 112526904A CN 202011349198 A CN202011349198 A CN 202011349198A CN 112526904 A CN112526904 A CN 112526904A
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- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
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Abstract
The invention discloses a working mode switching control method of an electronic product circuit containing an FPGA (field programmable gate array), which comprises the following steps that under the condition that the operating parameter of the electronic product circuit is smaller than a first preset value required by the operation of a first working mode, the FPGA is switched to a second working mode after being electrified, and the second working mode is used for correcting the operating parameter value based on an FPGA configuration circuit; switching to a first working mode when the operation parameters are corrected to a first preset value; and in the second working mode, the FPGA configuration circuit executes a working method. According to the method, based on the judgment of the operation parameters, when the condition of entering the first working mode is not met, the operation parameters are corrected by switching to the second working mode until the condition of entering the first working mode is met, and then the first working mode is used for working, so that the auxiliary effect of starting the first working mode is realized, and the influence of the operation parameters on the first working mode is avoided.
Description
Technical Field
The invention relates to the technical field of FPGA (field programmable gate array), in particular to a working mode switching control method of an electronic product circuit containing the FPGA.
Background
The complex and various external environments can affect electronic products to different degrees, and basically, three types of external environments affect the electronic products: climate factors, mechanical factors and electromagnetic interference (noise interference). The climate factors comprise main factors such as temperature, humidity and air pressure, and also comprise salt fog, dust, mould, sunlight irradiation and the like, and the influence of low air pressure on the electronic product is shown as follows: easy breakdown; increased arcing and corona phenomena, etc. Electromagnetic interference exists in electronic products and outside the electronic products, electromagnetic waves generated by various reasons exist, and except signals to be received by equipment, the rest electromagnetic waves belong to interference. Electromagnetic interference can be divided into external interference and internal interference, and the existence of the electromagnetic interference can cause the performance parameters of the machine to change, such as unstable operation and increased noise, and can cause the machine to work abnormally in severe cases.
Therefore, in order to improve the reliability and robustness of the circuit of the electronic product, some protection measures are required to be added to avoid the influence of the external environment on the normal operation of the electronic product, and usually, the structure of the electronic circuit can be changed or an additional compensation circuit structure can be added, but the original circuit needs to be modified, which is troublesome and can affect the appearance, weight, power consumption and the like of the product.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a method for controlling the switching of the working mode of an electronic product circuit containing an FPGA, which comprises the following steps:
under the condition that the circuit operation parameters of the electronic product are smaller than a first preset value required by the operation of a first working mode, switching to a second working mode after the FPGA is powered on, wherein the second working mode is used for correcting the operation parameter values based on the FPGA configuration circuit;
switching to a first working mode when the operation parameters are corrected to a first preset value;
in the second working mode, the FPGA configuration circuit executes the following working method:
the operation parameter correction of the correcting sub-parts in the normal working state is realized by controlling the m correcting sub-parts to enter the normal working state, and then the circuit operation parameter correction of the electronic product is realized; and
and the change rate control of the operation parameters of the correction sub-part in the correction process is realized by controlling the size adjustment of the m.
As a further optimization of the above scheme, in the second operating mode, the FPGA configuration circuit further executes the following operating method:
when the FPGA detects that the self-operation parameter is larger than a first threshold value, controlling all the correction sub-parts to enter a work stopping state, and then entering a correction stopping state;
and when the FPGA detects that the self operating parameter is smaller than a second threshold value, controlling all the correction sub-parts to enter a normal working state, wherein the first threshold value is larger than the second threshold value, and the second threshold value is larger than or equal to the first preset value.
As a further optimization of the above scheme, the operating parameter is an operating temperature.
As a further optimization of the above scheme, in the second operating mode, the FPGA configuration circuit executes the following operating method:
when the FPGA detects that the working temperature of the FPGA is larger than a first threshold value, all the correction sub-parts are controlled to enter a working stop state, and the working temperature of the FPGA gradually drops; up to
When the FPGA detects that the working temperature of the FPGA is lower than a second threshold value, all the correction subsections are controlled to enter a normal working state;
and repeating the process to ensure that the working temperature of the FPGA is constant between the second threshold value and the first threshold value.
As a further optimization of the above scheme, the correcting subsection is configured with the following working method by the FPGA:
the high level and the low level are respectively used as first input signals of the first switch circuit and the second switch circuit;
when the high level is used as a second input signal of the first switch circuit and the second switch circuit, the second switch circuit outputs a signal, and only the second switch circuit outputs the first input signal;
when the low level is used as a second input signal of the first switch circuit and the second switch circuit, the first switch circuit outputs a signal and only the first switch circuit outputs the first input signal;
the first switch circuit and the second switch circuit are used as a group, n groups of circuits are connected in series end to form a correction sub-part, and n is an odd number.
As a further optimization of the above scheme, the first switch circuit adopts a PMOS transistor, the second switch circuit adopts an NMOS transistor, gates of the PMOS transistor and the NMOS transistor receive a second input signal, a source of the PMOS transistor takes a high level as its first input signal, a source of the NMOS transistor takes a low level as its first input signal, and a drain of the PMOS transistor or the NMOS transistor serves as an output terminal to output a signal.
The working mode switching control method of the electronic product circuit containing the FPGA has the following beneficial effects:
1. based on the judgment of the operation parameters, when the condition of entering the first working mode is not reached, the operation parameters are corrected by switching to the second working mode until the condition of entering the first working mode is reached, and then the operation is carried out in the first working mode, so that the auxiliary effect of starting the first working mode is realized, the influence of the current operation parameters on the first working mode is avoided, and the electronic product circuit can reliably work in various working environments.
2. In the process of correcting the self-operation parameters of the FPGA, the correction process is controlled by comparing the self-operation parameters with the first threshold and the second threshold, so that the self-operation parameters of the FPGA are always between the second threshold and the first threshold in the process of correcting the self-operation parameters of the FPGA by the m correction subsections, the stability of the operation parameters in a certain sense is kept, the FPGA is prevented from being damaged, the gradual progressive correction of all circuits in the whole electronic product circuit is realized, and the corrected circuit is prevented from being damaged.
3. The whole auxiliary circuit is based on the original FPGA in the electronic product circuit to program each circuit unit, an additional heating module is not needed to be added on the basis of the normal functions of the product to heat the electronic product circuit, the influence on the appearance, the weight, the power consumption and the like of the product is avoided, and the programming is convenient to realize.
Drawings
FIG. 1 is a flow chart of the method for controlling the switching of the operating mode of the circuit of the electronic product including the FPGA according to the present invention;
FIG. 2 is a block diagram of a second mode of operation of the correction of the operating parameter of FIG. 1 with temperature;
fig. 3 is a structural view of an embodiment of the correcting sub-section of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
It should be noted that, in the present embodiment, programming control is mainly performed based on the FPGA to implement the working mode switching control, so that the method is preferably applied to the circuit of the electronic product including the FPGA, and on this basis, the method can be implemented only by programming based on the FPGA in the circuit of the original electronic product.
Specifically, the method for controlling switching of the operating mode of the electronic product circuit of the embodiment includes:
and under the condition that the operation parameter of the electronic product circuit is smaller than a first preset value required by the operation of the first working mode, switching to a second working mode after the FPGA is powered on, wherein the second working mode is used for correcting the value of the operation parameter based on the FPGA configuration circuit, and switching to the first working mode when the operation parameter is corrected to the first preset value. When the current working temperature is low and influences the product circuit to enter a normal working state, the ambient temperature of the whole product circuit is improved by entering the second working mode first, and the starting of the product circuit is assisted.
In a second working mode, the FPGA configuration circuit executes the following working method:
the operation parameter correction of the correcting sub-parts in the normal working state is realized by controlling the m correcting sub-parts to enter the normal working state, and then the circuit operation parameter correction of the electronic product is realized; and
and the change rate control of the operation parameters of the correction sub-part in the correction process is realized by controlling the size adjustment of the m.
For the working temperature as the operation parameter, each correction sub-part can work normally without being influenced by low temperature, and can quickly generate enough heat during normal work to eliminate the influence of the current operation parameter on the first working mode of the electronic product as soon as possible.
Considering that the FPGA has the limitation of the operation parameter range, a first preset value required by the operation parameter of the electronic product circuit in a first working mode and the like, the FPGA needs to be detected for the change of the real-time operation parameter in a second working mode:
when the FPGA detects that the self-operation parameter is larger than a first threshold value, controlling all the correction sub-parts to enter a work stopping state, and then entering a correction stopping state;
and when the FPGA detects that the self operating parameter is smaller than a second threshold value, controlling all the correction sub-parts to enter a normal working state, wherein the first threshold value is larger than the second threshold value, and the second threshold value is larger than or equal to the first preset value.
According to the process, the operation parameters of the FPGA are always kept between the second threshold and the first threshold in the process of correcting the operation parameters by the m correcting subsections, and the operation parameters are kept stable in a certain sense.
For the operating temperature as the operating parameter, in order to ensure the stability of the FPGA temperature in the second operating mode, the FPGA configuration circuit executes the following operating method:
when the FPGA detects that the working temperature of the FPGA is larger than a first threshold value, all the correction sub-parts are controlled to enter a working stop state, and the working temperature of the FPGA gradually drops; up to
When the FPGA detects that the working temperature of the FPGA is lower than a second threshold value, all the correction subsections are controlled to enter a normal working state;
and repeating the process to ensure that the working temperature of the FPGA is constant between the second threshold value and the first threshold value.
The following working methods are configured by the FPGA for the correcting sub-part for realizing the rise between the temperatures of the FPGA:
the high level and the low level are respectively used as first input signals of the first switch circuit and the second switch circuit;
when the high level is used as a second input signal of the first switch circuit and the second switch circuit, the second switch circuit outputs a signal, and the second switch circuit outputs a corresponding first input signal, namely the low level;
when the low level is used as a second input signal of the first switch circuit and the second switch circuit, the first switch circuit outputs a signal, and only the first switch circuit outputs a corresponding first input signal, namely the high level;
the first switch circuit and the second switch circuit are used as a group, n groups of head and tail are connected in series to form a correction sub-part, n is an odd number, therefore, when the input of the first group is high level, the output of the first group is low level, and simultaneously, the output of the first group is high level, the output of the second group is also used as the input (low level) of the second group, and the like, the automatic current circulation of the n groups of head and tail series correction sub-parts is realized, namely, the continuous operation and continuous power consumption of the correction sub-part are realized without an additional power supply unit, and heat is provided for other circuits in an electronic product.
Preferably, the first switch circuit adopts a PMOS tube, the second switch circuit adopts an NMOS tube, and the PMOS tube and the NMOS tubeThe gate of the transistor receives a second input signal, the source of the PMOS transistor takes a high level as a first input signal, the source of the NMOS transistor takes a low level as a first input signal, the drain of the PMOS transistor or the NMOS transistor serves as an output signal, the first switch circuit and the second switch circuit can be implemented by a CMOS not gate circuit, n (n is an odd number) CMOS not gate circuits are connected in series end to form a correction sub-part, and then m correction sub-parts are copied by FPGA programming, so that the control programming of the temperature raising process of the FPGA itself is simplified based on the FPGA. In practical applications, for example, when n is 9 and m is 100, and if the delay time of one CMOS not gate is T, the frequency of one correction sub-section circuit is:
the input and output of the CMOS NOT gate circuit are continuously turned over, and power consumption is simultaneously brought. A correction sub-part circuit operates to generate power consumption of
C in the formula represents the total capacitance value in one of the modifier sub-circuits. Therefore, under the condition that the CMOS NOT gate is determined, the power consumption generated by the correction sub-part circuit is determined by the number of the CMOS NOT gates, the more the number of the CMOS NOT gates is, the more the generated power consumption is, and based on the characteristics of the CMOS NOT gates and the structural characteristics of a circuit formed by connecting n (n is an odd number) CMOS NOT gates in series end to end, a large amount of power consumption can be quickly generated, namely, the temperature heat accumulation and heat transmission of the correction sub-part circuit are accelerated, and the temperature of the whole electronic product circuit is improved in the second working mode.
In the second working mode, the power consumption generated by the CMOS NOT gate circuit controls the temperature of the FPGA and controls the total number of the CMOS NOT gate circuits in the working state at the same moment by controlling the number of m in the heat transmission process of the whole electronic product circuit, thereby realizing the adjustment of the power consumption generated by the CMOS NOT gate circuit, and under the optimal state, the process of the second working mode is as follows:
when the FPGA detects that the temperature of the FPGA is lower than a second threshold value, all CMOS NOT gate circuits are in a working state to generate power consumption; when the temperature is higher than a first threshold value, setting a high ALM signal to stop all the CMOS NOT gate circuits, and when the temperature is lowered to a second threshold value, setting a low ALM signal to enable all the CMOS NOT gate circuits to be in a working state to generate power consumption; the steps are repeated, so that the temperature of the FPGA is stabilized within the range of the set target temperature.
In the repeated process, the FPGA transmits heat to the outside simultaneously, so that the temperature of other circuits in the circuit of the electronic product is gradually increased, the FPGA detects the temperature of a plurality of areas in the circuit of the electronic product, and when the temperature of the plurality of areas reaches a first preset value of the working temperature required by the operation of the first working mode, the FPGA starts to switch to the first working mode, so that the circuit of the electronic product rapidly enters a normal working state.
The present invention is not limited to the above-described embodiments, and those skilled in the art will be able to make various modifications without creative efforts from the above-described conception, and fall within the scope of the present invention.
Claims (6)
1. A working mode switching control method of an electronic product circuit containing an FPGA is characterized by comprising the following steps:
under the condition that the circuit operation parameters of the electronic product are smaller than a first preset value required by the operation of a first working mode, switching to a second working mode after the FPGA is powered on, wherein the second working mode is used for correcting the operation parameter values based on the FPGA configuration circuit;
switching to a first working mode when the operation parameters are corrected to a first preset value;
in the second working mode, the FPGA configuration circuit executes the following working method:
the operation parameter correction of the correcting sub-parts in the normal working state is realized by controlling the m correcting sub-parts to enter the normal working state, and then the circuit operation parameter correction of the electronic product is realized; and
and the change rate control of the operation parameters of the correction sub-part in the correction process is realized by controlling the size adjustment of the m.
2. The method according to claim 1, wherein in the second operating mode, the FPGA configuration circuit further performs the following steps:
when the FPGA detects that the self-operation parameter is larger than a first threshold value, controlling all the correction sub-parts to enter a work stopping state, and then entering a correction stopping state;
and when the FPGA detects that the self operating parameter is smaller than a second threshold value, controlling all the correction sub-parts to enter a normal working state, wherein the first threshold value is larger than the second threshold value, and the second threshold value is larger than or equal to the first preset value.
3. The method as claimed in claim 2, wherein the operating parameter is operating temperature.
4. The method according to claim 3, wherein in the second operating mode, the FPGA configuration circuit performs the following steps:
when the FPGA detects that the working temperature of the FPGA is larger than a first threshold value, all the correction sub-parts are controlled to enter a working stop state, and the working temperature of the FPGA gradually drops; up to
When the FPGA detects that the working temperature of the FPGA is lower than a second threshold value, all the correction subsections are controlled to enter a normal working state;
and repeating the process to ensure that the working temperature of the FPGA is constant between the second threshold value and the first threshold value.
5. The method for controlling switching of operation modes of an electronic product circuit comprising an FPGA according to any one of claims 3 or 4, wherein the modifying sub-section is configured by the FPGA to operate as follows:
the high level and the low level are respectively used as first input signals of the first switch circuit and the second switch circuit;
when the high level is used as a second input signal of the first switch circuit and the second switch circuit, the second switch circuit outputs a signal, and only the second switch circuit outputs the first input signal;
when the low level is used as a second input signal of the first switch circuit and the second switch circuit, the first switch circuit outputs a signal and only the first switch circuit outputs the first input signal;
the first switch circuit and the second switch circuit are used as a group, n groups of circuits are connected in series end to form a correction sub-part, and n is an odd number.
6. The method as claimed in claim 5, wherein the first switch circuit is a PMOS transistor, the second switch circuit is an NMOS transistor, gates of the PMOS transistor and the NMOS transistor receive the second input signal, a source of the PMOS transistor has a high level as its first input signal, a source of the NMOS transistor has a low level as its first input signal, and a drain of the PMOS transistor or the NMOS transistor serves as the output signal.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101790623A (en) * | 2007-08-28 | 2010-07-28 | 戴姆勒股份公司 | Operating and diagnostic method for an scr exhaust-gas aftertreatment system |
| CN107276804A (en) * | 2017-06-19 | 2017-10-20 | 深圳市盛路物联通讯技术有限公司 | A kind of method and apparatus for the working condition for correcting terminal device |
| CN107631447A (en) * | 2017-09-30 | 2018-01-26 | 广东美的制冷设备有限公司 | Progress control method, operating control device, air conditioner and storage medium |
| US20180067810A1 (en) * | 2016-09-02 | 2018-03-08 | Alibaba Group Holding Limited | Method and system of high-availability pcie ssd with software-hardware jointly assisted implementation to enhance immunity on multi-cell upset |
| CN110287028A (en) * | 2019-06-24 | 2019-09-27 | 深圳市腾讯网域计算机网络有限公司 | The method and relevant apparatus of one mode switching |
| CN110515437A (en) * | 2019-08-16 | 2019-11-29 | 苏州浪潮智能科技有限公司 | A kind of high-temperature protection method and device of FPGA accelerator card |
-
2020
- 2020-11-26 CN CN202011349198.6A patent/CN112526904A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101790623A (en) * | 2007-08-28 | 2010-07-28 | 戴姆勒股份公司 | Operating and diagnostic method for an scr exhaust-gas aftertreatment system |
| US20180067810A1 (en) * | 2016-09-02 | 2018-03-08 | Alibaba Group Holding Limited | Method and system of high-availability pcie ssd with software-hardware jointly assisted implementation to enhance immunity on multi-cell upset |
| CN107276804A (en) * | 2017-06-19 | 2017-10-20 | 深圳市盛路物联通讯技术有限公司 | A kind of method and apparatus for the working condition for correcting terminal device |
| CN107631447A (en) * | 2017-09-30 | 2018-01-26 | 广东美的制冷设备有限公司 | Progress control method, operating control device, air conditioner and storage medium |
| CN110287028A (en) * | 2019-06-24 | 2019-09-27 | 深圳市腾讯网域计算机网络有限公司 | The method and relevant apparatus of one mode switching |
| CN110515437A (en) * | 2019-08-16 | 2019-11-29 | 苏州浪潮智能科技有限公司 | A kind of high-temperature protection method and device of FPGA accelerator card |
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Application publication date: 20210319 |