CN112509937B

CN112509937B - Electric on-off test method for double-sided substrate

Info

Publication number: CN112509937B
Application number: CN202011376754.9A
Authority: CN
Inventors: 李宝霞
Original assignee: Zhuhai Tiancheng Advanced Semiconductor Technology Co ltd
Current assignee: Zhuhai Tiancheng Advanced Semiconductor Technology Co ltd
Priority date: 2020-11-30
Filing date: 2020-11-30
Publication date: 2023-06-30
Anticipated expiration: 2040-11-30
Also published as: CN112509937A

Abstract

The invention discloses an on-off test method of a double-sided substrate, which comprises the following steps of 1, in the preparation process of the double-sided substrate, etching is not carried out on a front electroplating seed layer, and the front electroplating seed layer is reserved; step 2, completing the back process of the double-sided substrate on the double-sided substrate with the front electroplating seed layer reserved, etching the back electroplating seed layer, then performing a first single-sided probe test on the back protruding points of the double-sided substrate, and measuring the connection relationship between every two back protruding points; step 3: etching the front electroplating seed layer in the area except the front salient points, performing a second single-sided probe test on the front salient points of the double-sided substrate, and measuring the connection relationship between every two front salient points; step 4: and (3) combining the first single-sided probe test result in the step (2) and the second single-sided probe test result in the step (3) to obtain the electric connection test result between the bumps on the front and back surfaces of the double-sided substrate. The method solves the problem of the on-off test of the silicon transfer substrate wafer and is suitable for automatic mass production test.

Description

Electric on-off test method for double-sided substrate

Technical Field

The invention belongs to the technical field of advanced electronic packaging, and particularly relates to an on-off test method of a double-sided substrate.

Background

For many years, the technology development speed of package substrates including ceramic substrates and organic substrates is far lower than that of integrated circuit IC chips, currently, advanced integrated circuit IC chips mostly adopt the outer pin form of micro-bump arrays, the pin number is very thousands, the pin density is increased, and meanwhile, the large size of the IC chips, low-K dielectric layers are very challenging to the traditional package substrates such as ceramic substrates, organic substrates and the like with poor flatness and obvious thermal mismatch. TSV silicon Interposer (Si Interposer) was introduced as a bridge between advanced integrated circuit IC chips and conventional package substrates such as ceramic substrates, organic substrates, and the like. One or more IC chips are micro-assembled on the TSV silicon transfer substrate, and interconnection among the plurality of IC chips is completed by utilizing low-loss and high-density metal wiring on the surface of the TSV silicon transfer substrate, so that the number and density of the whole outer pins are reduced; and through the electrical interconnection of the TSV conductive through holes in the vertical direction, the transfer of the IC chip on the TSV silicon transfer substrate to the traditional packaging substrate such as a ceramic substrate, an organic substrate and the like is realized. The TSV Interposer provides a good quality chip integration platform: the high-speed signal interconnection is supported by good thermal matching, the parasitic influence of RCL is reduced, the power consumption and ESD requirements are reduced, the signal conduction, heat transfer and mechanical support are realized, the mechanical stress buffering effect is realized, and the technical gap between the IC chip and the traditional packaging substrate is filled.

Typically, both the upper and lower surfaces of the TSV interposer substrate are distributed with pin pads or (micro) bumps that enable electrical interconnection in the vertical direction through TSV conductive vias. The thickness of the TSV (Through-Silicon-Via) Through substrate is mainly in the range of 200 micrometers to 50 micrometers, which is limited by the diameter and aspect ratio of the TSV hole and the consideration of the electrical signal transmission capability of the TSV hole. Because the silicon material is fragile and fragile, especially for a large-size (8 inches, 12 inches) TSV silicon transfer substrate wafer with the thickness below 100 microns, the wafer has large warpage, weak stress capability and high risk of breaking fragments, and the double-sided flying needle test is difficult to directly carry out by adopting a traditional flying needle probe station.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides an on-off test method of a double-sided substrate, solves the on-off test problem of an ultrathin large-size silicon transfer substrate wafer, is compatible with the prior commercial equipment, and is suitable for automatic mass production test.

In order to achieve the above purpose, the present invention provides the following technical solutions:

a method for testing the on/off state of double-sided substrate includes such steps as,

step 1, in the preparation process of a double-sided substrate, etching is not performed on the front electroplating seed layer, and the front electroplating seed layer is reserved;

step 2, completing the back process of the double-sided substrate on the double-sided substrate with the front electroplating seed layer reserved, etching the back electroplating seed layer, then performing a first single-sided probe test on the back protruding points of the double-sided substrate, and measuring the connection relationship between every two back protruding points;

step 3, etching the front electroplating seed layer of the area except the front salient points, performing a second single-sided probe test on the front salient points of the double-sided substrate, and measuring the connection relationship between every two front salient points;

and 4, combining the first single-sided probe test result in the step 2 and the second single-sided probe test result in the step 3 to obtain the electric connection test result between the bumps on the front and back surfaces of the double-sided substrate.

Preferably, in step 1, blind holes and front metal wiring are first completed in the preparation process of the double-sided substrate, and after the preparation of the front bump lower metal layer and the front bump, the complete electroplating seed layer is reserved.

Furthermore, the front metal wiring is horizontally and electrically connected and arranged on the front of the silicon substrate, when the front metal wiring is multi-layer, the front metal wiring layers are electrically insulated through front metal interlayer dielectric, and the electrical connection between the front metal wiring layers is realized through the connecting holes between the front metal wiring layers.

Preferably, in step 2, before the first single-sided probe test is performed on the back bump, the front surface of the double-sided substrate and the front carrier are temporarily bonded together, and the back surface of the double-sided substrate is thinned, so that the blind holes form conductive through holes, then the back metal wiring and the back bump are sequentially performed, and the electroplating seed layer is etched, so that the back process of the double-sided substrate is completed.

In step 3, before the second single-sided probe test is performed on the front bump, temporarily bonding the back surface of the double-sided substrate and the back carrier, and de-bonding the front carrier, removing the front carrier, and exposing the front surface of the double-sided substrate.

Further, the back metal wiring is horizontally and electrically connected and arranged on the back of the silicon substrate, when the back metal wiring is multi-layer, the back metal wiring layers are electrically insulated through back metal interlayer dielectric, and the electrical connection between the back metal wiring layers is realized through the connecting holes between the back metal wiring layers.

Preferably, the front surface under bump metal layer or the back surface under bump metal layer is prepared by adopting patterned electroplating.

Preferably, in step 2, all the front bumps are in parallel short circuit relationship when the back bumps are subjected to the first single-sided probe test.

Preferably, the double-sided substrate is a TSV silicon transfer substrate, a TGV glass transfer substrate or an organic substrate.

Compared with the prior art, the invention has the following beneficial technical effects:

the invention provides an electric on-off test method of a double-sided substrate, which is characterized in that a wafer-level electric on-off probe test is combined with a preparation process flow of the double-sided substrate, the double-sided probe test is needed by an original double-sided substrate wafer to perform vertical electric interconnection on-off detection of a through hole, the double-sided probe test is converted into two single-sided probe tests, and the interconnection on-off test which can be completed by the double-sided probe test is realized by the two single-sided probe tests in the preparation process flow. The electric connection and disconnection relations between the front salient points and the back salient points of the TSV silicon transfer substrate are judged by measuring the electric connection and disconnection relations between the salient points of the back of the TSV silicon transfer substrate and the electric connection and disconnection relations between the salient points of the front of the TSV silicon transfer substrate respectively, and the electric connection and disconnection test problem of the ultrathin double-sided substrate is solved by replacing one-time double-sided probe test with two-time single-sided probe test.

Furthermore, the front and back sides of the double-sided substrate are temporarily bonded with the slide glass, so that the two single-sided testing processes are performed under the condition that the double-sided substrate wafer is bonded with the slide glass, although the thickness of the double-sided substrate wafer is very thin and is generally smaller than 200 micrometers, because the double-sided substrate wafer is supported and protected by the slide glass, the problem of splinter and fragments in the processes of transferring, testing and holding is avoided, and the implementation of the testing process and the automatic mass production testing operation are facilitated.

Drawings

Fig. 1 is a schematic cross-sectional view of a TSV silicon interposer substrate according to an embodiment of the present invention.

Fig. 2 is a schematic diagram of electrical connection between bumps on the upper and lower surfaces of a TSV substrate according to an embodiment of the present invention.

Fig. 3 is a diagram showing an electrical connection relationship between bumps on the upper and lower surfaces of a TSV interposer substrate according to an embodiment of the present invention.

Fig. 4 is a schematic cross-sectional view of a substrate with blind TSV, front side multi-layer metal wiring, and front side bumps completed according to an embodiment of the present invention.

Fig. 5 is a schematic cross-sectional view illustrating a backside process of a TSV silicon transfer substrate in accordance with an embodiment of the present invention.

Fig. 6 is a diagram showing an electrical connection relationship between upper and lower surface bumps when a first single-sided probe test is performed on the bumps on the back surface of the TSV silicon adapter substrate according to an embodiment of the present invention.

Fig. 7 is a schematic cross-sectional view of an embodiment of the present invention after temporarily bonding the backside of the TSV silicon interposer substrate to the backside carrier 16 and removing the front side carrier 14 from the front side of the TSV silicon interposer substrate.

FIG. 8 is a schematic cross-sectional view of a partial area of a front side under bump metallization layer etched away according to an embodiment of the present invention.

In the accompanying drawings: 1 is a silicon substrate; 2 is a conductive through hole; 3 is front metal wiring; 4 is a front metal interlayer medium; 5 is a front electroplating seed layer; 6 is a front bump lower metal layer; 7 is a front bump; 8 is a back metal wiring; 9 is a back metal interlayer medium; 10 is a backside plating seed layer; 11 is a back bump lower metal layer; 12 is a back bump; 13 is a front temporary bonding adhesive layer; 14 is a front slide; 15 is a back temporary bonding adhesive layer; 16 is a back slide.

Detailed Description

The invention will now be described in further detail with reference to specific examples, which are intended to illustrate, but not to limit, the invention.

The invention provides an electric on-off test method of a double-sided substrate, which is not only suitable for the electric on-off test of an ultrathin TSV silicon transfer substrate wafer, but also suitable for the electric on-off test of an ultrathin TGV glass transfer substrate wafer, and can be also used for the electric on-off test of an ultrathin organic substrate, namely suitable for the electric on-off test of all ultrathin double-sided substrates. The following embodiments take TSV through-silicon substrate as an example.

Examples

As shown in fig. 1, TSV conductive vias 2 through a silicon substrate 1 provide electrical connection between the upper and lower surfaces of the silicon substrate 1. The front metal wiring 3 is arranged on the upper surface of the silicon substrate 1 in a horizontal electrical connection way, the number of layers of the front metal wiring 3 is at least 1, when the front metal wiring 3 is multiple layers, the front metal wiring 3 of each layer is electrically insulated through a front metal interlayer medium 4, and the electrical connection between the front metal wirings 3 of each layer is realized through the connecting holes between each layer. The front bump 7 is electrically connected to the front metal wiring 3 through a front Under Bump Metallization (UBM) 6. Correspondingly, the back metal wirings 8 are horizontally and electrically connected and arranged on the lower surface of the silicon substrate 1, the number of layers of the back metal wirings 8 is at least 1, when the back metal wirings 8 are multi-layer, the back metal wirings 8 of each layer are electrically insulated through a back metal interlayer medium 9, and the electrical connection between the back metal wirings 8 of each layer is realized through the connecting holes between each layer. The back bump 12 is electrically connected to the back metal wiring 8 through a back Under Bump Metal (UBM) 11.

As shown in fig. 2, the electrical connection relationship between the bumps on the upper and lower surfaces of the TSV silicon transfer substrate is that the front bumps A1, B1, A2, B2, A3, B3, A4 and B4 are electrically connected to the back bumps A1', B1', A2', B2', A3', B3', A4 'and B4' through respective corresponding TSV conductive vias 2, and the electrical connection and disconnection relationship between every two bumps is divided into four cases: (1) the convex points A1, B1 and A1', B1' are as shown in FIG. 2: bumps A1 and B1 are not electrically conductive in the front side metal wiring layer, and bumps A1 'and B1' are not electrically conductive in the back side metal wiring layer. (2) the convex points A2, B2 and A2', B2' are as shown in figure 2: bumps A2 and B2 are not electrically conductive in the front side metal wiring layer and bumps A2 'and B2' are electrically conductive in the back side metal wiring layer. (3) As shown in fig. 2 with bumps A3, B3 and A3', B3', bumps A3 and B3 are electrically conductive in the front side metal wiring layer and bumps A3 'and B3' are not electrically conductive in the back side metal wiring layer. (4) the convex points A4, B4 and A4', B4' are as shown in FIG. 2: bumps A3 and B3 are electrically conductive in the front side metal wiring layer and bumps A3 'and B3' are electrically conductive in the back side metal wiring layer.

As shown in fig. 3, fig. 3 is a simplified diagram of the electrical connection relationship between the bumps on the upper and lower surfaces of the TSV substrate in fig. 2, which shows the electrical connection/disconnection relationship between the bumps on the upper and lower surfaces of the TSV substrate. Where ports A1, B1, A2, B2, A3, B3, and A4, B4 represent bumps (or pads) on the front side (upper surface) of the TSV interposer substrate, and ports A1', B1', A2', B2', A3', B3', and A4', B4' represent bumps (or pads) on the back side (lower surface) of the TSV interposer substrate. The TSV conductive via 2 between the upper and lower surfaces is represented by a section of wiring. Whether a plurality of bumps (or pads) on one surface are routed through one TSV via to another surface or one bump (or pad) on one surface is routed through a plurality of TSV vias to another surface, it is simplified to one bump and one TSV via.

As shown in fig. 4, after the TSV silicon transfer substrate completes the preparation of the TSV blind via, the front side metal wiring 3, and the front side Under Bump Metal (UBM) 6 and the front side bump 7, the front side plating seed layer 5 under the front side Under Bump Metal (UBM) 6 in other areas of the surface is not temporarily etched away, but the front side plating seed layer 5 under the complete front side Under Bump Metal (UBM) 6 is left, and all the front side bumps 7 are electrically connected together by the front side plating seed layer 5 under the front side Under Bump Metal (UBM) 6, so as to be a buried pen for the subsequent back side single-sided probe test of the TSV silicon transfer substrate. The front side temporary bonding adhesive layer 13 temporarily bonds the front side of the TSV interposer substrate to the front side carrier 14.

As shown in fig. 5, the back side plating seed layer 10 under the Under Bump Metallurgy (UBM) 11 in other areas of the surface is normally etched away after the Under Bump Metallurgy (UBM) 11 and the back side bump 12 are prepared, unlike the front side.

As shown in fig. 6, fig. 6 is a diagram showing an electrical connection relationship between the upper and lower surface bumps when the first single-sided probe test is performed on the bump on the backside of the TSV silicon interposer substrate. All the front bumps 7 are in parallel short circuit relationship.

As shown in fig. 7, fig. 7 is a schematic cross-sectional view of the TSV silicon interposer substrate after temporarily bonding the backside of the TSV silicon interposer substrate to the backside carrier 16 and removing the front side carrier 14 from the TSV silicon interposer substrate front side. The front side of the TSV silicon interposer substrate is exposed while the front side plating seed layer 5 under the front side Under Bump Metallization (UBM) 6 remains intact over the TSV silicon interposer substrate. Temporary bonding between the backside of the TSV interposer substrate and the backside carrier 16 is achieved by a backside temporary bonding adhesive layer 15.

As shown in fig. 8, fig. 8 is a schematic cross-sectional view of the front side Under Bump Metallurgy (UBM) 6 after the front side plating seed layer 5 has been etched away. The front side Under Bump Metallurgy (UBM) layer 5 in the other regions than the front side bump 7 and the UBM (UBM) 6 in fig. 7 is etched away, so that the front side bumps are separated and the front side Under Bump Metallurgy (UBM) layer 6 is separated, as shown in fig. 8. And performing a second single-sided probe test on the bump on the front surface of the TSV silicon transfer substrate.

The backside carrier 16 shown in fig. 8 is then de-bonded and removed to form the finished TSV interposer substrate as shown in fig. 1.

In summary, the process of preparing the TSV silicon transfer substrate is as follows: (1) Firstly, preparing TSV blind holes on a silicon substrate 1, then preparing front metal wiring 3, and then preparing front protruding points 7 to finish front process preparation of a TSV silicon transfer substrate; (2) Temporarily bonding the front-side processed TSV silicon transfer substrate and the front-side carrier 14 together to perform a back-side process of the TSV silicon transfer substrate; (3) Thinning the back surface of the TSV silicon transfer substrate, exposing the bottom conductive material of the TSV blind hole to enable the TSV blind hole to be changed into a TSV conductive through hole 2, and then sequentially carrying out back metal wiring 8 and back protruding points 12 to finish back process preparation of the TSV silicon transfer substrate; (4) The TSV silicon interposer substrate is separated from the backside carrier 16 to complete the TSV silicon interposer substrate preparation.

The front Under Bump Metal (UBM) 6 or the back Under Bump Metal (UBM) 11 is usually prepared by a patterning electroplating method, that is, a whole layer of front electroplating seed layer 5 under the front Under Bump Metal (UBM) or back electroplating seed layer 10 under the back Under Bump Metal (UBM) is prepared by PVD, evaporation and sputtering, then a photoresist is coated thereon, the pattern of the front Under Bump Metal (UBM) 6 or the back Under Bump Metal (UBM) 11 is exposed and developed, and then the front Under Bump Metal (UBM) 6 or the back Under Bump Metal (UBM) 11 with a certain thickness is electroplated; when the front bump 7 or the back bump 12 is a plating bump, the front bump 7 or the back bump 12 is directly plated after the front Under Bump Metal (UBM) 6 or the back Under Bump Metal (UBM) 11 is plated; the front side Under Bump Metallization (UBM) patterns are then separated or the back side Under Bump Metallization (UBM) patterns are separated by etching away the front side plating seed layer 5 or the back side plating seed layer 10 under the front side Under Bump Metallization (UBM) elsewhere. When the front bump 7 or the back bump 12 is not a plating bump, or the front or the back of the TSV silicon transfer substrate does not need the front bump 7 or the back bump 12, but only needs to form a pad on the front Under Bump Metal (UBM) 6 or the back Under Bump Metal (UBM) 11, and later use, the pad pattern on the front Under Bump Metal (UBM) 6 or the back Under Bump Metal (UBM) 11 needs to be surface treated, such as electroless nickel-palladium-gold or electroless nickel-gold-plating. In summary, no matter whether the front surface or the back surface of the TSV silicon transfer substrate needs bumps or pads, an Under Bump Metal (UBM) layer is required, a whole layer of plating seed layer under the Under Bump Metal (UBM) layer is deposited on the entire surface of the TSV silicon transfer substrate during the process of preparing the Under Bump Metal (UBM), and finally the plating seed layer under the Under Bump Metal (UBM) layer in the non-bump or non-pad area of the TSV silicon transfer substrate is etched.

For ultrathin TSV silicon transfer substrate wafers, particularly those with a thickness of less than 150 microns, the wafer is thin, fragile and fragile, and the risk of performing double-sided probe testing is high, so that the wafer is not easy to implement. The invention combines the wafer-level electrical on-off probe test with the preparation process flow of the TSV silicon transfer substrate, and realizes the TSV interconnection on-off test which can be finished only by the double-sided probe test through the two single-sided probe tests in the preparation process.

The method for testing the on/off of the TSV silicon transfer substrate comprises the following specific implementation processes:

step 1: after the TSV through-substrate wafer completes the preparation of the TSV blind via, the front side metal wiring 3, and the front side Under Bump Metallization (UBM) 6 and the front side bump 7, the front side plating seed layer 5 under the front side Under Bump Metallization (UBM) elsewhere on the surface is not temporarily etched away, but the front side plating seed layer 5 under the complete front side Under Bump Metallization (UBM) remains, as shown in fig. 4.

Step 2: the front surface of the TSV silicon transfer substrate and the front carrier 14 are temporarily bonded together, the back surface of the TSV silicon transfer substrate is thinned to expose the bottom conductive material of the TSV blind hole, then the back metal wiring 8 and the back bump 12 are sequentially performed, and the back electroplating seed layer 10 under the back Under Bump Metal (UBM) at other places on the back surface is etched, thereby completing the back process preparation of the TSV silicon transfer substrate, as shown in fig. 5. At this time, the first single-sided probe test is performed on the backside bumps 12 of the TSV silicon interposer substrate, and the connection relationship between every two backside bumps 12 is measured.

Step 3: the back surface of the TSV silicon transfer substrate and the back surface carrier 16 are temporarily bonded together, and the front surface carrier 14 on the front surface of the TSV silicon transfer substrate is de-bonded, and the front surface carrier 14 on the front surface of the TSV silicon transfer substrate is removed and cleaned to expose the front surface of the TSV silicon transfer substrate, as shown in fig. 7.

Step 4: the front side Under Bump Metallization (UBM) 6 and the front side plating seed layer 5 under the front side Under Bump Metallization (UBM) in other areas than the front side bumps of the TSV interposer substrate are etched away as shown in fig. 8. And performing a second single-sided probe test on the front bumps 7 of the TSV silicon transfer substrate wafer, and measuring the connection relationship between every two front bumps 7.

Step 5: and combining the two single-sided probe test results to obtain the electrical connection test result between the bumps on the upper surface and the lower surface of the TSV silicon transfer substrate.

In the preparation process of the TSV silicon transfer substrate, the test and the process are combined, the electrical disconnection relation between the front bumps 7 and the back bumps 12 of the TSV silicon transfer substrate is judged by measuring the electrical disconnection connection relation between the back bumps 12 and the electrical disconnection relation between the front bumps 7 of the TSV silicon transfer substrate, and the electrical disconnection test problem of the ultrathin double-sided substrate is solved by replacing one-time double-sided probe test with two-time single-sided probe test.

The front bumps are electrically connected in parallel when probes are punched on the two rear bumps 12 to measure the electrical disconnection between the two rear bumps. The electrical connection between the front bump 7 and the back bump 12 on the TSV silicon transfer substrate is shown in fig. 2 and fig. 3, and can be regarded as four-port networks, and each four-port network determines the on-off relationship between four ports through the on-off relationship between two ports. Four cases are divided: first case: one TSV via (and its front and back RDL layers and front and back bumps) is electrically isolated from the other TSV via (and its front and back RDL layers and front and back bumps), which is often the case between signal lines, address lines and control line vias, between power lines and ground lines, and between signal lines, address lines, control lines and power lines, ground lines; second case: one TSV through hole and another TSV through hole are electrically connected together in a front RDL layer, and the situation that two or more front bumps on a TSV silicon transfer substrate have the same pin definition is often found, and the two or more front bumps can be used for power pins and ground pins; third case: one TSV via is electrically connected with another TSV via in the backside RDL layer, which is often the case when two or more backside bumps on the TSV interposer substrate have the same pin definition, and can be used for power and ground pins; fourth case: one TSV via is electrically connected to another TSV via in both the front RDL layer and the back RDL layer, which is often the case where two or more front bumps and two or more back bumps have the same pin definition, such as power and ground pins

In the four cases, the bump electrical connection relationship between the bumps at the two ends of the through hole of the TSV and whether the bump electrical connection relationship can be directly detected in the two single-sided probe tests in sequence disclosed by the invention are respectively detected, and meanwhile, whether the bump electrical connection relationship can be indirectly detected and indirectly judged according to the combination of the two single-sided probe test results is shown in tables 1-4.

In the first case described above: the first single-sided probe test is performed on the back bump of the TSV silicon transfer substrate, the short-circuit relationship between the front bumps A1 and B1 and the corresponding back bumps A1 'and B1' can be directly detected, but the open-circuit relationship between the front bumps A1 and B1 and the corresponding back bumps A1 'and B1' cannot be detected, but the second single-sided probe test is performed on the front bump of the TSV silicon transfer substrate wafer, so that the open-circuit relationship between the front bumps A1 and the corresponding back bumps A1, B1 and A1 'and B1' can be determined, and therefore, the electrical connection relationship between the front bumps A1 and the corresponding back bumps A1, B1 'and B1' can be determined in the first case by integrating the two single-sided probe tests.

In the second case described above: the short-circuit relationship between the front and back bumps A2, B2, A2', B2' cannot be determined from the first single-sided probe test on the back bump of the TSV silicon interposer substrate, but the short-circuit relationship between the front and back bumps A2, B2, A2', B2' can be determined from the second single-sided probe test on the front bump of the TSV silicon interposer substrate wafer, so that the on-off relationship between the front and back bumps A2, B2, A2', B2' can be determined in the second case by combining the above two single-sided probe tests.

In the third case described above: the first single-sided probe test is performed on the back bump of the TSV silicon transfer substrate to judge whether the short circuit relationship between the front bumps A3 and B3 and the corresponding back bumps A3 'and B3' is normal, and the judgment of the short circuit relationship between the front bumps A3 and B3 and the corresponding back bumps A3 'and B3' is of reference significance although the short circuit relationship between the front bumps A3 and B3 and the corresponding back bumps A3 'and B3' cannot be judged; from the second single-sided probe test of the front bump of the TSV silicon interposer substrate wafer, the short-circuit relationship between the front bumps A3 and B3 can be determined, and although the short-circuit relationship between the front bump A3 and the back bump B3', between the front bump B3 and the back bump A3', and between the back bumps A3 'and B3' cannot be determined, the same has a reference meaning, and the short-circuit relationship between the front bump A3 and the back bump B3', between the front bump B3 and the back bump A3', and between the back bumps A3 'and B3' can be indirectly determined by integrating the above-described two probe test results. Therefore, the two single-sided probe tests can be combined to judge the on-off relation between the front and back bumps A3, B3, A3', B3' in the second case.

In the fourth case described above: whether the first single-sided probe test is performed on the back bump of the TSV silicon interposer substrate or the second single-sided probe test is performed on the front bump of the TSV silicon interposer substrate, the short-circuit relationship between the front and back bumps A4, B4, A4', B4' in the fourth case cannot be exactly determined. However, since the front bumps A4 and B4 are electrically connected together in the front RDL layer, the back bumps A4' and B4' are electrically connected together in the back RDL layer, and the pins of the front bumps A4 and B4 are defined identically, the front bumps A4 and B4' are defined identically in the test network, and the back bumps A4' and B4' are considered identical, and the four-port network (A4, B4, A4', B4 ') can be considered as a two-port network (a4+b4, A4' +b4 ') that can be reconfigured into a four-port network by connecting with other front bumps and back bumps on the TSV silicon interposer substrate to determine the electrical connection and disconnection relationship between a4+b4 and a4' +b4 '.

TABLE 1 Electrical insulation of two TSV vias (front and rear RDL layers and front and rear bumps)

TABLE 2 case where two TSV vias are electrically connected through the front RDL layer

TABLE 3 case where two TSV vias are electrically connected through the backside RDL layer

TABLE 4 case where two TSV vias are electrically connected through both front RDL and rear RDL layers simultaneously

Claims

1. The method for testing the on/off of the double-sided substrate is characterized by comprising the following steps of,

step 1, in the preparation process of a double-sided substrate, the front electroplating seed layer (5) is not etched, and the front electroplating seed layer (5) is reserved;

step 2, completing the back surface process of the double-sided substrate on the double-sided substrate with the front surface electroplating seed layer (5) reserved, etching the back surface electroplating seed layer (10), then performing a first single-sided probe test on the back surface convex points (12) of the double-sided substrate, and measuring the connection relationship between every two back surface convex points (12) in an on-off manner;

etching a front electroplating seed layer (5) in a region except for the front protruding points (7), performing a second single-sided probe test on the front protruding points (7) of the double-sided substrate, and measuring the connection relationship between every two front protruding points (7) in an on-off manner;

2. The method for testing the electrical connection and disconnection of the double-sided substrate according to claim 1, wherein in the step 1, the blind holes, the front metal wiring (3) are firstly completed in the preparation process of the double-sided substrate, and the whole electroplating seed layer (5) is reserved after the preparation of the front under bump metal layer (6) and the front bump (7).

3. The method for testing the on/off of the double-sided substrate according to claim 2, wherein the front metal wires (3) are horizontally and electrically connected and arranged on the front surface of the silicon substrate (1), when the front metal wires (3) are multi-layered, the front metal wires (3) of each layer are electrically insulated by a front metal interlayer medium (4), and the electrical connection between the front metal wires (3) of each layer is realized by a connecting hole between each layer.

4. The method for testing the electrical connection and disconnection of the double-sided substrate according to claim 1, wherein in the step 2, before the first single-sided probe test is performed on the back bump (12), the front surface of the double-sided substrate and the front carrier (14) are temporarily bonded together, the back surface of the double-sided substrate is thinned, so that the blind holes form the conductive through holes (2), then the back metal wiring (8) and the back bump (12) are sequentially performed, and the electroplating seed layer (10) is etched, thereby completing the back surface process of the double-sided substrate.

5. The method for testing on/off of a double-sided substrate according to claim 4, wherein in step 3, before the front bump (7) is subjected to the second single-sided probe test, the back surface of the double-sided substrate and the back carrier (16) are temporarily bonded together, and the front carrier (14) Jie Jian is bonded, and the front carrier (14) is removed to expose the front surface of the double-sided substrate.

6. The method for testing on/off of a double-sided substrate according to claim 4, wherein the back metal wires (8) are arranged in a horizontal electrical connection on the back surface of the silicon substrate (1), and when the back metal wires (8) are multi-layered, the back metal wires (8) of each layer are electrically insulated by a back metal interlayer medium (9), and the electrical connection between the back metal wires (8) of each layer is realized by a connection hole between the layers.

7. The method for testing the electrical on/off of the double-sided substrate according to claim 2, wherein the front under bump metal layer (6) is prepared by using patterned electroplating.

8. The method for testing on/off of a double-sided substrate according to claim 1, wherein in step 2, all the front bumps (7) are in parallel short-circuit relationship when the back bumps (12) are subjected to the first single-sided probe test.

9. The method for testing on/off of double-sided substrate according to claim 1, wherein the double-sided substrate is a TSV silicon interposer substrate, a TGV glass interposer substrate, or an organic substrate.