CN112492404A

CN112492404A - Multiplexing interface device and MAC system

Info

Publication number: CN112492404A
Application number: CN202011301949.7A
Authority: CN
Inventors: 张贞雷; 刘同强; 周玉龙; 王贤坤
Original assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Current assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Priority date: 2020-11-19
Filing date: 2020-11-19
Publication date: 2021-03-12
Anticipated expiration: 2040-11-19
Also published as: CN112492404B

Abstract

The invention discloses a multiplexing interface device and an MAC system, which comprise a first interface controller, an interface conversion module, an output interface selector and a clock generation module. The multiplexing interface device can provide PHY interfaces of different types at the same time, and selects a corresponding interface to output according to the interface type adaptive to the currently connected PHY, so that the flexibility of MAC is improved, and the burden of a user is reduced; meanwhile, the clock generation module can complete clock conversion of different interfaces, and further reduces burden of users and complexity of actual use.

Description

Multiplexing interface device and MAC system

Technical Field

The present invention relates to the field of communication interfaces, and in particular, to a multiplexing interface device and an MAC system.

Background

A data interaction manner between a conventional MAC (ethernet Media connection controller) and a PHY (physical Interface transceiver) is as shown in fig. 1, where the MAC outputs only one Interface for communicating with the PHY, such as MII (Media Independent Interface), RMII (Reduced Media Independent Interface, Reduced MII Interface), GMII (Gigabit MII Interface), RGMII (Reduced Media Independent Interface, Reduced GMII Interface), and one PHY has only one type of Interface, so when one MAC communicates with different PHYs, an additional Interface protocol conversion module is often required to be added to implement Interface adaptation between the MAC and the PHY.

For example, the MAC only outputs the GMII interface, and when the user 1 applies the PHY of the RGMII interface, the user 1 needs to implement protocol conversion from GMII to RGMII by itself; when the user 2 applies the PHY of the MII interface, the user 2 needs to implement GMII-MII protocol conversion by itself. That is to say, for different application scenarios, additional interface protocol conversion workload is required to implement interface adaptation between the MAC and the PHY, which greatly reduces the flexibility of the MAC and increases the burden of the user. Meanwhile, each interface has different working rates, and working clocks corresponding to the different working rates are different, so that a user needs to complete interface conversion and clock conversion, and the burden of the user and the complexity of actual use are further increased.

Therefore, how to provide a solution to the above technical problem is a problem that needs to be solved by those skilled in the art.

Disclosure of Invention

The multiplexing interface device can simultaneously provide PHY interfaces of different types, and selects a corresponding interface to output according to the interface type adaptive to the currently connected PHY, so that the flexibility of the MAC is improved, and the burden of a user is reduced; meanwhile, the clock generation module can complete clock conversion of different interfaces, and further reduces burden of users and complexity of actual use.

To solve the above technical problem, the present invention provides a multiplexing interface device, including:

the first interface controller is arranged on the MAC and used for outputting a first interface;

the interface conversion module is connected with the first interface controller and is used for converting the first interface into different types of interface output;

the output interface selector is respectively connected with the first interface controller, the interface conversion module and the PHY and is used for selecting a target interface adaptive to the currently connected PHY from different types of interfaces connected with the output interface selector to be connected to the PHY;

and the clock generation module is respectively connected with the MAC, the first interface controller and the interface conversion module and is used for generating a clock signal meeting the current communication requirements of the MAC and the PHY according to the current working rate of the MAC and the interface type adaptive to the current connected PHY and correspondingly providing the clock signal to a clock signal line of the target interface.

Preferably, the first interface controller is a GMII controller for outputting a GMII interface;

and the interface conversion module includes:

the RGMII conversion submodule is respectively connected with the GMII controller and the output interface selector and is used for converting the GMII interface into an RGMII interface to be output;

the MII conversion submodule is respectively connected with the GMII controller and the output interface selector and is used for converting the GMII interface into an MII interface to be output;

and the RMII conversion submodule is respectively connected with the MII conversion submodule and the output interface selector and is used for converting the MII interface into RMII interface output.

Preferably, the GMII interface includes a GTX _ CLK signal representing a transmission clock generated by the clock generation module, a TX _ ER signal representing a transmission data error, a TX _ EN signal representing transmission enable, a TXD [7:0] signal representing transmission data, a RX _ CLK signal representing a reception clock generated by the PHY, a RX _ DV signal representing reception data valid, a RX _ ER signal representing a reception data error, a RXD [7:0] signal representing reception data, a CRS signal representing carrier sense, a COL signal representing collision sense, an MDIO signal representing management data, and an MDC signal representing a management data clock.

Preferably, the RGMII interface includes a GTX _ CLK signal, a TX _ CTL signal for conveying both TX _ EN signal and TX _ ER signal, a TXD [3:0] signal representing transmitted data, a RX _ CLK signal, a RX _ CTL signal for conveying both RX _ DV signal and RX _ ER signal, a RXD [3:0] signal representing received data, a CRS signal, a COL signal, an MDIO signal, and a MDC signal; wherein the RGMII interface multiplexes the same signals as the GMII interface;

correspondingly, the RGMII conversion sub-module includes:

the transmitting clock rising edge sampling unit is respectively connected with the GTX _ CLK signal and the TXD [7:0] signal, and is used for sampling the low 4-bit signal at the rising edge of the GTX _ CLK signal to obtain a low 4-bit transmitting signal; outputting the TX _ EN signal to the TX _ CTL signal on a rising edge of the GTX _ CLK signal;

the transmitting clock falling edge sampling unit is respectively connected with the GTX _ CLK signal and the TXD [7:0] signal, and is used for sampling the high 4-bit signal at the falling edge of the GTX _ CLK signal to obtain a high 4-bit transmitting signal; outputting the TX _ ER signal to the TX _ CTL signal on a falling edge of the GTX _ CLK signal;

the input end of the MUX selector is connected with the transmitting clock rising edge sampling unit and the transmitting clock falling edge sampling unit respectively, and the output end of the MUX selector is used as a TXD [3:0] signal and is used for controlling the low 4-bit transmitting signal and the high 4-bit transmitting signal to be alternately output according to the current working rate of the MAC;

the receiving clock rising edge sampling units are respectively connected with the RX _ CLK signal and the RXD [3:0] signal and are used for sampling the RXD [3:0] signal at the rising edge of the RX _ CLK signal to obtain a high-4-bit receiving signal; the RX _ CTL signal is sampled at the rising edge of the RX _ CLK signal and then output to an RX _ DV signal;

the receiving clock falling edge sampling units are respectively connected with the RX _ CLK signal and the RXD [3:0] signal and are used for sampling the RXD [3:0] signal at the falling edge of the RX _ CLK signal to obtain a low-4-bit receiving signal; the RX _ CTL signal is sampled at the falling edge of the RX _ CLK signal and then output to the RX _ ER signal;

the COM combined module is used for combining and outputting the low 4-bit receiving signal and the high 4-bit receiving signal according to the current working speed of the MAC, wherein the input end of the COM combined module is respectively connected with the receiving clock rising edge sampling unit and the receiving clock falling edge sampling unit, and the output end of the COM combined module is used as a TXD [7:0] signal.

Preferably, the MII interface includes TX _ CLK, TX _ ER, TX _ EN, TXD [3:0], RX _ CLK, RX _ DV, RX _ ER, RXD [3:0], CRS, COL, MDIO, MDC signals representing a transmit clock generated by the PHY; wherein the MII interface multiplexes the same signals as the GMII interface;

correspondingly, the MII conversion sub-module includes:

the low-4 bit taking-out unit is respectively connected with the TX _ CLK signal and the TXD [7:0] signal and is used for intercepting the low-4 bit signals of the TXD [7:0] signal under the driving of the TX _ CLK signal and outputting the signals as TXD [3:0] signals;

and the high 4-bit 0 complementing unit is respectively connected with the RX _ CLK signal and the RXD [3:0] signal and is used for outputting the high 4-bit 0 complementing signal of the RXD [3:0] signal as the RXD [7:0] signal under the driving of the RX _ CLK signal.

Preferably, the MII conversion sub-module further includes:

and the interruption unit is used for generating interruption if the current work rate of the MAC is 1000MBps and prompting the current output interface of the MAC to select errors.

Preferably, the RMII interface includes a REF _ CLK signal representing a reference clock generated by the clock generation module, a TX _ EN signal, a TXD [1:0] signal representing transmitted data, an RX _ ER signal, an RXD [1:0] signal representing received data, a CRS _ DV signal combined by an RX _ DV signal and a CRS signal, an MDIO signal, and an MDC signal; the RMII interface multiplexes the same signals as the MII interface; the TX _ CLK signal and the RX _ CLK signal in the MII conversion sub-module are generated by the clock generation module instead;

correspondingly, the RMII conversion sub-module includes:

a TX _ CNT counter connected with a REF _ CLK signal and used for triggering a reading instruction every 1 clock cycle of the REF _ CLK signal when the current working speed of the MAC is 100 MBps; when the current working speed of the MAC is 10MBps, triggering a reading instruction every 10 clock cycles of the REF _ CLK signal;

the TX _ FIFO unit is used for writing TXD [3:0] signals into the TX _ FIFO unit under the enabling of the TX _ EN signal and the driving of the TX _ CLK signal; after receiving the reading instruction, firstly reading a low 2-bit signal of the TXD [3:0] signal as a TXD [1:0] signal, and then reading a high 2-bit signal of the TXD [3:0] signal as a TXD [1:0] signal;

an RX _ CNT counter coupled to the REF _ CLK signal for triggering a write command every 1 clock cycle of the REF _ CLK signal when a current operating rate of the MAC is 100 MBps; when the current working speed of the MAC is 10MBps, triggering a write-in instruction every 10 clock cycles of the REF _ CLK signal;

the RX _ FIFO unit is respectively connected with an RX _ CLK signal, an RXD [1:0] signal, a CSR _ DV signal and the RX _ CNT counter and is asynchronous to read and write, and is used for writing the RXD [1:0] signal into the RX _ FIFO unit under the condition that the CSR _ DV signal is effective and after the write instruction is received so as to sequentially form 4-bit effective data; the 4-bit valid data are read out sequentially as RXD [3:0] signals, driven by the RX _ CLK signal.

Preferably, the clock generation module includes:

a first frequency divider coupled to a LOCAL _ CLK signal representing a LOCAL clock for generating a corresponding clock frequency for the GMII/RGMII conversion sub-module based on a current operating rate of the MAC;

a second frequency divider coupled to the EXT _ CLK signal representing an external input clock and configured to generate a TX _ CLK signal, an RX _ CLK signal, and a REF _ CLK signal for the RMII conversion sub-module based on a current operating rate of the MAC;

and the clock gating units are respectively connected with the first frequency divider and the second frequency divider and used for gating the clock signal matched with the interface type adaptive to the currently connected PHY and supplying the clock signal to the corresponding conversion sub-modules.

Preferably, the MAC is directly connected to the PHY; and the MAC and the PHY transmit MDIO signals and MDC signals through a direct connection line between the MAC and the PHY.

In order to solve the above technical problem, the present invention further provides an MAC system, which includes an MAC and any one of the multiplexing interface devices.

The invention provides a multiplexing interface device which comprises a first interface controller, an interface conversion module, an output interface selector and a clock generation module. The first interface controller is arranged on the MAC and used for outputting a first interface; the interface conversion module is used for converting the first interface into different types of interface output; the output interface selector is used for selecting a target interface adaptive to the currently connected PHY from different types of interfaces connected with the output interface selector to be connected to the PHY; the clock generation module is used for generating a clock signal meeting the current communication requirements of the MAC and the PHY according to the current working speed of the MAC and the interface type adaptive to the PHY currently connected, and correspondingly providing the clock signal to a clock signal line of a target interface. Therefore, the multiplexing interface device can provide PHY interfaces of different types at the same time, and selects the corresponding interface to output according to the interface type adaptive to the currently connected PHY, thereby improving the flexibility of MAC and reducing the burden of a user; meanwhile, the clock generation module can complete clock conversion of different interfaces, and further reduces burden of users and complexity of actual use.

The invention also provides an MAC system which has the same beneficial effect with the multiplexing interface device.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a diagram illustrating a data interaction between a MAC and a PHY in the prior art;

fig. 2 is a schematic structural diagram of a multiplexing interface device according to an embodiment of the present invention;

fig. 3 is a schematic structural diagram of a multiplexing interface device according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a GMII _ RGMII _ CTRL sub-module according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of a GMII _ MII _ CTRL submodule according to an embodiment of the present invention;

FIG. 6 is a schematic diagram of a design of a MII _ RMII _ CTRL sub-module according to an embodiment of the present invention;

fig. 7 is a schematic design diagram of a CLOCK _ GEN submodule according to an embodiment of the present invention.

Detailed Description

The core of the invention is to provide a multiplexing interface device and an MAC system, wherein the multiplexing interface device can simultaneously provide PHY interfaces of different types, and select a corresponding interface to output according to the interface type adaptive to the currently connected PHY, thereby improving the flexibility of the MAC and reducing the burden of a user; meanwhile, the clock generation module can complete clock conversion of different interfaces, and further reduces burden of users and complexity of actual use.

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a multiplexing interface device according to an embodiment of the present invention.

The multiplexing interface device includes:

a first interface controller 1 provided on the MAC for outputting a first interface;

the interface conversion module 2 is connected with the first interface controller 1 and is used for converting the first interface into different types of interface output;

the output interface selector 3 is respectively connected with the first interface controller 1, the interface conversion module 2 and the PHY, and is used for selecting a target interface adaptive to the currently connected PHY from different types of interfaces connected with the output interface selector 3 to be connected with the PHY;

and the clock generation module 4 is respectively connected with the MAC, the first interface controller 1 and the interface conversion module 2 and is used for generating a clock signal meeting the current communication requirements of the MAC and the PHY according to the current working rate of the MAC and the interface type adaptive to the current connected PHY and correspondingly providing the clock signal to a clock signal line of a target interface.

Specifically, the multiplexing interface device of the present application includes a first interface controller 1, an interface conversion module 2, an output interface selector 3, and a clock generation module 4, and its working principle is:

the first interface controller 1 is arranged on the MAC, and the first interface controller 1 can output a first interface. The interface conversion module 2 is connected with the first interface controller 1, and can convert the first interface output by the first interface controller 1 into different types of interface output. One end of the output interface selector 3 is connected to the first interface controller 1 and the interface conversion module 2, and the other end is connected to the PHY, so as to select a target interface adapted to the currently connected PHY from the first interface output by the first interface controller 1 and other different types of interfaces output by the interface conversion module 2 to connect to the PHY (physically, one interface is an external interface of the multiplexing interface device), so as to implement interface adaptation between the MAC and the PHY.

And, the present application is further provided with a clock generation module 4, which can generate a clock signal meeting the current communication requirements of the MAC and the PHY according to the current working rate of the MAC and the type of the interface adapted to the PHY currently connected, and correspondingly provide the clock signal to a clock signal line of a target interface adapted to the PHY currently connected, so as to implement communication between the MAC and the PHY.

On the basis of the above-described embodiment:

referring to fig. 3, fig. 3 is a schematic structural diagram of a multiplexing interface device according to an embodiment of the present invention.

As an alternative embodiment, the first interface controller 1 is a GMII controller for outputting a GMII interface;

and the interface conversion module 2 includes:

the RGMII conversion submodule is respectively connected with the GMII controller and the output interface selector 3 and is used for converting the GMII interface into the RGMII interface to be output;

the MII conversion submodule is respectively connected with the GMII controller and the output interface selector 3 and is used for converting the GMII interface into an MII interface to be output;

and the RMII conversion submodule is respectively connected with the MII conversion submodule and the output interface selector 3 and is used for converting the MII interface into RMII interface output.

Specifically, four interfaces between MAC and PHY are introduced first:

1) the MII interface contains 16 signals and 2 management interface signals. The MII interface transfers data bi-directionally in 4-bit bytes. When the clock rate corresponding to the MII interface is 25MHz, the working rate of the MAC can reach 100 Mb/s; when the clock rate corresponding to the MII interface is 2.5MHz, the working rate of the MAC can reach 10 Mb/s.

TABLE 1

Signal name	Description of the invention	Direction
			TX_CLK	Transmission clock	PHY→MAC
TX_ER	Error of transmission data	MAC→PHY
			TX_EN	Transmit enable	MAC→PHY
TXD[3:0]	Transmitting data	MAC→PHY
			RX_CLK	Receiving clock	PHY→MAC
RX_DV	Receiving data efficiently	PHY→MAC
			RX_ER	Received data errors	PHY→MAC
RXD[3:0]	Receiving data	PHY→MAC
			CRS	Carrier monitoring	PHY→MAC
COL	Collision collision monitoring	PHY→MAC
			MDIO	Managing data	Bidirectional
MDC	Managing data clocks	MAC→PHY

RXD [3:0 ]: the data receiving signals are 4 signal lines in total. TX _ ER: sending a data error prompt signal which is synchronous with TX _ CLK, is effective at a high level and indicates that data transmitted in the TX _ ER validity period is invalid; for a 10Mbps rate, TX _ ER does not work. RX _ ER: receiving a data error prompt signal, synchronizing with RX _ CLK, enabling a high level to indicate that data transmitted in the RX _ ER validity period are invalid; for a 10Mbps rate, RX _ ER does not work. TX _ EN: an enable signal is sent and only data that is transmitted during the TX _ EN validity period is valid. RX _ DV: the data valid signal is received and acts like TX _ EN for the transmit channel. TX _ CLK: sending a data reference clock, wherein the clock frequency is 25MHz at the rate of 100 Mbps; at 10Mbps rate, the clock frequency is 2.5 MHz. Note that the direction of the TX _ CLK clock is from the PHY side to the MAC side, so the clock is provided by the PHY. RX _ CLK: receiving a data reference clock, wherein the clock frequency is 25MHz at the rate of 100 Mbps; at 10Mbps rate, the clock frequency is 2.5 MHz. RX _ CLK is also provided by the PHY side. CRS: the CRS is valid as long as there is data transmission, and in addition, the CRS is valid only in the PHY half-duplex mode. COL: the collision detection signal, which need not be synchronized to the reference clock, is only valid for the PHY in half-duplex mode.

2) The RMII interface saves half of the data lines compared with the MII interface. The RMII interface transmits and receives 2-bit data and adopts a 50MHz clock source. In a 100Mbps Ethernet rate, the MAC layer samples data on RXD [1:0] once per clock. In a 10Mbps Ethernet rate, the MAC layer samples the data on RXD [1:0] every 10 clocks, and each data received by the physical layer will remain for 10 clocks at RXD [1:0 ].

TABLE 2

Signal name	Description of the invention	Direction
			REF_CLK	Reference clock	External clock provision
TX_EN	Transmit enable	MAC→PHY
			TXD[1:0]	Transmitting data	MAC→PHY
RX_ER	Received data errors	PHY→MAC
			RXD[1:0]	Receiving data	PHY→MAC
CRS_DV	Carrier and received data validation	PHY→MAC
			MDIO	Managing data	Bidirectional
MDC	Managing data clocks	MAC→PHY

The CRS _ DV is the combination of RX _ DV and CRS in an MII interface, and when a physical layer receives a carrier signal, the CRS _ DV becomes effective and sends data to the RXD. It should be noted that the RMII interface differs from the MII interface not only in halving the data lines, but also in that: the TX _ CLK and RX _ CLK of the MII interface are passed to the MAC by the PHY, while only one clock (50M REF _ CLK) on the RMII interface is provided externally to both the MAC and PHY.

3) The GMII interface adopts 8-bit interface data, and the working clock is 125MHz, so the transmission rate can reach 1000 Mbps. The GMII interface is compatible with 10/100Mbps operation mode specified by the MII interface, and uses TX _ CLK and 4 of 8 data lines when used in MII mode. At the rate of 100Mbps, the working clock is 25MHz, and the data is 4bits lower; and when the rate of 10Mbps is high, the working clock is 2.5MHz, and the data is low by 4 bits.

TABLE 3

It should be noted that: the transmit reference clock GTX _ CLK is different from TX _ CLK in the MII interface, which is provided to the MAC chip by the PHY chip, and GTX _ CLK in the GMII interface is provided to the PHY chip by the MAC chip.

4) RGMII interface compared to GMII interface, RGMII interface has the following features: the number of the transmitting/receiving data lines is changed from 8 to 4, and the clock frequency is 125MHz (double-edge sampling) at the rate of 1 Gbit/s; at a rate of 100Mbit/s, the clock frequency is 25MHz (single edge sampling); at a rate of 10Mbit/s, the clock frequency is 2.5MHz (single edge sampling).

TABLE 4

Signal name	Description of the invention	Direction
			GTX_CLK	Transmission clock	MAC→PHY
TX_CTL	Transmission control	MAC→PHY
			TXD[3:0]	Transmitting data	MAC→PHY
RX_CLK	Receiving clock	PHY→MAC
			RX_CTL	Reception control	PHY→MAC
RXD[3:0]	Receiving data	PHY→MAC
			CRS	Carrier monitoring	PHY→MAC
COL	Collision collision monitoring	PHY→MAC
			MDIO	Managing data	Bidirectional
MDC	Managing data clocks	MAC→PHY

The clock frequency of RGMII is still 125MHz and the TX/RX data width is changed from 8 to 4bits, and the RGMII interface samples data on both the rising and falling edges of the clock in order to keep the transmission rate of 1000Mbps constant. TXD [3:0]/RXD [3:0] in the GMII interface is transmitted on the rising edge of the reference clock, and TXD [7:4]/RXD [7:4] in the GMII interface is transmitted on the falling edge of the reference clock. RGMI is also compatible with both 100Mbps and 10Mbps rates, when the reference clock rates are 25MHz and 2.5MHz, respectively. The TX _ CTL signal line is used for transmitting two kinds of information of TX _ EN and TX _ ER, the TX _ EN is transmitted on the rising edge of TX _ CLK, and the TX _ ER is transmitted on the falling edge; similarly, the RX _ CTL signal line carries both RX _ DV and RX _ ER information, with RX _ DV being transmitted on the rising edge of RX _ CLK and RX _ ER being transmitted on the falling edge.

Based on the description of the four interfaces between the MAC and the PHY, it can be seen from the interface signal definitions (including clocks) of MII/RMII/GMII/RGMII that many of the internal structures/functions overlap, although these protocols are different, so the present application takes advantage of this point to fully utilize the logic function of the GMII controller, and the MII/RGMII performs partial modification (including clocks) based on the GMII controller to respectively implement RGMII/MII controllers (corresponding to GMII _ RGMII _ CTRL/GMII _ MII _ CTRL in fig. 3), and output corresponding RGMII/MII interfaces, and the RMII interface is a multiplexing GMII _ MII _ CTRL, corresponding to MII _ RMII _ CTRL in fig. 3, and outputs an RMII interface. The PHY _ INTF _ MUX is an output interface selector 3, and selects a corresponding interface to output according to a specific interface of the PHY in a current application scene. CLOCK _ GEN is a CLOCK generation module 4, and only generates a CLOCK for an interface controller corresponding to the current PHY interface type, and closes an interface controller CLOCK that cannot be used, thereby greatly reducing power consumption.

That is, GMII _ CTRL is a stand-alone GMII controller that outputs the GMII interface for use with the PHY of the GMII interface. GMII _ RGMII _ CTRL is based on the RGMII controller (i.e., RGMII conversion sub-module) of the GMII controller, outputting RGMII interface, for use with the PHY of the RGMII interface. GMII _ MII _ CTRL is based on the MII controller (i.e., MII conversion sub-module) of the GMII controller, outputting the MII interface, and is used in cooperation with the PHY of the MII interface. MII _ RMII _ CTRL is based on the RMII controller (namely RMII conversion sub-module) of GMII _ MII _ CTRL, and outputs RMII interface to be used with PHY of RMII interface. The principle of reducing the power consumption is that a CLOCK is generated only for an interface controller corresponding to the current PHY interface type, for example, when the PHY chip is of the GMII interface type, the CLOCK _ GEN only outputs the CLOCK of a GMII channel, and the CLOCKs of the GMII _ RGMII _ CTRL, GMII _ MII _ CTR and MII _ RMII _ CTRL sub-modules are closed; when the PHY chip type is the RGMII interface type, because the RGMII controller multiplexes GMII _ CTRL, the CLOCK _ GEN only outputs the CLOCKs of the GMII _ CTRL and GMII _ RGMII _ CTRL sub-modules, and the CLOCKs of the GMII _ MII _ CTRL and MII _ RMII _ CTRL sub-modules are closed; when the PHY chip type is the MII interface type, because the MII controller multiplexes GMII _ CTRL, the CLOCK _ GEN only outputs the CLOCKs of the GMII _ CTRL and GMII _ MII _ CTRL sub-modules, and the CLOCKs of the GMII _ RGMII _ CTRL and MII _ RMII _ CTRL sub-modules are closed; when the PHY chip type is the RMII interface type, because the RMII controller multiplexes the MII controller and the MII controller multiplexes the GMII controller, the CLOCK _ GEN outputs only the CLOCKs of the GMII _ CTRL, GMII _ MII _ CTRL, and MII _ RMII _ CTRL sub-modules, and the CLOCK of the GMII _ RGMII _ CTRL sub-module is turned off.

As an alternative embodiment, the GMII interface includes a GTX _ CLK signal indicating a transmission clock generated by the clock generation module 4, a TX _ ER signal indicating a transmission data error, a TX _ EN signal indicating transmission enable, a TXD [7:0] signal indicating transmission data, an RX _ CLK signal indicating a reception clock generated by the PHY, an RX _ DV signal indicating reception data is valid, an RX _ ER signal indicating a reception data error, an RXD [7:0] signal indicating reception data, a CRS signal indicating carrier sense collision, a coio signal indicating management data, an MDIO signal indicating management data, and an MDC signal indicating a management data clock.

Specifically, the description of the present embodiment has been mentioned in the above embodiments, and the description of the present application is omitted here.

Referring to fig. 4, fig. 4 is a schematic diagram of a design of a GMII _ RGMII _ CTRL sub-module according to an embodiment of the present invention.

As an alternative embodiment, the RGMII interface includes the GTX _ CLK signal, the TX _ CTL signal used to convey both the TX _ EN signal and the TX _ ER signal, the TXD [3:0] signal representing the transmitted data, the RX _ CLK signal, the RX _ CTL signal used to convey both the RX _ DV signal and the RX _ ER signal, the RXD [3:0] signal representing the received data, the CRS signal, the COL signal, the MDIO signal, the MDC signal; wherein the RGMII interface multiplexes the same signal as the GMII interface;

accordingly, the RGMII conversion sub-module includes:

the input end of the COM combination module is respectively connected with the receiving clock rising edge sampling unit and the receiving clock falling edge sampling unit, and the output end of the COM combination module is used as a TXD [7:0] signal, and the COM combination module is used for combining and outputting a low 4-bit receiving signal and a high 4-bit receiving signal according to the current working speed of the MAC.

Specifically, as shown in FIG. 4, the GMII _ RGMII _ CTRL sub-module functionally resolves:

the TX side: converting the sending time sequence of the GMII into the sending time sequence of the RGMII, firstly dividing Tx _ GMII _ data [7:0] input by the GMII into two paths, wherein one path is low 4bits, namely Tx _ GMII _ data [3:0 ]; one way is 4bits high, namely Tx _ gmii _ data [7:4 ]. Where Tx _ gmii _ data [3:0] is sampled with the rising edge of TX _ CLK, and Tx _ gmii _ data [7:4] is sampled with the falling edge of TX _ CLK. Then, the two sampling results are input into a MUX selector, and the MUX selector selects according to a current working rate MAC _ speed signal (1000 MBps/100MBps/10MBps, in practical application, the signal is obtained by self-negotiation between a local MAC and a MAC of an opposite terminal). When the MAC _ speed signal is only that the current MAC is in 1000MBps mode, the MUX selector outputs Tx _ gmii _ data [3:0] to Tx _ gmii _ data [3:0] on the rising edge of TX _ CLK, and the MUX selector outputs Tx _ gmii _ data [7:4] to Tx _ rgmii _ data [3:0] on the falling edge of TX _ CLK. When the MAC _ speed signal indicates that the current MAC is in 100MBps/10MBps mode, the MUX selector outputs Tx _ gmii _ data [3:0] to Tx _ rgmii _ data [3:0] only on the rising edge of TX _ CLK. On the falling edge of TX _ CLK, the data remains unchanged. The TX _ EN signal is sent to TX _ CTL on the rising edge of TX _ CLK and the TX _ ER signal is sent to TX _ CTL on the falling edge of TX _ CLK.

RX side: the sending time sequence of the RGMII is converted into the sending time sequence of the GMII, Tx _ RGMII _ data [3:0] is sampled respectively at the rising edge and the falling edge of RX _ CLK to obtain Tx _ RGMII _ high _ data [3:0] and Tx _ RGMII _ low _ data [3:0], and then the Tx _ RGMII _ high _ data [3:0] is sent to a COM combination module. And the COM combination module performs combination according to the mac _ speed signal. When the MAC _ speed signal indicates that the current MAC is in 1000MBps mode, the COM combining module combines Rx _ rgi _ high _ data [3:0] and Rx _ rgi _ data [3:0] into RX _ rmi _ data [7:0]

(RX_gmii_data[7:4]＝Rx_rgmii_high_data[3:0]，

RX _ gmii _ data [3:0] ═ RX _ rgmii _ high _ data [3:0 ]). When the MAC _ speed signal indicates that the current MAC is in 100MBps/100MBps mode, the COM combining module combines Rx _ rgi _ data [3:0] and 0 into RX _ gmii _ data [7:0] on the rising edge of RX _ CLK,

(RX _ gmii _ data [7:4] ═ 4' H0, RX _ gmii _ data [3:0] ═ RX _ rgmii _ data [3:0 ]). RX _ CTL is sampled at the rising edge of RX _ CLK and output to RX _ DV signal, and RX _ CLK is sampled at the falling edge of RX _ CLK and output to RX _ ER signal.

And (3) the other: COS signals and COL signals are directly transmitted through the GMII _ RGMII _ CTRL submodule without being processed.

Referring to fig. 5, fig. 5 is a schematic diagram of a design of a GMII _ MII _ CTRL submodule according to an embodiment of the present invention.

As an alternative embodiment, the MII interface includes TX _ CLK, TX _ ER, TX _ EN, TXD [3:0], RX _ CLK, RX _ DV, RX _ ER, RXD [3:0], CRS, COL, MDIO, MDC signals representing the PHY generated transmit clock; wherein, the MII interface multiplexes the same signal as the GMII interface;

correspondingly, the MII conversion sub-module includes:

Specifically, as shown in FIG. 5, the GMII _ MII _ CTRL submodule functionally resolves:

the TX side: driven by the CLOCK TX _ CLK at the PHY input (note that in GMII mode TX _ CLK is generated by CLOCK _ GEN), the transmit data TX _ GMII _ data [7:0] of GMII is truncated, with only the lower 4bits being truncated as the output data TX _ mii _ data [3:0 ].

RX side: driven by a clock RX _ CLK input from the PHY, the high-order complement 4 'H0 of RX _ mii _ data [3:0], then RX _ GMII _ data [7:0] { 4' H0, RX _ mii _ data [3:0] }, is input to the GMII controller.

Meanwhile, the controller inputs a MAC _ speed signal, because the MII controller only supports 100/10MBps mode, if the rate mode indicated by the MAC _ speed is 1000MBps, the module generates interruption, and prompts that the current MAC output interface is selected wrongly and needs to be selected again are performed.

And (3) the other: and the signals TX _ EN, TX _ ER, RX _ DV, RX _ ER, CRS and COL are directly transmitted without being processed.

As an alternative embodiment, the MII conversion sub-module further includes:

and the interrupt unit is used for generating interrupt if the current work rate of the MAC is 1000MBps and prompting the current output interface selection error of the MAC.

Referring to fig. 6, fig. 6 is a schematic diagram of a design of an MII _ RMII _ CTRL sub-module according to an embodiment of the present invention.

As an alternative embodiment, the RMII interface includes a REF _ CLK signal representing a reference clock generated by the clock generation module 4, a TX _ EN signal, a TXD [1:0] signal representing transmission data, an RX _ ER signal, an RXD [1:0] signal representing reception data, a CRS _ DV signal combined by the RX _ DV signal and the CRS signal, an MDIO signal, and an MDC signal; the RMII interface multiplexes signals the same as the MII interface; the TX _ CLK signal and the RX _ CLK signal in the MII conversion sub-module are generated by the clock generation module 4 instead;

correspondingly, the RMII conversion sub-module includes:

the TX _ CNT counter is connected with the REF _ CLK signal and is used for triggering a reading instruction every 1 clock cycle of the REF _ CLK signal when the current working speed of the MAC is 100 MBps; when the current working rate of the MAC is 10MBps, triggering a reading instruction every 10 clock cycles of the REF _ CLK signal;

the TX _ FIFO unit is used for writing the TXD [3:0] signals into the TX _ FIFO unit under the enabling of the TX _ EN signal and the driving of the TX _ CLK signal; after receiving a read command, reading a low 2-bit signal of the TXD [3:0] signal as a TXD [1:0] signal, and then reading a high 2-bit signal of the TXD [3:0] signal as a TXD [1:0] signal;

the RX _ CNT counter is connected with the REF _ CLK signal and is used for triggering a write command every 1 clock cycle of the REF _ CLK signal when the current working speed of the MAC is 100 MBps; when the current working rate of the MAC is 10MBps, triggering a write-in instruction every 10 clock cycles of the REF _ CLK signal;

the RX _ FIFO unit is respectively connected with the RX _ CLK signal, the RXD [1:0] signal, the CSR _ DV signal and the RX _ CNT counter and is asynchronous to read and write, and is used for writing the RXD [1:0] signal into the RX _ FIFO unit under the condition that the CSR _ DV signal is effective and after a write-in instruction is received so as to sequentially form 4-bit effective data; the 4-bit valid data are read out sequentially as RXD [3:0] signals, driven by the RX _ CLK signal.

Specifically, as shown in FIG. 6, the MII _ RMII _ CTRL sub-module functionally resolves:

the TX side: under the drive of TX _ CLK, Tx _ mii _ data is written into TX _ FIFO _ ASYNC, wherein the TX _ FIFO _ ASYNC realizes the function of reading and writing asynchronous TX _ FIFO controller, the writing end data is 4bits, the reading end data is 2bits, and the low 2bits of the 4bits of the input end data are read and written first, and then the high 2bits are read.

Meanwhile, the clock of the write end of the TX _ FIFO _ ASYNC is TX _ CLK (25 MHz in 100MBps mode; 2.5MHz in 10MBps mode), and the enable signal of the write end is TX _ EN.

The clock at the read side is REF _ CLK (100/10MBps mode, which is 50MHz), and the read enable signal is associated with the TX _ CNT counter, which reads TX _ FIFO _ ASYNC every REF _ CLK clock cycle when mac _ speed indicates that the current mode of operation is 100MBps mode. When mac _ speed indicates that the current operation mode is 10MBps, the TX _ FIFO _ ASYNC is read once when the count period is 10 (i.e., the value of TX _ CNT is 9). The counter TX _ CNT is driven by REF _ CLK, has an initial value of 0, and is reset to 0 after counting to 9. That is, in 10MBps mode, TX _ FIFO _ ASYNC is read once every 10 REF _ CLK cycles.

Note that: the RMII protocol does not require the TX _ ER signal, and therefore the MII TX _ ER signal does not need to be accessed to this module.

RX side: the reverse process is performed on the TX side.

Driven by RX _ CLK, RX _ rmii _ data [1:0] is written to RX _ FIFO _ ASYNC. Wherein RX _ FIFO _ ASYNC is a read-write asynchronous RX _ FIFO controller, the clock at its write end is RX _ CLK, the data enable at the write end is CSR _ DV, and the write enable is controlled by RX _ CNT. When the mac _ speed signal indicates that the current operating mode is 100MBps mode and CSR _ DV is high, RX _ rmii _ data [1:0] is written to RX _ FIFO _ ASYNC. While the mac _ speed signal indicates that the current operating mode is 10MBps mode, when CSR _ DV is high and RX _ CNT has a count period of 10(RX _ CNT is 9), RX _ rmii _ data [1:0] is written into RX _ FIFO _ ASYNC. The counter RX _ CNT is driven by REF _ CLK, has an initial value of 0, and is reset to 0 after counting to 9. That is, in 10MBps mode, RX _ FIFO _ ASYNC is written once every 10 REF _ CLK cycles.

It should be noted that, when storing the write data, the RX _ FIFO _ ASYNC stores the first valid RX _ rmii _ data [1:0], then stores the second valid RX _ rmii _ data [1:0], and then stores the valid data after forming 4 bits.

A reading end: under the drive of RX _ CLK, 4bits of valid data RX _ mii _ data [3:0] are read out.

CRS _ COL _ GEN: the submodule generates CRS, COL signals in the MII protocol. According to the inclusion of these signals themselves, the processing is as follows:

CRS＝TX_EN|CSR_DV；

COL＝TX_EN&CSR_DV；

RX _ DV is generated by RX _ FIFO _ ASYNC read logic, and when there is a valid RX _ mii _ data [3:0] read, RX _ DV is set to 1.

Referring to fig. 7, fig. 7 is a schematic design diagram of a CLOCK _ GEN submodule according to an embodiment of the present invention.

As an alternative embodiment, the clock generation module 4 includes:

a second frequency divider coupled to the EXT _ CLK signal representing the external input clock and configured to generate a TX _ CLK signal, a RX _ CLK signal, and a REF _ CLK signal for the RMII conversion sub-module based on a current operating rate of the MAC;

Specifically, as shown in fig. 7, the CLOCK _ GEN submodule performs functional analysis:

the main function of the CLOCK _ GEN submodule is to generate a CLOCK signal corresponding to the current PHY interface type based on PHY _ intf (indicating the PHY interface type in the current application scenario) and MAC _ speed (indicating the MAC current mode).

LOCAL _ CLK is a LOCAL clock used to generate the GMII/RGMII clock, typically 125 MHz. EXT _ CLK is the external input clock for the RMII clock, typically 50 MHz. DIVIDE0 is a first frequency divider that generates a corresponding clock frequency for the GMII/RGMII controller based on the operating mode indicated by mac _ speed (1000 MBps-125 MHz, 100 MBps-25 MHz, 10 MPbs-2.5 MHz). DIVIDE1 is a second frequency divider that generates TX _ CLK and RX _ CLK for the RMII controller based on the operating mode indicated by mac _ speed (100 MBps-25 MHz, 10 MPbs-2.5 MHz). REF _ CLK outputs 50 MHz.

The CLOCK _ PORT _ SEL is a CLOCK gating unit and is used for gating the output CLOCK of the CLOCK _ GEN according to the result of phy _ intf: when the PHY is the GMII interface, the CLOCK _ PORT _ SEL gates TX _ GMII _ CLK, namely the 1 interface; when the PHY is an MII interface, the CLOCK _ PORT _ SEL gates TX _ GMII _ CLK, namely the interface 1 gates; when the PHY is the RGMII interface, CLOCK _ PORT _ SEL gates TX _ GMII _ CLK and TX _ RGMII _ CLK, namely the gating of No. 1 and No. 2; when the PHY is an RMII interface, CLOCK _ PORT _ SEL gates TX _ GMII _ CLK and TX _ RMII _ CLK, i.e., PORT Nos. 1 and 3.

As an alternative embodiment, the MAC is directly connected to the PHY; and the MAC and the PHY transmit MDIO signals and MDC signals through a direct connection line between the MAC and the PHY.

Specifically, the MDIO interface is used for management control of the MAC and the PHY, and is used for reading and writing a control register and a status register of the PHY, and other protocols all have the interface, so as shown in fig. 3, the MAC and the PHY are directly connected, so that the MAC and the PHY transmit an MDIO signal and an MDC signal through a direct connection line between the MAC and the PHY, thereby simplifying line connection.

In conclusion, the core control logic is multiplexed to the greatest extent, code logic is reduced, hardware resources are reduced, and the area of a corresponding chip is reduced; meanwhile, a flexible clock generation module is designed, and clocks are not output to unnecessary submodules, so that the power consumption is greatly reduced.

The application also provides a MAC system, which comprises the MAC and any one multiplexing interface device.

For the introduction of the MAC system provided in the present application, please refer to the above-mentioned embodiment of the multiplexing interface device, which is not described herein again.

It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A multiplexing interface device, comprising:

2. The multiplexing interface device of claim 1 wherein the first interface controller is a GMII controller for an output GMII interface;

and the interface conversion module includes:

3. The multiplexing interface device of claim 2 wherein the GMII interface includes a GTX _ CLK signal representing a transmit clock generated by the clock generation module, a TX _ ER signal representing a transmit data error, a TX _ EN signal representing transmit enable, a TXD [7:0] signal representing transmit data, a RX _ CLK signal representing a receive clock generated by the PHY, a RX _ DV signal representing receive data valid, a RX _ ER signal representing a receive data error, a RXD [7:0] signal representing receive data, a CRS signal representing carrier sense, a COL signal representing collision sense, an MDIO signal representing management data, and an MDC signal representing a management data clock.

4. The multiplexing interface device of claim 3 wherein the RGMII interface comprises a GTX _ CLK signal, a TX _ CTL signal conveying both TX _ EN and TX _ ER signals, a TXD [3:0] signal representing transmitted data, a RX _ CLK signal, a RX _ CTL signal conveying both RX _ DV and RX _ ER signals, a RXD [3:0] signal representing received data, a CRS signal, a COL signal, a MDIO signal, a MDC signal; wherein the RGMII interface multiplexes the same signals as the GMII interface;

correspondingly, the RGMII conversion sub-module includes:

5. The multiplexing interface device of claim 4, wherein the MII interface comprises a TX _ CLK signal, a TX _ ER signal, a TX _ EN signal, a TXD [3:0] signal, a RX _ CLK signal, a RX _ DV signal, a RX _ ER signal, a RXD [3:0] signal, a CRS signal, a COL signal, a MDIO signal, a MDC signal representative of a transmit clock generated by the PHY; wherein the MII interface multiplexes the same signals as the GMII interface;

correspondingly, the MII conversion sub-module includes:

6. The multiplexing interface device of claim 5 wherein the MII conversion sub-module further comprises:

7. The multiplexing interface device of claim 5, wherein the RMII interface includes a REF _ CLK signal representing a reference clock generated by the clock generation module, a TX _ EN signal, a TXD [1:0] signal representing transmit data, a RX _ ER signal, a RXD [1:0] signal representing receive data, a CRS _ DV signal combined by a RX _ DV signal and a CRS signal, an MDIO signal, a MDC signal; the RMII interface multiplexes the same signals as the MII interface; the TX _ CLK signal and the RX _ CLK signal in the MII conversion sub-module are generated by the clock generation module instead;

correspondingly, the RMII conversion sub-module includes:

8. The multiplexing interface device of claim 7 wherein the clock generation module comprises:

9. The multiplexing interface device of claim 8 wherein the MAC is directly connected to the PHY; and the MAC and the PHY transmit MDIO signals and MDC signals through a direct connection line between the MAC and the PHY.

10. A MAC system comprising a MAC and a multiplexing interface device according to any one of claims 1 to 9.