CN112445415B

CN112445415B - Control method, control device, reading method, storage medium and processor

Info

Publication number: CN112445415B
Application number: CN201910819096.7A
Authority: CN
Inventors: 竹敏; 熊保玉; 何世坤
Original assignee: CETHIK Group Ltd; Hikstor Technology Co Ltd
Current assignee: CETHIK Group Ltd; Hikstor Technology Co Ltd
Priority date: 2019-08-30
Filing date: 2019-08-30
Publication date: 2022-11-08
Anticipated expiration: 2039-08-30
Also published as: WO2021037246A1; CN112445415A

Abstract

The application provides a control method, a control device, a reading method, a storage medium and a processor. The control method comprises the following steps: collecting the temperature of the environment where the storage unit is located; and obtaining a first relation, a second relation and a third relation, adjusting the resistance and/or the reference resistance of the first switch unit at least according to the collected temperature, the first relation, the second relation and the third relation to obtain a final high-resistance state resistance, a final low-resistance state resistance and a final reference resistance, wherein the difference value between the final reference resistance and the final low-resistance state resistance is a first preset difference value, and the difference value between the final reference resistance and the final high-resistance state resistance is a second preset difference value. Under the condition that the resistance and/or the reference resistance of the memory cell change along with the change of the environmental temperature, the difference value between the final reference resistance and the final high-resistance-state resistance is close to or equal to the difference value between the final reference resistance and the final low-resistance-state resistance, so that the lowest error rate of the reading result of the memory cell is ensured.

Description

Control method, control device, reading method, storage medium and processor

Technical Field

The present application relates to the field of memories, and in particular, to a control method, an apparatus, a reading method, a storage medium, and a processor.

Background

A Magnetic Tunnel Junction (MTJ) is a device based on the magnetic Tunnel Magnetoresistance (TMR) effect, which is mainly composed of two magnetic layers and a dielectric layer interposed between the magnetic layers. The first magnetic layer has a fixed magnetization orientation (also called a fixed layer), and the second magnetic layer has a magnetization orientation that can be changed by a magnetic field or a current (called a free layer), so that the two magnetic layers are in a parallel or antiparallel state, corresponding to a high resistance state and a low resistance state, respectively corresponding to data 0 or 1, and can be used for storing information.

Spin transfer torque MRAM (STT-MRAM), a memory that utilizes current to change the state of an MTJ, is a new memory with great potential. The memory has the advantages of simple circuit design, high read-write speed, infinite erasing and writing and the like, and has the greatest advantage of non-volatility (no loss of power-off data) compared with the traditional memory such as DRAM.

The memory state of the MRAM is mainly determined by comparing the resistance of the MTJ with a reference resistance, and in the case where the resistance of the MTJ is greater than the reference resistance, the memory state is determined to be 1, and in the case where the resistance of the MTJ is less than the reference resistance, the memory state is determined to be 0. However, in practice, when reading the state of the MRAM, a problem of inaccurate reading often occurs.

The above information disclosed in this background section is only for enhancement of understanding of the background of the technology described herein and, therefore, it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.

Disclosure of Invention

The present application is directed to a control method, an apparatus, a reading method, a storage medium, and a processor, so as to solve the problem in the prior art that inaccurate reading often occurs when reading the state of an MRAM.

In order to achieve the above object, according to one aspect of the present application, there is provided a control method for controlling reading of a memory cell, the memory cell including a memory bit cell and a first switching unit electrically connected to the memory bit cell, a reading circuit of the memory cell including a reference circuit, the reference circuit including a reference resistance, the control method including: collecting the temperature of the environment where the storage unit is located; acquiring a first relation, a second relation and a third relation, wherein the first relation is the relation between the low resistance state resistance and the temperature of the storage unit, the second relation is the relation between the high resistance state resistance and the temperature of the storage unit, and the third relation is the relation between the reference resistance and the temperature; and adjusting the resistance of the first switch unit and/or the reference resistance at least according to the acquired temperature, the first relation, the second relation and the third relation to obtain a final high-resistance state resistance, a final low-resistance state resistance and a final reference resistance, wherein the difference value between the final reference resistance and the final low-resistance state resistance is a first preset difference value, and the difference value between the final reference resistance and the final high-resistance state resistance is a second preset difference value.

Further, adjusting the resistance of the first switching unit and/or the reference resistance according to at least the collected temperature, the first relation, the second relation, and the third relation comprises: determining the low-resistance state resistance of the storage unit at the current temperature according to the acquired temperature and the first relation; determining the high-resistance state resistance of the storage unit at the current temperature according to the acquired temperature and the second relation; determining the reference resistance at the current temperature according to the acquired temperature and the third relation; and adjusting the resistance of the first switch unit and/or the reference resistance according to the high resistance state resistance at the current temperature, the low resistance state resistance at the current temperature and the reference resistance at the current temperature.

Further, adjusting the resistance of the first switch unit and/or the reference resistance according to the high resistance state resistance at the current temperature, the low resistance state resistance at the current temperature, and the reference resistance at the current temperature includes: acquiring a fourth relation and/or a fifth relation, wherein the fourth relation is the relation between the resistance of the first switch unit and the control voltage, the fifth relation is the relation between a second switch unit in a reference circuit and the control voltage, the reference resistance is the resistance of the reference circuit, and the reference circuit further comprises a resistance unit electrically connected with the second switch unit; adjusting the control voltage of the first switch unit according to the fourth relation among the high resistance state resistance at the current temperature, the low resistance state resistance at the current temperature, the reference resistance at the current temperature and/or adjusting the control voltage of the second switch unit according to the fifth relation among the high resistance state resistance at the current temperature, the low resistance state resistance at the current temperature, the reference resistance at the current temperature and the reference resistance at the current temperature.

Further, the step of adjusting the control voltage of the first switching unit according to the fourth relationship among the high resistance state resistance at the current temperature, the low resistance state resistance at the current temperature, the reference resistance at the current temperature, and the control voltage of the first switching unit is performed by using a first MOS transistor, and the control voltage of the first MOS transistor is a first gate voltage, includes: and adjusting the first gate voltage according to the fourth relation among the high resistance state resistance at the current temperature, the low resistance state resistance at the current temperature, the reference resistance at the current temperature and the fourth relation.

Further, the step of adjusting the control voltage of the second switching unit according to the fifth relationship among the high resistance state resistance at the current temperature, the low resistance state resistance at the current temperature, the reference resistance at the current temperature, and the control voltage of the second switching unit is performed by using a second MOS transistor as the second switching unit, and the step of: and adjusting the second gate voltage according to the fifth relation among the high resistance state resistance at the current temperature, the low resistance state resistance at the current temperature, the reference resistance at the current temperature and the voltage.

Further, a grid voltage controller is adopted to adjust the first grid voltage and/or the second grid voltage, and the grid voltage controller is an analog feedback control circuit or a grid voltage control chip.

According to an aspect of the present application, there is provided a method for reading a memory cell, the memory cell including a memory bit cell and a first switch cell electrically connected to the memory bit cell, the method including: collecting the temperature of the environment where the storage unit is located; acquiring a first relation, a second relation and a third relation, wherein the first relation is the relation between the low resistance state resistance and the temperature of the storage unit, the second relation is the relation between the high resistance state resistance and the temperature of the storage unit, and the third relation is the relation between the reference resistance and the temperature; adjusting the resistance and/or the reference resistance of the first switch unit at least according to the acquired temperature, the first relation, the second relation and the third relation to obtain a final high-resistance-state resistance, a final low-resistance-state resistance and a final reference resistance, wherein the difference value between the final reference resistance and the final low-resistance-state resistance is a first preset difference value, and the difference value between the final reference resistance and the final high-resistance-state resistance is a second preset difference value; acquiring the current resistance of the storage unit; comparing the current resistance of the storage unit with the final reference resistance to obtain a comparison result; and reading out the data stored in the storage unit according to the comparison result.

According to an aspect of the present application, there is provided a control apparatus for controlling reading of a memory cell including a memory bit cell and a first switch cell electrically connected to the memory bit cell, comprising: the acquisition unit is used for acquiring the temperature of the environment where the storage unit is located; the memory device comprises an acquisition unit, a comparison unit and a control unit, wherein the acquisition unit is used for acquiring a first relation, a second relation and a third relation, the first relation is the relation between the low resistance state resistance and the temperature of the memory unit, the second relation is the relation between the high resistance state resistance and the temperature of the memory unit, and the third relation is the relation between the reference resistance and the temperature; and the adjusting unit is used for adjusting the resistance and/or the reference resistance of the first switch unit at least according to the acquired temperature, the first relation, the second relation and the third relation to obtain a final high-resistance state resistance, a final low-resistance state resistance and a final reference resistance, wherein the difference value between the final reference resistance and the final high-resistance state resistance is a first preset difference value, and the difference value between the final reference resistance and the final low-resistance state resistance is a second preset difference value.

According to an aspect of the present application, there is provided a storage medium including a stored program, wherein the program executes any one of the control methods.

According to another aspect of the present application, there is provided a processor for executing a program, wherein the program executes any one of the control methods.

By applying the technical scheme of the application, the temperature of the environment where the storage unit is located is obtained firstly; then obtaining the relation (a first relation) between the low resistance state resistance and the temperature of the storage unit, the relation (a second relation) between the high resistance state resistance and the temperature of the storage unit and the relation (a third relation) between the reference resistance and the temperature; and finally, adjusting the low-resistance state resistance of the storage unit, the high-resistance state resistance of the storage unit and/or the reference resistance according to the temperature, the first relational expression, the second relational expression and the third relational expression, so that the difference value between the finally obtained final reference resistance and the final low-resistance state resistance is a first preset difference value, and the difference value between the final reference resistance and the final high-resistance state resistance is a second preset difference value. Therefore, under the condition that the resistance and/or the reference resistance of the memory cell change along with the change of the environmental temperature, the difference value between the final reference resistance and the final high-resistance-state resistance is close to or equal to the difference value between the final reference resistance and the final low-resistance-state resistance, and the lowest error rate of the reading result of the memory cell is ensured. The resistance and the reference resistance of the memory cell are adjusted in real time according to the ambient temperature, and the control of reading the memory cell is realized, so that the memory cell can be read in an optimal state in real time, the data reading speed is accelerated, and the error rate of data reading is reduced.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:

FIG. 1 is a diagram showing the relationship between the MTJ high resistance state (Rap) and the temperature and the relationship between the low resistance state resistance (Rp) and the temperature;

FIG. 2 is a graph showing the relationship between TMR and temperature;

FIG. 3 is a schematic showing the relationship between reference resistance and temperature prepared using doped Poly;

FIG. 4 is a schematic diagram showing the distribution of MRAM bit resistance and reference resistance in a normal temperature state;

FIG. 5 is a schematic diagram showing the distribution of Rp/Rap and poly resistance values of the MTJ without trimming at high temperature;

FIG. 6 is a flow chart of a control method of an embodiment of the present application;

FIG. 7 is a diagram illustrating a relationship between a MOS gate voltage and a channel resistance value according to an embodiment of the present invention;

FIG. 8 is a schematic diagram showing the distribution of the resistance of an MRAM bit cell read out after being adjusted by MOS resistance at high temperature;

FIG. 9 illustrates a schematic diagram of a control device for reading memory cells in accordance with an exemplary embodiment of the present application;

FIG. 10 is a schematic diagram of a reading apparatus for a memory cell according to an embodiment of the present application; and

FIG. 11 is a schematic diagram of another reading apparatus for a memory cell according to an embodiment of the present application.

Wherein the figures include the following reference numerals:

1. a storage unit; 2. a reference circuit.

Detailed Description

It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict. The present application will be described in detail below with reference to the embodiments with reference to the attached drawings.

In order to make the technical solutions of the present application better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments in the present application without making any creative effort shall fall within the protection scope of the present application.

It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the application described herein may be used. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.

Generally, the state of the memory cell is determined by comparing the resistance of the memory cell with a reference resistance, for example, the resistance of the memory cell is greater than the reference resistance, i.e., the memory cell is in a high resistance state, which may be represented by "1"; the resistance of the memory cell is less than the reference resistance, i.e., the memory cell is in a low resistance state, which can be represented by "0".

The inventor tests the resistance of the memory cell, and finds that the high resistance state resistance (Rap) of the MTJ is obviously reduced and the low resistance state resistance (Rp) of the MTJ is slightly changed along with the temperature rise, as shown in FIG. 1. As shown in fig. 2, TMR is significantly reduced, where the size relationship of TMR with Rap and Rp is: TMR = (R) _ap -R _p )/R _p . The difference between the high and low resistance states is expressed by Δ R, and with respect to the prior art, Δ R/2 must be greater than 6 δ of the MTJ resistance to ensure a read error rate of less than ppm. As shown in fig. 3, the reference resistor prepared by doping Poly has a positive temperature effect, and the resistance is increased as the temperature is higher. Such as

Fig. 4 is a schematic diagram showing distributions of MRAM bit resistance and reference resistance in a normal temperature state, where Δ R1 is a difference between a low resistance state resistance (Rp) and a reference resistance (Rref), and Δ R2 is a difference between a high resistance state resistance (Rap) and a reference resistance (Rref), as can be seen from fig. 4, in the conventional design, Δ R1 and Δ R2 are approximately equal to each other in the normal temperature state, and a memory cell has a better read window. Such as

FIG. 5 shows the resistance variation of Rp/Rap and the reference resistance of the MTJ at high temperature, where Δ R1 is the difference between the resistance in the low resistance state (Rp) and the reference resistance (Rref), and Δ R2 is the difference between the resistance in the high resistance state (Rap) and the reference resistance (Rref). As can be seen from fig. 4 and 5, under such a design method, the read window of the MRAM bit becomes smaller at high temperature, and the error rate of reading data state 1 is significantly increased.

As can be seen from the above, the resistance (low resistance state resistance and/or high resistance state resistance) of the memory cell changes with the change of the ambient temperature, and the reference resistance may also change with the change of the ambient temperature, so that if the same reference resistance is used to read the state of the memory cell at any temperature, the reading result is inevitably inaccurate.

In order to solve the technical problem as described above, according to an exemplary embodiment of the present application, a control method is provided.

Fig. 6 is a flowchart of a control method for controlling reading of a memory cell including a memory bit cell and a first switch cell electrically connected to the memory bit cell, the reading circuit of the memory cell including a reference circuit including a reference resistor, according to an embodiment of the present application. As shown in fig. 6, the method comprises the steps of:

step S101, collecting the temperature of the environment where the storage unit is located;

step S102, obtaining a first relation, a second relation and a third relation, wherein the first relation is a relation between the low resistance state resistance and the temperature of the memory unit, the second relation is a relation between the high resistance state resistance and the temperature of the memory unit, and the third relation is a relation between the reference resistance and the temperature;

step S103, adjusting the resistance of the first switch unit and/or the reference resistance at least according to the collected temperature, the first relationship, the second relationship, and the third relationship to obtain a final high resistance state resistance, a final low resistance state resistance, and a final reference resistance, where a difference between the final reference resistance and the final high resistance state resistance is a first predetermined difference, and a difference between the final reference resistance and the final high resistance state resistance is a second predetermined difference.

In the above scheme, the temperature of the environment where the storage unit is located is first obtained; then obtaining the relation (a first relation) between the low resistance state resistance and the temperature of the storage unit, the relation (a second relation) between the high resistance state resistance and the temperature of the storage unit and the relation (a third relation) between the reference resistance and the temperature; and finally, adjusting the low resistance state resistance of the storage unit, the high resistance state resistance of the storage unit and/or the reference resistance according to the temperature, the first relational expression, the second relational expression and the third relational expression so that the difference value between the finally obtained final reference resistance and the final low resistance state resistance is a first preset difference value, and the difference value between the final reference resistance and the final high resistance state resistance is a second preset difference value. Therefore, under the condition that the resistance and/or the reference resistance of the memory unit change along with the change of the environmental temperature, the difference value between the final reference resistance and the final high-resistance-state resistance and the difference value between the final reference resistance and the final low-resistance-state resistance are close to or equal to each other, namely the first preset difference value and the second preset difference value have different absolute values at different temperatures and have the same relative magnitude. Therefore, the highest accuracy of the reading result of the storage unit is ensured. The resistance and the reference resistance of the memory cell are adjusted in real time according to the ambient temperature, and the control of reading the memory cell is realized, so that the memory cell can be read in an optimal state in real time, the data reading speed is accelerated, and the error rate of data reading is reduced.

The above adjusting and/or including three conditions in the resistance and/or the reference resistance of the first switching unit: and adjusting the resistance and the reference resistance of the first switch unit, only adjusting the resistance of the first switch unit, and only adjusting the reference resistance. The difference value between the resistance of the first switch unit and the reference resistance is unchanged by adjusting the resistance of the first switch unit and the reference resistance, so that the control of reading the memory cell is realized; the difference value between the resistance of the first switch unit and the reference resistance is not changed by only adjusting the resistance of the first switch unit, so that the control of reading the memory unit is realized; by adjusting only the reference resistance, the difference between the resistance of the first switch unit and the reference resistance is not changed, thereby realizing the control of reading the memory cell.

It should be noted that the steps illustrated in the flowcharts of the figures may be performed in a computer system such as a set of computer-executable instructions and that, although a logical order is illustrated in the flowcharts, in some cases, the steps illustrated or described may be performed in an order different than presented herein.

According to an embodiment of the application, adjusting the resistance of the first switching unit and/or the reference resistance at least according to the collected temperature, the first relation, the second relation and the third relation comprises: determining the low resistance state resistance of the memory cell at the current temperature according to the collected temperature and the first relation; determining the high-resistance state resistance of the memory cell at the current temperature according to the acquired temperature and the second relation; determining the reference resistance at the current temperature according to the acquired temperature and the third relation; and adjusting the resistance of the first switch unit and/or the reference resistance according to the high resistance state resistance at the current temperature, the low resistance state resistance at the current temperature and the reference resistance at the current temperature. In this way, the resistance of the first switching unit and/or the reference resistance can be adjusted more accurately, thereby realizing more accurate reading of the memory cell.

In order to precisely adjust the resistance and/or the reference resistance of the memory cell, according to an embodiment of the present application, the adjusting the resistance and/or the reference resistance of the first switching unit according to the high resistance state resistance at the current temperature, the low resistance state resistance at the current temperature, and the reference resistance at the current temperature includes: acquiring a fourth relation and/or a fifth relation, wherein the fourth relation is a relation between the resistance of the first switch unit and a control voltage, the fifth relation is a relation between a second switch unit in a reference circuit and a control voltage, the reference resistance is the resistance of the reference circuit, and the reference circuit further comprises a resistance unit electrically connected with the second switch unit; adjusting a control voltage of the first switch unit according to the fourth relationship, and/or adjusting a control voltage of the second switch unit according to the high resistance state resistance at the current temperature, the low resistance state resistance at the current temperature, the reference resistance at the current temperature, and the fifth relationship. In this embodiment, the control of the resistance and/or the reference resistance of the memory cell can be achieved by adjusting the control voltage of the at least one switching unit, and thus the reading of the memory cell can be accurately controlled.

The structure of the reference circuit may be any structure including the second switch unit and the resistance unit, and specifically may be a series connection of the second switch unit and the resistance unit, a parallel connection of the second switch unit and the resistance unit, or a mixed connection of the second switch unit and the resistance unit. The skilled person can select a suitable connection method according to the actual situation.

The first switch unit and the second switch unit of the present application may be any device or circuit structure whose resistance may vary with the control voltage, and those skilled in the art may select a suitable device or circuit as the first switch unit or the second switch unit according to actual situations. For example, the first switching unit and the second switching unit may also be BJTs or transmission gates, etc.

In order to simplify the structure of the memory cell, the first switching unit is a first MOS transistor, the control voltage of the first MOS transistor is a first gate voltage, and the control voltage of the first switching unit is adjusted according to the fourth relationship among the high resistance state resistance at the current temperature, the low resistance state resistance at the current temperature, the reference resistance at the current temperature, and the method includes: and adjusting the first gate voltage according to the fourth relationship among the high resistance state resistance at the current temperature, the low resistance state resistance at the current temperature, the reference resistance at the current temperature and the fourth relationship.

In order to simplify the structure of the reference circuit, the second switching unit is a second MOS transistor, the control voltage of the second MOS transistor is a second gate voltage, and the control voltage of the second switching unit is adjusted according to the fifth relationship among the high resistance at the current temperature, the low resistance at the current temperature, the reference resistance at the current temperature, and the fifth relationship, and the method includes: and adjusting the second gate voltage according to the fifth relationship among the high resistance state resistance at the current temperature, the low resistance state resistance at the current temperature, the reference resistance at the current temperature, and the voltage.

In a more simplified structure, the second MOS transistor of the reference circuit is connected in series with a reference resistor.

According to an embodiment of the present application, the first gate voltage and/or the second gate voltage is adjusted by using a gate voltage controller, and the gate voltage controller is an analog feedback control circuit or a gate voltage control chip. The gate voltage controller is used for adjusting the first gate voltage and/or the second gate voltage, and the method comprises three conditions: adjusting only the first gate voltage; adjusting only the second gate voltage; the first gate voltage and the second gate voltage are adjusted simultaneously. The resistance of the memory cell is adjusted by adjusting the first gate voltage, and the resistance of the reference circuit is adjusted by adjusting the second gate voltage.

The first gate voltage and the second gate voltage can be adjusted by a gate voltage controller, the gate voltage controller can be, but is not limited to, an analog feedback control circuit or a gate voltage control chip, and a person skilled in the art can select an appropriate kind of gate voltage controller according to actual situations. The gate voltage is adjusted through the gate voltage adjuster, so that the corresponding resistance is adjusted, the compensation of the corresponding resistance can be realized without introducing circuits and devices of other compensation resistors, the purpose of simplifying the circuit is achieved, and meanwhile, the adjustment of the corresponding resistance is realized by changing the gate voltage, so that the compensation is more accurate and flexible.

In a specific embodiment, the memory cell is an MRAM, and as shown in fig. 7, a wide range of channel resistance variation resistance values can be obtained by adjusting the MOS gate voltage within the MOS operating voltage range. Fig. 8 shows the distribution of the MRAM bit resistance read out after the MOS resistance adjustment at high temperature, and it can be obtained that the read window of the MRAM resistance becomes larger after the MOS voltage adjustment at high temperature.

In the embodiment, the MOS gate voltage in the control reference circuit can be increased by adjusting the MOS gate voltage under the working window of the MOS, so that the whole reference resistor moves to a smaller resistor end, the total reference resistance value is always in the middle state of the high-low resistance state resistance value of the MTJ, and the chip reading window is always in the optimal state. The adjustment of the reference resistance includes the following two cases: 1. when the reference resistor has a positive temperature coefficient, the MOS gate voltage of the control reference resistor is increased along with the rise of the environmental temperature, so that the resistance of the control MOS transistor is reduced, and the total reference resistor moves to a smaller resistance end; 2. when the reference resistor has a negative temperature coefficient, as the ambient temperature rises, the MOS gate voltage controlling the reference resistor is increased or decreased according to the magnitude of the negative temperature coefficient, so that the reference resistor moves to a smaller or larger resistor end, specifically, the increase or decrease is determined according to the change of the resistance of the memory cell and the change of the reference resistor.

The MOS gate voltage can be adjusted under the working window of the MOS to control the MOS gate voltage in the storage unit to enable the total resistance of the storage unit to move to a larger end, so that the average difference value between the parallel resistance and the anti-parallel resistance of the MTJ and the reference resistance is smaller than the resistance value of each resistance distribution, and the reading window of the chip is always in the optimal state. The adjustment of the total resistance of the memory cell includes two cases: 1. when the high resistance state of the memory cell has a positive temperature coefficient: as the ambient temperature rises, the MOS gate voltage in the memory cell is increased to make the total resistance of the low resistance state bit element move to the low resistance end, and the total resistance of the high resistance state moves to the high resistance state. Thereby enlarging the read window; 2. when the high resistance state of the memory cell has a negative temperature coefficient: with the rise of the environmental temperature, according to the magnitude of the negative temperature coefficient, the MOS gate voltage in the storage unit is reduced, so that the total resistance in the high resistance state and the total resistance in the low resistance state of the storage unit are symmetrically distributed on two sides of the reference resistance. .

In order to further ensure the accuracy of the reading result, in an embodiment of the present application, the storage bit is an MTJ, the first switch unit and the second switch unit are both MOS transistors, the first switch unit is connected in series with the MTJ, and the second switch unit is connected in series with the reference resistor. In a specific embodiment, the gate voltage of the first switch is adjusted so that the resistance variation value of the first MOS transistor, the reference resistance variation value, and the MTJ high resistance state resistance variation value satisfy the following relation:

dRmos(V)＝dRref(T)-1/2×dRmtj(T)

wherein dRmos (V) is the variation value of the first MOS transistor resistance with the grid voltage, dRref (T) is the variation value of the reference resistance with the temperature, and dRmtj (T) is the variation value of the MTJ high resistance state resistance with the temperature.

In another specific embodiment, the gate voltage of the second switch is adjusted so that the resistance variation value of the second MOS transistor, the reference resistance variation value, and the MTJ high resistance state resistance variation value satisfy the following relation:

dRmos(V)＝1/2×dRmtj(T)-dRref(T)

wherein dRmos (V) is the variation value of the resistance of the second MOS tube along with the grid voltage, dRref (T) is the variation value of the reference resistance along with the temperature, and dRmtj (T) is the variation value of the high resistance state resistance of the MTJ along with the temperature.

According to another exemplary embodiment of the present application, a method for reading a memory cell, the memory cell including a memory bit cell and a first switch cell electrically connected to the memory bit cell, includes: collecting the temperature of the environment where the storage unit is located; acquiring a first relation, a second relation and a third relation, wherein the first relation is the relation between the low resistance state resistance and the temperature of the memory unit, the second relation is the relation between the high resistance state resistance and the temperature of the memory unit, and the third relation is the relation between the reference resistance and the temperature; adjusting the resistance and/or the reference resistance of the first switch unit at least according to the acquired temperature, the first relation, the second relation and the third relation to obtain a final high-resistance-state resistance, a final low-resistance-state resistance and a final reference resistance, wherein the difference value between the final reference resistance and the final low-resistance-state resistance is a first preset difference value, and the difference value between the final reference resistance and the final high-resistance-state resistance is a second preset difference value; acquiring the current resistance of the memory cell; comparing the current resistance of the memory cell with the final reference resistance to obtain a comparison result; and reading out the data stored in the memory cell according to the comparison result.

In the above scheme, the resistance and/or the reference resistance of the memory cell is adjusted by the control method, then the current resistance value of the memory cell is obtained, then the comparison result is obtained by comparing the current resistance and the final reference resistance of the memory cell, and then the data accessed by the memory cell is read according to the comparison result, so that the real-time reading of the memory data of the memory cell is realized. The reading method enables the reading window to be in the optimal state in real time, thereby reducing the error rate of data reading and ensuring the accuracy of the reading result.

According to an embodiment of the application, adjusting the resistance of the first switching unit and/or the reference resistance at least according to the collected temperature, the first relation, the second relation and the third relation comprises: determining the low resistance state resistance of the memory cell at the current temperature according to the collected temperature and the first relation; determining the high-resistance state resistance of the memory cell at the current temperature according to the collected temperature and the second relation; determining the reference resistance at the current temperature according to the acquired temperature and the third relation; and adjusting the resistance of the first switch unit and/or the reference resistance according to the high resistance state resistance at the current temperature, the low resistance state resistance at the current temperature and the reference resistance at the current temperature. In this way, the resistance of the first switching unit and/or the reference resistance can be adjusted more accurately, thereby realizing more accurate reading of the memory cell.

The structure of the reference circuit may be any structure including a second switch unit and a resistance unit, and specifically may be a series connection of the second switch unit and the resistance unit, a parallel connection of the second switch unit and the resistance unit, or a mixed connection of the second switch unit and the resistance unit. The skilled person can select a suitable connection method according to the actual situation.

In order to simplify the structure of the reference circuit, the second switching unit is a second MOS transistor, the control voltage of the second MOS transistor is a second gate voltage, and the control voltage of the second switching unit is adjusted according to the fifth relationship among the high resistance state resistance at the current temperature, the low resistance state resistance at the current temperature, the reference resistance at the current temperature, and the method includes: and adjusting the second gate voltage according to the fifth relationship among the high resistance state resistance at the current temperature, the low resistance state resistance at the current temperature, the reference resistance at the current temperature, and the voltage.

In a more simplified structure, the second MOS transistor and a resistor in the reference circuit are connected in series.

It should be noted that the control device for reading a memory cell according to the embodiment of the present application may be used to execute the control method for reading a memory cell according to the embodiment of the present application. A control device for reading a memory cell according to an embodiment of the present application is described below.

The memory cell includes a memory bit cell and a first switch cell electrically connected to the memory bit cell, as shown in fig. 9, the apparatus includes:

the acquisition unit 10 is used for acquiring the temperature of the environment where the storage unit is located;

a first obtaining unit 20, configured to obtain a first relationship, a second relationship, and a third relationship, where the first relationship is a relationship between a low resistance of the memory cell and a temperature, the second relationship is a relationship between a high resistance of the memory cell and a temperature, and the third relationship is a relationship between a reference resistance and a temperature;

an adjusting unit 30, configured to adjust the resistance and/or the reference resistance of the first switch unit at least according to the collected temperature, the first relationship, the second relationship, and the third relationship, so as to obtain a final high-resistance state resistance, a final low-resistance state resistance, and a final reference resistance, where a difference between the final reference resistance and the final high-resistance state resistance is a first predetermined difference, and a difference between the final reference resistance and the final low-resistance state resistance is a second predetermined difference.

In the scheme, the acquisition unit acquires the temperature of the environment where the storage unit is located; the first obtaining unit obtains a relation (a first relation) between the low resistance state resistance and the temperature of the storage unit, a relation (a second relation) between the high resistance state resistance and the temperature of the storage unit and a relation (a third relation) between the reference resistance and the temperature; the adjusting unit adjusts the low-resistance state resistance of the storage unit, the high-resistance state resistance of the storage unit and/or the reference resistance according to the temperature, the first relation, the second relation and the third relation, so that the difference value between the finally obtained final reference resistance and the final low-resistance state resistance is a first preset difference value, and the difference value between the final reference resistance and the final high-resistance state resistance is a second preset difference value. Therefore, under the condition that the resistance and/or the reference resistance of the memory cell change along with the change of the environmental temperature, the difference value between the final reference resistance and the final high-resistance-state resistance is close to or equal to the difference value between the final reference resistance and the final low-resistance-state resistance, and the result of reading the memory cell is accurate. The resistance and the reference resistance of the memory cell are adjusted in real time according to the ambient temperature, and the control of reading the memory cell is realized, so that the memory cell can be read in an optimal state in real time, the data reading speed is accelerated, and the error rate of data reading is reduced.

The adjusting unit adjusts and/or includes three conditions in the resistance and/or the reference resistance of the first switching unit: and adjusting the resistance and the reference resistance of the first switch unit, only adjusting the resistance of the first switch unit, and only adjusting the reference resistance. The difference value between the resistance of the first switch unit and the reference resistance is unchanged by adjusting the resistance of the first switch unit and the reference resistance, so that the control of reading the memory cell is realized; the difference value between the resistance of the first switch unit and the reference resistance is not changed by only adjusting the resistance of the first switch unit, so that the control of reading the memory unit is realized; by adjusting only the reference resistance, the difference between the resistance of the first switch unit and the reference resistance is not changed, thereby realizing the control of reading the memory cell.

According to an embodiment of the application, the adjustment unit includes a first determination module, a second determination module, a third determination module, and an adjustment module. The first determining module is used for determining the low resistance state resistance of the memory unit at the current temperature according to the acquired temperature and the first relation; the second determining module is used for determining the high-resistance state resistance of the storage unit at the current temperature according to the acquired temperature and the second relation; the third determining module is used for determining the reference resistance at the current temperature according to the acquired temperature and the third relation; the adjusting module is used for adjusting the resistance of the first switch unit and/or the reference resistance according to the high resistance state resistance at the current temperature, the low resistance state resistance at the current temperature and the reference resistance at the current temperature. In this way, the resistance of the first switch unit and/or the reference resistance can be adjusted more accurately, thereby realizing more accurate reading of the memory cell.

In order to precisely adjust the resistance of the memory cell and/or the reference resistance, according to an embodiment of the present application, the adjusting module includes an obtaining submodule and an adjusting submodule, wherein the obtaining submodule is configured to obtain a fourth relationship and/or a fifth relationship, the fourth relationship is a relationship between the resistance of the first switching unit and a control voltage, the fifth relationship is a relationship between a second switching unit in a reference circuit and a control voltage, the reference resistance is the resistance of the reference circuit, and the reference circuit further includes a resistance unit electrically connected to the second switching unit; the adjusting submodule is configured to adjust a control voltage of the first switch unit according to the high resistance state resistance at the current temperature, the low resistance state resistance at the current temperature, the reference resistance at the current temperature, and the fourth relationship, and/or adjust a control voltage of the second switch unit according to the high resistance state resistance at the current temperature, the low resistance state resistance at the current temperature, the reference resistance at the current temperature, and the fifth relationship. In this embodiment, the control of the resistance and/or the reference resistance of the memory cell can be achieved by adjusting the control voltage of the at least one switching unit, and thus the reading of the memory cell can be accurately controlled.

In order to simplify the structure of the memory cell, the first switch unit is a first MOS transistor, the control voltage of the first MOS transistor is a first gate voltage, and the adjustment submodule includes a first adjustment submodule configured to adjust the first gate voltage according to the fourth relationship among the high resistance state resistance at the current temperature, the low resistance state resistance at the current temperature, the reference resistance at the current temperature, and the reference resistance at the current temperature.

In order to simplify the structure of the reference circuit, the second switching unit is a second MOS transistor, the control voltage of the second MOS transistor is a second gate voltage, and the adjustment submodule further includes a second adjustment submodule configured to adjust the second gate voltage according to the fifth relationship among the high resistance state resistance at the current temperature, the low resistance state resistance at the current temperature, the reference resistance at the current temperature, and the reference resistance at the current temperature.

According to an embodiment of the application, the adjusting submodule is a gate voltage controller, and the first gate voltage and/or the second gate voltage are adjusted by the gate voltage controller, and the gate voltage controller is an analog feedback control circuit or a gate voltage control chip. The gate voltage controller is used for adjusting the first gate voltage and/or the second gate voltage, and the method comprises the following three conditions: adjusting only the first gate voltage; adjusting only the second gate voltage; the first gate voltage and the second gate voltage are adjusted simultaneously. The resistance of the memory cell is adjusted by adjusting the first gate voltage, and the resistance of the reference circuit is adjusted by adjusting the second gate voltage.

The first gate voltage and the second gate voltage can be adjusted by a gate voltage controller, the gate voltage controller can be, but is not limited to, an analog feedback control circuit or a gate voltage control chip, and a person skilled in the art can select an appropriate kind of gate voltage controller according to actual situations. The grid voltage is adjusted through the grid voltage adjuster, so that the corresponding resistance is adjusted, the compensation of the corresponding resistance can be realized without introducing circuits and devices of other compensation resistors, the purpose of simplifying the circuit is achieved, and meanwhile, the adjustment of the corresponding resistance is realized by changing the grid voltage, so that the compensation is more accurate and flexible.

According to another exemplary embodiment of the present application, there is provided a reading apparatus of a memory cell, the memory cell including a memory bit cell and a first switching unit electrically connected to the memory bit cell, the reading apparatus including:

the acquisition unit is used for acquiring the temperature of the environment where the storage unit is located;

a first obtaining unit configured to obtain a first relationship, a second relationship, and a third relationship, where the first relationship is a relationship between a low resistance of the memory cell and a temperature, the second relationship is a relationship between a high resistance of the memory cell and a temperature, and the third relationship is a relationship between a reference resistance and a temperature;

and the adjusting unit is used for adjusting the resistance and/or the reference resistance of the first switch unit at least according to the acquired temperature, the first relation, the second relation and the third relation to obtain a final high-resistance-state resistance, a final low-resistance-state resistance and a final reference resistance, wherein the difference value between the final reference resistance and the final high-resistance-state resistance is a first preset difference value, and the difference value between the final reference resistance and the final low-resistance-state resistance is a second preset difference value.

The second acquisition unit is used for acquiring the current resistance of the storage unit;

a comparison unit for comparing the current resistance of the memory unit with the final reference resistance to obtain a comparison result;

and a reading unit for reading out the data stored in the storage unit according to the comparison result.

In the scheme, the acquisition unit acquires the temperature of the environment where the storage unit is located; the first obtaining unit obtains a relation (a first relation) between the low resistance state resistance and the temperature of the storage unit, a relation (a second relation) between the high resistance state resistance and the temperature of the storage unit and a relation (a third relation) between the reference resistance and the temperature; the adjusting unit adjusts the low resistance state resistance of the storage unit and the high resistance state resistance and/or the reference resistance of the storage unit according to the temperature, the first relational expression, the second relational expression and the third relational expression, so that the difference value between the finally obtained final reference resistance and the final low resistance state resistance is a first preset difference value, and the difference value between the final reference resistance and the final high resistance state resistance is a second preset difference value. A comparison unit for comparing the current resistance of the memory unit with the final reference resistance to obtain a comparison result; and a reading unit for reading out the data stored in the storage unit according to the comparison result. Therefore, under the condition that the resistance of the memory cell and/or the reference resistance changes along with the change of the environmental temperature, the difference value between the final reference resistance and the final high-resistance-state resistance is kept unchanged, and the difference value between the final reference resistance and the final low-resistance-state resistance is kept unchanged, so that the result of reading the memory cell is accurate. The resistance and the reference resistance of the memory cell are adjusted in real time according to the ambient temperature, and the control of reading the memory cell is realized, so that the memory cell can be read in an optimal state in real time, the data reading speed is accelerated, and the error rate of data reading is reduced.

The adjusting unit adjusts and/or includes three conditions in the resistance and/or the reference resistance of the first switching unit: and adjusting the resistance and the reference resistance of the first switch unit, only adjusting the resistance of the first switch unit, and only adjusting the reference resistance. The difference value between the resistance of the first switch unit and the reference resistance is unchanged by adjusting the resistance of the first switch unit and the reference resistance, so that the control of reading the memory cell is realized; the difference value between the resistance of the first switch unit and the reference resistance is not changed by only adjusting the resistance of the first switch unit, so that the control of reading the memory cell is realized; by adjusting only the reference resistance, the difference between the resistance of the first switch unit and the reference resistance is not changed, thereby realizing the control of reading the memory cell.

According to an embodiment of the application, the adjustment unit includes a first determination module, a second determination module, a third determination module, and an adjustment module. The first determining module is used for determining the low-resistance-state resistance of the storage unit at the current temperature according to the acquired temperature and the first relation; the second determining module is used for determining the high-resistance state resistance of the storage unit at the current temperature according to the acquired temperature and the second relation; the third determining module is used for determining the reference resistance at the current temperature according to the acquired temperature and the third relation; the adjusting module is used for adjusting the resistance of the first switch unit and/or the reference resistance according to the high resistance state resistance at the current temperature, the low resistance state resistance at the current temperature and the reference resistance at the current temperature. In this way, the resistance of the first switching unit and/or the reference resistance can be adjusted more accurately, thereby realizing more accurate reading of the memory cell.

In order to accurately adjust the resistance of the memory cell and/or the reference resistance, according to an embodiment of the present application, the adjusting module includes an obtaining submodule and an adjusting submodule, where the obtaining submodule is configured to obtain a fourth relationship and/or a fifth relationship, where the fourth relationship is a relationship between the resistance of the first switch unit and a control voltage, the fifth relationship is a relationship between a second switch unit in a reference circuit and a control voltage, the reference resistance is the resistance of the reference circuit, and the reference circuit further includes a resistance unit electrically connected to the second switch unit; the adjusting submodule is configured to adjust a control voltage of the first switch unit according to the high resistance state resistance at the current temperature, the low resistance state resistance at the current temperature, the reference resistance at the current temperature, and the fourth relationship, and/or adjust a control voltage of the second switch unit according to the high resistance state resistance at the current temperature, the low resistance state resistance at the current temperature, the reference resistance at the current temperature, and the fifth relationship. In this embodiment, the control of the resistance of the memory cell and/or the reference resistance can be realized by adjusting the control voltage of the at least one switching unit, and thus the reading of the memory cell can be accurately controlled.

In a more simplified structure, the reference circuit comprises a second MOS transistor and a resistor, which are connected in series.

According to an embodiment of the application, the adjusting submodule is a gate voltage controller, and the first gate voltage and/or the second gate voltage are adjusted by the gate voltage controller, and the gate voltage controller is an analog feedback control circuit or a gate voltage control chip. The gate voltage controller is used for adjusting the first gate voltage and/or the second gate voltage, and the method comprises three conditions: adjusting only the first gate voltage; adjusting only the second gate voltage; the first gate voltage and the second gate voltage are adjusted simultaneously. The resistance of the memory cell is adjusted by adjusting the first gate voltage, and the resistance of the reference circuit is adjusted by adjusting the second gate voltage.

The control device for reading the storage unit comprises a processor and a memory, wherein the acquisition unit, the first acquisition unit, the adjustment unit and the like are stored in the memory as program units, and the processor executes the program units stored in the memory to realize corresponding functions.

The processor comprises a kernel, and the kernel calls the corresponding program unit from the memory. The kernel can be set to be one or more, and the control of reading the storage unit is realized by adjusting the kernel parameters.

The memory may include volatile memory in a computer readable medium, random Access Memory (RAM) and/or nonvolatile memory such as Read Only Memory (ROM) or flash memory (flash RAM), and the memory includes at least one memory chip.

An embodiment of the present invention provides a storage medium on which a program is stored, the program implementing the above-described control method for reading a storage unit when executed by a processor.

The embodiment of the invention provides a processor, which is used for running a program, wherein the control method for reading a storage unit is executed when the program runs.

An embodiment of the present invention provides an apparatus, where the apparatus includes a processor, a memory, and a program that is stored in the memory and is executable on the processor, and when the processor executes the program, at least the following steps are implemented:

step S102, obtaining a first relation, a second relation and a third relation, wherein the first relation is the relation between the low resistance state resistance and the temperature of the memory unit, the second relation is the relation between the high resistance state resistance and the temperature of the memory unit, and the third relation is the relation between the reference resistance and the temperature;

step S103, adjusting the resistance and/or the reference resistance of the first switch unit at least according to the collected temperature, the first relation, the second relation, and the third relation, to obtain a final high resistance state resistance, a final low resistance state resistance, and a final reference resistance, where a difference between the final reference resistance and the final high resistance state resistance is a first predetermined difference, and a difference between the final reference resistance and the final high resistance state resistance is a second predetermined difference.

The device herein may be a server, a PC, a PAD, a mobile phone, etc.

The present application further provides a computer program product adapted to perform a program of initializing at least the following method steps when executed on a data processing device:

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

In a typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.

The memory may include forms of volatile memory in a computer readable medium, random Access Memory (RAM) and/or non-volatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). The memory is an example of a computer-readable medium.

Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.

In order to make the technical solutions of the present application more clearly understood by those skilled in the art, the following description will be given with reference to specific embodiments.

Example 1

The specific reading apparatus for the memory cell is shown in fig. 10, wherein the memory bit in the memory cell 1 is an MTJ, the first switching unit is a first MOS transistor connected in series with the MTJ, and the reference circuit 2 includes a resistor and a second MOS transistor (second switching unit) connected in series. The reading circuit comprises an acquisition unit 10, a first acquisition unit 20, an adjustment unit 30, a second acquisition unit (not marked in the figure), a comparison unit 50 and a reading unit 60, wherein the acquisition unit 10 is a temperature sensor, the comparison unit 50 is a differential amplification circuit, and the adjustment unit 30 is a temperature feedback circuit. The adjusting unit 30 is electrically connected to the gate of the second MOS transistor in the reference circuit 2.

The reading process of the reading device comprises the following steps:

acquiring the temperature of the environment where the storage unit is located by using a temperature sensor;

acquiring a first relation, a second relation and a third relation, wherein the first relation is the relation between the low resistance state resistance and the temperature of the memory unit, the second relation is the relation between the high resistance state resistance and the temperature of the memory unit, and the third relation is the relation between the reference resistance and the temperature;

adjusting the resistance of the first switch unit at least according to the acquired temperature, the first relation, the second relation and the third relation to obtain a final high-resistance state resistance, a final low-resistance state resistance and a final reference resistance, wherein a difference value between the final reference resistance and the final high-resistance state resistance is a first preset difference value, and a difference value between the final reference resistance and the final low-resistance state resistance is a second preset difference value;

acquiring the current resistance of the memory cell;

comparing the current resistance of the memory unit with the final reference resistance to obtain a comparison result;

and reading out the data stored in the memory cell according to the comparison result.

Example 2

The present embodiment is different from the embodiments in that: as shown in fig. 11, the adjusting unit 30 is electrically connected to the gate of the first MOS transistor in the memory unit 1.

And in the specific reading process, the resistance of the memory cell is adjusted, and the technical effect is the same as that of embodiment 1.

Example 3

In practical operation, adjusting the gate voltage of the second switch is easier to achieve, and as shown in fig. 10, the adjusting unit 30 is electrically connected to the gate of the second MOS transistor in the reference circuit 2. By adjusting the gate voltage of the second switch, the resistance change value of the second MOS transistor, the reference resistance change value and the MTJ high resistance state resistance change value satisfy the following relational expression:

dRmos(V)＝1/2×dRmtj(T)-dRref(T)

wherein dRmos (V) is the variation value of the resistance of the second MOS transistor along with the gate voltage, dRref (T) is the variation value of the reference resistance along with the temperature, and dRmtj (T) is the variation value of the high-resistance-state resistance of the MTJ along with the temperature.

From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:

1) In the control method, the temperature of the environment where the storage unit is located is obtained; then obtaining the relation (a first relation) between the low resistance state resistance and the temperature of the storage unit, the relation (a second relation) between the high resistance state resistance and the temperature of the storage unit and the relation (a third relation) between the reference resistance and the temperature; and finally, adjusting the low-resistance state resistance of the storage unit, the high-resistance state resistance of the storage unit and/or the reference resistance according to the temperature, the first relational expression, the second relational expression and the third relational expression, so that the difference value between the finally obtained final reference resistance and the final low-resistance state resistance is a first preset difference value, and the difference value between the final reference resistance and the final high-resistance state resistance is a second preset difference value. Therefore, under the condition that the resistance and/or the reference resistance of the memory cell change along with the change of the environmental temperature, the difference value between the final reference resistance and the final high-resistance-state resistance is close to or equal to the difference value between the final reference resistance and the final low-resistance-state resistance, and the result of reading the memory cell is accurate. The resistance and the reference resistance of the memory cell are adjusted in real time according to the ambient temperature, and the control of reading the memory cell is realized, so that the memory cell can be read in an optimal state in real time, the data reading speed is accelerated, and the error rate of data reading is reduced.

2) In the reading method, the resistance and/or the reference resistance of the storage unit are/is adjusted through the control method, then the current resistance value of the storage unit is obtained, then the current resistance and the final reference resistance of the storage unit are compared to obtain a comparison result, and data accessed by the storage unit is read according to the comparison result, so that the storage data of the storage unit can be read in real time. The reading method enables the reading window to be in the optimal state in real time, thereby reducing the error rate of data reading and ensuring the accuracy of the reading result.

3) In the control device, the acquisition unit acquires the temperature of the environment where the storage unit is located; the first obtaining unit obtains a relation (a first relation) between the low resistance state resistance and the temperature of the storage unit, a relation (a second relation) between the high resistance state resistance and the temperature of the storage unit and a relation (a third relation) between the reference resistance and the temperature; the adjusting unit adjusts the low-resistance state resistance of the storage unit, the high-resistance state resistance of the storage unit and/or the reference resistance according to the temperature, the first relation, the second relation and the third relation, so that the difference value between the finally obtained final reference resistance and the final low-resistance state resistance is a first preset difference value, and the difference value between the final reference resistance and the final high-resistance state resistance is a second preset difference value. Therefore, under the condition that the resistance and/or the reference resistance of the memory cell change along with the change of the environmental temperature, the difference value between the final reference resistance and the final high-resistance-state resistance is close to or equal to the difference value between the final reference resistance and the final low-resistance-state resistance, and the result of reading the memory cell is accurate. The resistance and the reference resistance of the memory cell are adjusted in real time according to the ambient temperature, and the control of reading the memory cell is realized, so that the memory cell can be read in an optimal state in real time, the data reading speed is accelerated, and the error rate of data reading is reduced.

4) In the reading device, the acquisition unit acquires the temperature of the environment where the storage unit is located; the first obtaining unit obtains a relation (a first relation) between the low resistance state resistance and the temperature of the storage unit, a relation (a second relation) between the high resistance state resistance and the temperature of the storage unit and a relation (a third relation) between the reference resistance and the temperature; the adjusting unit adjusts the low-resistance state resistance of the storage unit, the high-resistance state resistance of the storage unit and/or the reference resistance according to the temperature, the first relation, the second relation and the third relation, so that the difference value between the finally obtained final reference resistance and the final low-resistance state resistance is a first preset difference value, and the difference value between the final reference resistance and the final high-resistance state resistance is a second preset difference value. A comparison unit for comparing the current resistance of the memory unit with the final reference resistance to obtain a comparison result; and a reading unit for reading out the data stored in the storage unit according to the comparison result. Therefore, under the condition that the resistance and/or the reference resistance of the memory cell change along with the change of the environmental temperature, the difference value between the final reference resistance and the final high-resistance-state resistance is close to or equal to the difference value between the final reference resistance and the final low-resistance-state resistance, and the result of reading the memory cell is accurate. The resistance and the reference resistance of the memory cell are adjusted in real time according to the ambient temperature, and the control of reading the memory cell is realized, so that the memory cell can be read in an optimal state in real time, the data reading speed is accelerated, and the error rate of data reading is reduced.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A control method for controlling reading of a memory cell, the memory cell including a memory bit cell and a first switch cell electrically connected to the memory bit cell, a reading circuit of the memory cell including a reference circuit, the reference circuit including a reference resistor, the method comprising:

collecting the temperature of the environment where the storage unit is located;

adjusting the resistance of the first switch unit and/or the reference resistance at least according to the acquired temperature, the first relation, the second relation and the third relation to obtain a final high-resistance state resistance, a final low-resistance state resistance and a final reference resistance, wherein a difference value between the final reference resistance and the final low-resistance state resistance is a first preset difference value, and a difference value between the final reference resistance and the final high-resistance state resistance is a second preset difference value;

adjusting the resistance and/or the reference resistance of the first switching unit according to at least the collected temperature, the first relation, the second relation, and the third relation, including:

determining the low-resistance state resistance of the storage unit at the current temperature according to the acquired temperature and the first relation;

determining the high-resistance state resistance of the storage unit at the current temperature according to the acquired temperature and the second relation;

determining the reference resistance at the current temperature according to the acquired temperature and the third relation;

adjusting the resistance of the first switch unit and/or the reference resistance according to the high resistance state resistance at the current temperature, the low resistance state resistance at the current temperature and the reference resistance at the current temperature;

under the condition that the resistance and/or the reference resistance of the memory unit change along with the change of the environmental temperature, the difference value between the final reference resistance and the final high-resistance-state resistance is close to or equal to the difference value between the final reference resistance and the final low-resistance-state resistance, namely the first preset difference value and the second preset difference value have different absolute values at different temperatures and are consistent in relative size;

the difference between the resistance of the first switching unit and the reference resistance is constant by adjusting the resistance of the first switching unit and/or the reference resistance.

2. The control method according to claim 1, wherein adjusting the resistance of the first switching unit and/or the reference resistance according to the high resistance state resistance at the current temperature, the low resistance state resistance at the current temperature, and the reference resistance at the current temperature comprises:

acquiring a fourth relation and/or a fifth relation, wherein the fourth relation is a relation between the resistance of the first switch unit and the control voltage, the fifth relation is a relation between a second switch unit in a reference circuit and the control voltage, the reference resistance is the resistance of the reference circuit, and the reference circuit further comprises a resistance unit electrically connected with the second switch unit;

adjusting the control voltage of the first switch unit according to the fourth relation among the high resistance state resistance at the current temperature, the low resistance state resistance at the current temperature, the reference resistance at the current temperature and/or adjusting the control voltage of the second switch unit according to the fifth relation among the high resistance state resistance at the current temperature, the low resistance state resistance at the current temperature, the reference resistance at the current temperature and the reference resistance at the current temperature.

3. The control method of claim 2, wherein the first switching unit is a first MOS transistor, the control voltage of the first MOS transistor is a first gate voltage, and the adjusting the control voltage of the first switching unit according to the fourth relationship among the high resistance at the current temperature, the low resistance at the current temperature, the reference resistance at the current temperature, and the first MOS transistor comprises:

and adjusting the first gate voltage according to the fourth relation among the high resistance state resistance at the current temperature, the low resistance state resistance at the current temperature, the reference resistance at the current temperature and the fourth relation.

4. The control method according to claim 3, wherein the second switching unit is a second MOS transistor, the control voltage of the second MOS transistor is a second gate voltage, and the adjusting the control voltage of the second switching unit according to the fifth relationship among the high resistance state resistance at the current temperature, the low resistance state resistance at the current temperature, the reference resistance at the current temperature, and the fifth relationship includes:

and adjusting the second gate voltage according to the fifth relation among the high resistance state resistance at the current temperature, the low resistance state resistance at the current temperature, the reference resistance at the current temperature and the voltage.

5. The control method according to claim 4, wherein the first gate voltage and/or the second gate voltage is adjusted by a gate voltage controller, and the gate voltage controller is an analog feedback control circuit or a gate voltage control chip.

6. A method for reading a memory cell, the memory cell including a memory bit cell and a first switch cell electrically connected to the memory bit cell, the method comprising:

acquiring a first relation, a second relation and a third relation, wherein the first relation is the relation between the low resistance state resistance and the temperature of the storage unit, the second relation is the relation between the high resistance state resistance and the temperature of the storage unit, and the third relation is the relation between the reference resistance and the temperature;

adjusting the resistance and/or the reference resistance of the first switch unit at least according to the acquired temperature, the first relation, the second relation and the third relation to obtain a final high-resistance-state resistance, a final low-resistance-state resistance and a final reference resistance, wherein a difference value between the final reference resistance and the final low-resistance-state resistance is a first preset difference value, and a difference value between the final reference resistance and the final high-resistance-state resistance is a second preset difference value;

acquiring the current resistance of the storage unit;

comparing the current resistance of the storage unit with the final reference resistance to obtain a comparison result;

reading out the data stored in the storage unit according to the comparison result;

determining the low resistance state resistance of the memory cell at the current temperature according to the acquired temperature and the first relation;

the difference between the resistance of the first switching unit and the reference resistance is made constant by adjusting the resistance of the first switching unit and/or the reference resistance.

7. A control device for controlling reading of a memory cell, the memory cell including a memory bit cell and a first switch cell electrically connected to the memory bit cell, comprising:

the first obtaining unit is used for obtaining a first relation, a second relation and a third relation, wherein the first relation is the relation between the low resistance state resistance and the temperature of the storage unit, the second relation is the relation between the high resistance state resistance and the temperature of the storage unit, and the third relation is the relation between the reference resistance and the temperature;

the adjusting unit is used for adjusting the resistance and/or the reference resistance of the first switch unit at least according to the acquired temperature, the first relation, the second relation and the third relation to obtain a final high-resistance state resistance, a final low-resistance state resistance and a final reference resistance, wherein the difference value between the final reference resistance and the final high-resistance state resistance is a first preset difference value, and the difference value between the final reference resistance and the final low-resistance state resistance is a second preset difference value;

the adjusting unit comprises a first determining module, a second determining module, a third determining module and an adjusting module;

the first determining module is used for determining the low resistance state resistance of the storage unit at the current temperature according to the acquired temperature and the first relation;

the second determining module is configured to determine the high-resistance state resistance of the memory cell at the current temperature according to the acquired temperature and the second relationship;

the third determining module is used for determining the reference resistance at the current temperature according to the acquired temperature and the third relation;

the adjusting module is used for adjusting the resistance of the first switch unit and/or the reference resistance according to the high resistance state resistance at the current temperature, the low resistance state resistance at the current temperature and the reference resistance at the current temperature;

8. A storage medium characterized by comprising a stored program, wherein the program executes the control method of any one of claims 1 to 5.

9. A processor, characterized in that the processor is configured to run a program, wherein the program is configured to execute the control method according to any one of claims 1 to 5 when running.