CN112397539B - Image sensor and method for manufacturing the same - Google Patents

Abstract

The invention provides an image sensor and a manufacturing method thereof, comprising the following steps: providing a substrate, wherein a plurality of pixel units are distributed on the substrate, and the pixel units are positioned in a first type well region in the substrate; etching the substrate to form isolation trenches between adjacent pixel units; performing second type ion implantation on the peripheral substrate of the isolation trench, wherein the second type ions and ions in the first type well region form PN junctions; the isolation layer fills the isolation trench. The isolation between the pixel units combines Deep Trench Isolation (DTI) with PN junction isolation formed by ion implantation, PN junctions are formed in the peripheral substrate of the isolation trenches, carriers generated by defects near the isolation trenches are prevented from freely entering the reading area and the photosensitive area, dark current is reduced, good electrical and optical isolation effects are achieved, the area of the isolation areas is reduced, and the chip area utilization rate of the image sensor is improved.

Description

Image sensor and method for manufacturing the same

Technical Field

The present invention belongs to the field of image sensors, and in particular relates to an image sensor and a manufacturing method thereof.

Background technique

Vertically charge transferring pixel sensors (VPS) are three-dimensional image sensors based on standard flash memory technology, and are also semiconductor image sensors based on floating gate structure arrays, that is, the pixel units of image sensors are formed based on floating gate (FG) structures. The intensity of the light signal sensed by each pixel unit is converted into the number of electrons injected into the floating gate layer of the pixel unit to achieve continuous detection and imaging of the light signal. It has the characteristics of high pixel density and small pixel size. Its working principle is to use the voltage generated by the photogenerated electrons in the photosensitive area to couple to the floating gate, thereby changing the transistor threshold voltage in the reading area and realizing image recognition. In practical applications, vertical charge transfer image sensors have problems such as large dark current and optical crosstalk between pixels.

Summary of the invention

The object of the present invention is to provide an image sensor and a manufacturing method thereof, which can reduce dark current and improve optical crosstalk between pixels of the image sensor.

The present invention provides a method for manufacturing an image sensor, comprising:

A substrate is provided, wherein the substrate has a first surface and a second surface opposite to each other; a plurality of pixel units are distributed on the substrate, and the pixel units are located in a first type well region in the substrate;

Etching the substrate to form isolation trenches between adjacent pixel units;

Performing a second type of ion implantation on the surrounding substrate of the isolation trench, so that the second type of ions in the surrounding substrate of the isolation trench form a PN junction with the ions in the first type of well region;

An isolation layer is formed, wherein the isolation layer fills the isolation trench.

Furthermore, in the ion implantation, with the vertical direction perpendicular to the substrate surface as a reference, the ion implantation inclination angle ranges from 7° to 45°.

Furthermore, in the ion implantation, the ion implantation energy ranges from 5 keV to 45 keV, and the ion implantation dose ranges from 5×10 ¹⁴ ions/cm ² to 1×10 ¹⁶ ions/cm ² .

Furthermore, before etching the substrate to form the isolation trench, the method further includes:

A shallow trench isolation is formed, wherein the shallow trench isolation is spaced and distributed in the substrate, and the shallow trench isolation extends from the second surface into the substrate along the thickness direction of the substrate; the shallow trench isolation is located between adjacent pixel units and/or between the photosensitive area and the reading area.

The isolation trench is formed after the shallow trench isolation is formed. The isolation trench penetrates a portion of the thickness of the substrate from the first surface along the thickness direction of the substrate and stops on the shallow trench isolation.

Furthermore, in the region of the substrate around the isolation trench where the second type of ions are implanted, the concentrations of the second type of ions at positions that are equally distant from the center line of the isolation trench are substantially equal.

The present invention also provides an image sensor, comprising:

A substrate having a first surface and a second surface opposite to each other; a plurality of pixel units are distributed on the substrate, and the pixel units are located in a first type well region in the substrate;

An isolation trench, wherein the isolation trench penetrates at least a portion of the thickness of the substrate, and the isolation trench is located between adjacent pixel units;

an isolation layer, wherein the isolation layer is filled in the isolation trench;

A PN junction is formed in the surrounding substrate of the isolation trench, and the PN junction is formed by the second type of ions implanted in the surrounding substrate of the isolation trench and the ions in the first type of well region.

Furthermore, each of the pixel units includes a photosensitive area and a reading area, and the isolation trench is also located between the photosensitive area and the reading area.

Furthermore, shallow trench isolations are spaced apart in the substrate, and the shallow trench isolations extend from the second surface into the substrate along the direction of the substrate thickness; the shallow trench isolations are located between adjacent pixel units and/or between the photosensitive area and the reading area; the isolation trenches extend from the first surface into the substrate along the direction of the substrate thickness, and the isolation trenches are connected to the shallow trench isolations.

Furthermore, in the region of the substrate around the isolation trench where the second type of ions are implanted, the concentrations of the second type of ions at positions that are equally distant from the center line of the isolation trench are substantially equal.

Furthermore, the second surface of the substrate is stacked with a gate dielectric layer, a floating gate layer, a dielectric stack and a control gate layer in sequence; the portion of the floating gate layer located directly below the photosensitive area and the portion located directly below the reading area are integrally arranged, and the portion of the control gate layer located directly below the photosensitive area and the portion located directly below the reading area are isolated from each other.

Furthermore, in the region where the second type of ions are implanted in the first type of well region of the circumferential substrate of the isolation trench, the concentration of the second type of ions at positions with equal distances from the center line of the isolation trench is substantially equal.

Furthermore, in a cross section perpendicular to the substrate, a cross-sectional width of the isolation trench is 0.08 to 0.3 micrometers.

Further, the second type of ions include N-type P ions, N-type As ions or P-type B ions;

When the second type of ions are N-type P ions, the implantation depth around the isolation trench is

When the second type of ions are N-type As ions, the implantation depth around the isolation trench is

When the second type of ions are P-type B ions, the implantation depth around the isolation trench is

Compared with the prior art, the present invention has the following beneficial effects:

The image sensor and its manufacturing method provided by the present invention include: providing a substrate, on which a plurality of pixel units are distributed, and the pixel units are located in a first type well region in the substrate; etching the substrate to form an isolation trench located between adjacent pixel units; performing a second type of ion implantation on the peripheral substrate of the isolation trench, and the second type of ions in the peripheral substrate of the isolation trench form a PN junction with the ions in the first type well region; forming an isolation layer, and the isolation layer fills the isolation trench. The isolation trench is usually deep, and the isolation layer located in the isolation trench plays an isolation role, which is called deep trench isolation (DTI). The isolation between pixel units combines deep trench isolation (DTI) with PN junction isolation formed by ion implantation, forming a PN junction in the surrounding substrate of the isolation trench, blocking carriers generated by defects near the deep trench isolation (DTI) from freely entering the reading area and the photosensitive area, reducing dark current while also having good electrical and optical isolation effects. In addition, in a cross-section perpendicular to the substrate, the cross-sectional area of the isolation area formed by the PN junction in the surrounding substrate of the isolation trench and the isolation layer in the isolation trench is smaller than the cross-sectional area of the isolation area formed by ion implantation alone, thereby achieving effective isolation while reducing the area of the isolation area and improving the chip area utilization of the image sensor.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic flow chart of a method for manufacturing an image sensor according to an embodiment of the present invention;

2 to 5 are schematic diagrams of steps of a method for manufacturing an image sensor according to an embodiment of the present invention.

The reference numerals are as follows:

10-substrate; 11-first type well region; 12-isolation trench; 13-PN junction; 14-isolation layer; 15-shallow trench isolation; 16-reading area; 17-photosensitive area; 21-gate dielectric layer; 22-floating gate layer; 23-dielectric stack; 24-control gate layer; 25-bonding layer; 26-second region; 27-first region; 30-carrier wafer.

Detailed ways

The embodiment of the present invention provides an image sensor and a method for manufacturing the same. The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and use an inaccurate scale, which is only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

An embodiment of the present invention provides a method for manufacturing an image sensor, as shown in FIG1 , comprising:

Providing a substrate, on which a plurality of pixel units are distributed, and the pixel units are located in a first type well region in the substrate;

Etching the substrate to form isolation trenches between adjacent pixel units;

Performing a second type of ion implantation on the surrounding substrate of the isolation trench, so that the second type of ions in the surrounding substrate of the isolation trench form a PN junction with the ions in the first type of well region;

An isolation layer is formed, wherein the isolation layer fills the isolation trench.

The image sensor and the manufacturing method thereof according to the embodiment of the present invention are described in detail below in conjunction with FIG. 2 to FIG. 4 .

As shown in FIG2 , a substrate 10 is provided, on which a plurality of pixel units are distributed, and the pixel units are located in a first type well region 11 in the substrate 10. Each of the pixel units includes a photosensitive region 17 and a reading region 16. When light is irradiated onto the photosensitive region 17, photogenerated carriers are generated in the photosensitive region 17, which is reflected as a potential change on the floating gate layer 22. After this potential change is coupled to the reading region 16, the reading current of the reading region 16 is changed, so that the light intensity is read by the reading region 16.

It should be noted that the boundary of the first type well region 11 is not necessarily the same boundary as the substrate 10 , that is, the first type well region 11 may be a certain area in the substrate 10 , and the range of the first type well region 11 may not end at the boundary of the substrate 10 .

A shallow trench isolation 15 is formed, the substrate 10 has a first surface _f1 and a second surface _f2 opposite to each other, the shallow trench isolation 15 is spaced apart in the substrate 10, the shallow trench isolation 15 extends from the second surface _f2 into the substrate 10 along the thickness direction of the substrate 10, and the shallow trench isolation 15 is located between adjacent pixel units and/or between the photosensitive area 17 and the reading area 16. Exemplarily, the material of the shallow trench isolation 15 is silicon oxide. Alternatively, the photosensitive area 17 and the reading area 16 can also be isolated by ion implantation.

As shown in FIG3 , the substrate 10 is etched to form an isolation groove 12 between adjacent pixel units. The isolation groove 12 penetrates a portion of the thickness of the substrate 10 from the first surface _f1 along the thickness direction of the substrate 10 and stops at the shallow trench isolation 15. Together they play an isolation role in the direction perpendicular to the substrate to prevent optical crosstalk between pixel units. After forming the shallow trench isolation 15, the isolation groove 12 is formed, and the shallow trench isolation 15 is used as an etching stop structure for the isolation groove 12, which can prevent damage to the pixel during the etching process. Specifically, it can prevent the etching process from damaging the gate dielectric layer 21, thereby ensuring the integrity of the gate dielectric layer 21 and improving the imaging quality.

As shown in FIG3 and FIG4, the second type of ion implantation is performed on the surrounding substrate 10 of the isolation trench 12, and the second type of ions in the surrounding substrate 10 of the isolation trench 12 form a PN junction 13 with the ions in the first type of well region. In one embodiment, the first type of well region 11 in the substrate 10 is, for example, a P-type well region, and the N-type ion implantation is performed on the surrounding substrate 10 of the isolation trench 12 to form a PN junction 13. In another embodiment, the first type of well region 11 in the substrate 10 is, for example, an N-type well region, and the P-type ion implantation is performed on the surrounding substrate 10 of the isolation trench 12 to form a PN junction 13. That is, the first type of well region 11 is a P-type well region, and the second type of ions are N-type ions; the first type of well region 11 is an N-type well region, and the second type of ions are P-type ions.

In the ion implantation, the ion implantation tilt angle α is in the range of 7° to 45°, based on the vertical direction perpendicular to the surface of the substrate 10. Exemplarily, in the ion implantation, the ion implantation energy ranges from 5keV to 45keV, and the ion implantation dose ranges from 5×10 ¹⁴ ions/cm ² to 1×10 ¹⁶ ions/cm ^2. The ion implantation can be achieved by horizontally/vertically moving the ion implantation source and/or rotating the wafer.

The ion implantation energy range is preferably 10keV, 20keV, 25keV, 30keV, 35keV.

The implanted ions are preferably N-type P (phosphorus) ions, and the implantation depth around the isolation trench 12 is (angstrom), preferably/>

The implanted ions may also be preferably N-type As (arsenic) ions, and the implantation depth around the isolation trench 12 is (angstrom), preferably/>

The implanted ions may also be preferably P-type B (boron) ions, and the implantation depth around the isolation trench 12 is (angstrom), preferably/>

Since the present embodiment performs the ion implantation process after the isolation trench 12 is formed, a better isolation effect can be achieved with a smaller ion implantation intensity and depth. Therefore, the depth of ion implantation in the present embodiment can be used as a significant feature different from the prior art.

Next, an isolation layer 14 is formed, and the isolation layer 14 fills the isolation trench 12. The isolation layer 14 includes: metal or silicide, such as tungsten or silicon oxide. The isolation trench 12 is usually deep, and the isolation layer 14 located in the isolation trench 12 plays an isolation role, which is called deep trench isolation (DTI). The isolation layer 14 can be formed by chemical vapor deposition, plasma enhanced chemical vapor deposition or high-density plasma chemical vapor deposition. Specifically, the isolation layer 14 fills the isolation trench 12 and covers the first surface _f1 of the substrate 10. The isolation layer 14 is planarized by a chemical mechanical polishing (CMP) process. Preferably, the top surface of the isolation layer 14 is flush with the first surface _f1 of the substrate 10.

In the manufacturing method of the image sensor of this embodiment, the isolation between pixel units combines deep trench isolation (DTI) with PN junction isolation formed by ion implantation, and forms a PN junction in the peripheral substrate of the isolation trench, thereby blocking carriers generated by defects near the deep trench isolation (DTI) from freely entering the reading area and the photosensitive area, thereby reducing dark current while also having good electrical and optical isolation effects. Moreover, in a cross-section perpendicular to the substrate, the cross-sectional area of the isolation area formed by the PN junction in the peripheral substrate of the isolation trench and the isolation layer in the isolation trench is smaller than the cross-sectional area of the isolation area formed by ion implantation alone, thereby achieving effective isolation while reducing the area of the isolation area and improving the chip area utilization rate of the image sensor.

Compared with the isolation region formed by ion implantation alone, the isolation between pixel units in the manufacturing method of the image sensor of this embodiment combines deep trench isolation (DTI) with ion implantation to form PN junction isolation. The ion implantation of this embodiment requires less energy, and the area of the PN junction formed around the substrate of the isolation trench can be changed by adjusting the ion implantation angle and energy. After the ion implantation is completed, an isolation layer is filled in the isolation trench to provide good optical isolation between pixels. In addition, this embodiment forms a PN junction with the well region of the pixel itself by performing ion implantation on the sidewall of the isolation trench 12, utilizing the original structure of the pixel, thereby simplifying the process.

As shown in FIG4 , the present invention further provides an image sensor, comprising:

A substrate 10, wherein the substrate 10 has a first surface and a second surface opposite to each other; a plurality of pixel units are distributed on the substrate, and the pixel units are located in a first type well region 11 in the substrate;

An isolation trench 12, wherein the isolation trench 12 penetrates at least a portion of the thickness of the substrate 10, and the isolation trench 12 is located between adjacent pixel units;

an isolation layer 14, wherein the isolation layer 14 is filled in the isolation trench 12;

A PN junction 13 is formed in the substrate 10 around the isolation trench 12 .

Specifically, each of the pixel units includes a photosensitive area 17 and a reading area 16. The substrate 10 has a first surface _f1 and a second surface _f2 opposite to each other. Shallow trench isolations (STI) 15 are spaced apart in the substrate 10, and the shallow trench isolations 15 extend from the second surface _f2 into the substrate 10 along the thickness direction of the substrate 10, and the shallow trench isolations 15 are located between adjacent pixel units and/or between the photosensitive area 17 and the reading area 16. Exemplarily, the material of the shallow trench isolations 15 is silicon oxide, for example. The isolation trench 12 extends from the first surface _f1 into the substrate 10 along the thickness direction of the substrate, and the isolation trench 12 is connected to the shallow trench isolation 15, and they play an isolation role together in a direction perpendicular to the substrate to prevent optical crosstalk between pixel units.

FIG5 shows a partial schematic diagram of the isolation trench 12 and the PN junction 13, and the isolation layer 14 is not shown for clarity. As shown in FIG5, the center line (symmetry axis) of the isolation trench 12 is AA', and the PN junction 13 is a circular ring or a square ring when viewed from above. In the region of the substrate surrounding the isolation trench 12 where the second type of ions are injected, the concentration of the second type of ions at positions that are equal to the center line AA' of the isolation trench 12 is substantially equal. For example, the distance between the line segment BB' perpendicular to the substrate direction in the PN junction 13 and the center line AA' is r; the line segment BB' takes the center line AA' as the axis, and the concentration of the second type of ions on the entire annular surface formed by the circle is substantially equal. The meaning of substantially equal should be correctly understood, because in industrial production, no process can achieve absolute equality under the same conditions, but due to the use of the same or similar process conditions, the ion concentration can be substantially equal. In addition, if the second type of ion implantation is performed first and then the isolation trench 12 is made, this technical effect cannot be achieved, because the ion implantation will gradually decay as the thickness of the substrate increases, and even if multiple ion implantations are used, the uniformity of ion implantation in this embodiment cannot be achieved. The uniformity and consistency of ion implantation in this embodiment also improve the consistency of device performance and the isolation effect.

Alternatively, the isolation trench 12 may penetrate the substrate 10 , and the isolation trench 12 is located between adjacent pixel units to directly separate two pixels. In this case, there is no shallow trench isolation 15 between the two pixels.

The isolation trench 12 may be formed after the shallow trench isolation 15 is formed, and the shallow trench isolation 15 is used as an etching stop structure for the isolation trench 12 to prevent damage to the pixel during the etching process. Specifically, the etching process can prevent damage to the gate dielectric layer 21, thereby ensuring the integrity of the gate dielectric layer 21 and improving the imaging quality.

The first surface _f1 is the surface of the image sensor receiving incident light, and the second surface _f2 of the substrate 10 is sequentially stacked with a gate dielectric layer 21, a floating gate layer 22, a dielectric stack 23 and a control gate layer 24. To facilitate process operation, the image sensor can be bonded to a wafer 30 through a bonding layer 25. The wafer 30 can be a carrier wafer, and the temporary bonding serves as a support. The wafer 30 can also be a device wafer, such as a logic wafer.

The substrate 10 is, for example, a silicon substrate; specifically, its material may be selected from single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium compounds or silicon on insulator (SOI), etc. The material of the gate dielectric layer 21 may be an oxide, such as silicon dioxide. The materials of the floating gate layer 22 and the control gate layer 24 may both be polycrystalline silicon. The dielectric stack 23 may be a stack of silicon oxide layer-silicon nitride layer-silicon oxide layer (Oxcide-Nitride-Oxcide, ONO). The control gate layer 24 may also include a circuit structure, such as a stacked dielectric layer and a wiring layer, in which interconnection vias may be arranged, and in which metal lines, contact pads (Pad) and other structures may be arranged, which may be located between the control gate layer 24 and the bonding layer 25, which are not shown in the figure.

In each of the pixel units, the floating gate layer 22 areas corresponding to the photosensitive area 17 and the reading area 16 are connected and arranged as a whole; when light is irradiated to the top of the photosensitive area 17, photogenerated carriers will be generated in the photosensitive area 17, which will be reflected as a potential change on the floating gate layer 22. After this potential change is coupled to the reading area 16, the reading current of the reading area 16 will be changed, so that the light intensity is read out by the reading area. The reading area 16 can be connected to a pixel circuit, and the pixel circuit is used to sense the voltage change caused by the charge stored in the reading area 16. The pixel circuit includes, for example, a reset transistor, a sensing transistor, an address transistor, etc. On the one hand, the pixel circuit is used to write the reset data value into the image sensor pixel to reset the reading area, and on the other hand, the pixel circuit is used to read data from the image sensor pixel, and the data corresponds to a part of the captured image.

Each pixel unit includes a photosensitive region 17 and a readout region 16 . The floating gate layer 22 and the control gate layer 24 have a first region 27 corresponding to the photosensitive region 17 , and the floating gate layer 22 and the control gate layer 24 have a second region 26 corresponding to the readout region 16 .

The floating gate layer 22 and the control gate layer 24 respectively have regions corresponding to the photosensitive region 17 and the reading region 16, which refers to the correspondence in function and/or position; specifically, the photosensitive region 17 and the first region 27 are structures belonging to the same photoelectric conversion transistor. The first region 27 is located directly below the photosensitive region 17 (the first surface _f1 is on the top and the second surface _f2 is on the bottom), and the second region 26 is located directly below the reading region 16.

In one embodiment, the photosensitive area 17 includes a photosensitive element (e.g., a photodiode PD), and the photosensitive element of the photosensitive area 17 generates photogenerated carriers under the action of light. In another embodiment, in the photosensitive area 17, a first photodiode and a second photodiode are stacked and distributed along the thickness direction of the substrate 10, and the first photodiode is located above the second photodiode. In the photosensitive area 17, a vertical charge transfer region is distributed on one side of the stacked first photodiode and the second photodiode close to the shallow trench isolation 15. The reading area 16 is connected to a pixel circuit, and the pixel circuit is used to sense the voltage change caused by the charge in the reading area.

It can be understood that the image sensor provided by the embodiment of the present invention can be a VPS structure based on a flash memory process. In the VPS structure based on a flash memory process, the photosensitive area 17 is separated from the reading area 16 by a shallow trench isolation (STI) 15. The portion of the floating gate layer 22 located directly below the photosensitive area 17 is integrally arranged with the portion located directly below the reading area 16, and the portion of the control gate layer 24 located directly below the photosensitive area 17 is isolated from the portion located directly below the reading area 16. The floating gate layer 22 regions corresponding to the photosensitive area 17 and the reading area 16 are integrally arranged, so that when the photosensitive area 17 generates photogenerated carriers under the incident light, it can generate a voltage coupling effect on the reading area 16; the control gate layers 24 corresponding to the photosensitive area 17 and the reading area 16 are isolated from each other so as to load voltages respectively to realize gate control.

The first surface _f1 is a surface of the image sensor for receiving incident light, and the image sensor prepared in this way has a back side illumination (BSI) structure. It can be understood that by using the first surface _f1 as a surface for receiving incident light, the influence of the circuit structure, the control gate layer 24, the dielectric stack 23, the floating gate layer 22, and the gate dielectric layer 21 on the incident light is avoided, thereby increasing the number of photons received.

The image sensor manufactured by the embodiment of the present invention includes an array of image sensor pixel units. The pixel units in the image sensor may include light-sensitive elements such as photodiodes that convert incident light into electrons. The image sensor may have any number of pixels (e.g., hundreds or thousands or more). A typical image sensor may, for example, have millions of pixels (e.g., megapixels). In high-end devices, the image sensor may have tens of millions of pixels.

In summary, the image sensor and its manufacturing method provided by the present invention include: providing a substrate, on which a plurality of pixel units are distributed, and the pixel units are located in a first type well region in the substrate; etching the substrate to form an isolation trench located between adjacent pixel units; performing a second type of ion implantation on the peripheral substrate of the isolation trench, and the second type of ions in the peripheral substrate of the isolation trench form a PN junction with the ions in the first type well region; forming an isolation layer, and the isolation layer fills the isolation trench. The isolation trench is usually deep, and the isolation layer located in the isolation trench plays an isolation role, which is called deep trench isolation (DTI). The isolation between pixel units combines deep trench isolation (DTI) with PN junction isolation formed by ion implantation, forming a PN junction in the surrounding substrate of the isolation trench, blocking carriers generated by defects near the deep trench isolation (DTI) from freely entering the reading area and the photosensitive area, reducing dark current while also having good electrical and optical isolation effects. In addition, in a cross-section perpendicular to the substrate, the cross-sectional area of the isolation area formed by the PN junction in the surrounding substrate of the isolation trench and the isolation layer in the isolation trench is smaller than the cross-sectional area of the isolation area formed by ion implantation alone, thereby achieving effective isolation while reducing the area of the isolation area and improving the chip area utilization of the image sensor.

In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims (13)

1. A method for manufacturing an image sensor, comprising: A substrate is provided, wherein the substrate has a first surface and a second surface opposite to each other; a plurality of pixel units are distributed on the substrate, and the pixel units are located in a first type well region in the substrate; Etching the substrate to form isolation trenches between adjacent pixel units; Performing a second type of ion implantation on the peripheral substrate of the isolation trench, so that the second type of ions in the peripheral substrate of the isolation trench and the ions in the first type of well region form a PN junction isolation; forming an isolation layer, wherein the isolation layer fills the isolation trench; Wherein, the second type of ions include N-type P ions, N-type As ions or P-type B ions; when the second type of ions are N-type P ions, the implantation depth around the isolation trench is When the second type of ions are N-type As ions, the implantation depth around the isolation trench is When the second type of ions are P-type B ions, the implantation depth around the isolation trench is 2. The method for manufacturing an image sensor according to claim 1, characterized in that, in the ion implantation, with the vertical direction perpendicular to the substrate surface as a reference, the ion implantation tilt angle range is: 7° to 45°. 3 . The method for manufacturing an image sensor according to claim 1 , wherein in the ion implantation, the ion implantation energy ranges from 5 keV to 45 keV, and the ion implantation dose ranges from 5×10 ¹⁴ ions/cm ² to 1×10 ¹⁶ ions/cm ² . 4. The method for manufacturing an image sensor according to claim 1, wherein each of the pixel units comprises a photosensitive area and a reading area; and before etching the substrate to form the isolation trench, the method further comprises: A shallow trench isolation is formed, wherein the shallow trench isolation is spaced and distributed in the substrate, and the shallow trench isolation extends from the second surface into the substrate along the thickness direction of the substrate; the shallow trench isolation is located between adjacent pixel units and/or between the photosensitive area and the reading area. 5. The method for manufacturing an image sensor as described in claim 4 is characterized in that the isolation trench is formed after the shallow trench isolation is formed, and the isolation trench penetrates a portion of the thickness of the substrate from the first surface along the thickness direction of the substrate and stops on the shallow trench isolation. 6. The method for manufacturing an image sensor as described in claim 1 is characterized in that, in the region of the substrate surrounding the isolation trench where the second type of ions are implanted, the concentration of the second type of ions at positions equidistant from the center line of the isolation trench is substantially equal. 7. An image sensor, comprising: A substrate having a first surface and a second surface opposite to each other; a plurality of pixel units are distributed on the substrate, and the pixel units are located in a first type well region in the substrate; An isolation trench, wherein the isolation trench penetrates at least a portion of the thickness of the substrate, and the isolation trench is located between adjacent pixel units; an isolation layer, wherein the isolation layer is filled in the isolation trench; PN junction isolation, the PN junction isolation is formed in the surrounding substrate of the isolation trench, and the PN junction isolation is formed by the second type of ions implanted in the surrounding substrate of the isolation trench and the ions in the first type of well region; Wherein, the second type of ions include N-type P ions, N-type As ions or P-type B ions; when the second type of ions are N-type P ions, the implantation depth around the isolation trench is When the second type of ions are N-type As ions, the implantation depth around the isolation trench is When the second type of ions are P-type B ions, the implantation depth around the isolation trench is 8 . The image sensor according to claim 7 , wherein each of the pixel units comprises a photosensitive area and a reading area, and the isolation trench is further located between the photosensitive area and the reading area. 9. The image sensor according to claim 8, wherein: Shallow trench isolations are spaced apart in the substrate, and the shallow trench isolations extend from the second surface into the substrate along the thickness direction of the substrate; the shallow trench isolations are located between adjacent pixel units and/or between the photosensitive area and the reading area; The isolation trench extends from the first surface into the substrate along the thickness direction of the substrate, and the isolation trench is connected to the shallow trench isolation. 10. The image sensor according to claim 7, wherein in the region of the substrate around the isolation trench where the second type of ions are implanted, the concentrations of the second type of ions at positions equidistant from the center line of the isolation trench are substantially equal. 11. The image sensor as described in claim 8 is characterized in that a gate dielectric layer, a floating gate layer, a dielectric stack and a control gate layer are sequentially stacked on the second surface of the substrate; a portion of the floating gate layer located directly below the photosensitive area is integrally arranged with a portion located directly below the reading area, and a portion of the control gate layer located directly below the photosensitive area is isolated from a portion located directly below the reading area. 12. The image sensor as claimed in claim 10, characterized in that, in the region where the second type of ions are implanted in the first type of well region of the circumferential substrate of the isolation trench, the concentration of the second type of ions at positions equidistant from the center line of the isolation trench is substantially equal. 13 . The image sensor according to claim 7 , wherein, in a cross section perpendicular to the substrate, a cross-sectional width of the isolation trench is 0.08 to 0.3 μm.