CN112380160A - Device and method for realizing dynamic reconfiguration of pin function in processor - Google Patents
Device and method for realizing dynamic reconfiguration of pin function in processor Download PDFInfo
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Abstract
The invention discloses a device and a method for realizing dynamic reconfiguration of pin functions in a processor. After the device and the method of the invention are applied, the pin functions of the processor are not fixed but can be dynamically reconfigured, and a user can dynamically reconfigure the pin functions of the processor chip through a program/instruction when using the processor chip or even under the operating state of the processor chip, namely, the user can dynamically reconfigure the input/output of any functional module in the processor to any pin of the processor chip through the program/instruction when using or even under the operating state of the processor chip, thereby improving the convenience and flexibility of the processor in application and improving the user experience.
Description
Technical Field
The present invention relates to the field of processor technologies, and in particular, to an apparatus and method for implementing dynamic reconfiguration of pin functions in a processor.
Background
Generally, once the processor has completed its design and tapout, it enters the production phase, the product of which is the processor chip. Generally, the connection relationship between all pins of the processor chip and the internal ports of the internal functional modules/devices is fixed, and this fixed relationship, while simplifying the design of the processor, brings some inconvenience to the application.
Disclosure of Invention
The present invention is directed to overcoming the above-mentioned drawbacks of the prior art and providing an apparatus and method for implementing dynamic reconfiguration of pin functions in a processor.
To achieve the above object, a first aspect of the present invention provides an apparatus for implementing pin function dynamic reconfiguration in a processor, comprising at least one dynamic reconfiguration table and at least one dynamic reconfiguration module,
the dynamic reconfiguration table is used for storing pin serial numbers currently configured to a single or a plurality of internal ports, each dynamic reconfiguration table is respectively composed of M-1 registers, M is the number of the configurable internal ports of the dynamic reconfiguration table, and the content of the ith register of the dynamic reconfiguration table is the pin serial number to which the ith internal port is configured; the internal port is an IO port for information exchange between an internal functional module of the processor and the outside of the processor, and the pin is a GPIO pin;
the dynamic reconfiguration modules are used for being responsible for processing dynamic reconfiguration, and each dynamic reconfiguration module at least comprises an input processing submodule and an output processing submodule which can be operated in parallel;
the output processing submodule is used for inquiring a corresponding pin serial number in a specified dynamic reconfiguration table according to the serial number of an internal port when detecting that an output request mark of the internal port is set, copying contents to be sent from an output cache of the internal port to an output cache of a pin corresponding to the pin serial number if the corresponding pin serial number is inquired, and starting output enabling of the pin to enable the contents to be output to the outside of the processor through the pin;
the input processing submodule is used for inquiring a corresponding pin serial number in a specified dynamic reconfiguration table according to the serial number of an internal port when detecting that an input request mark of the internal port is set, if the corresponding pin serial number is inquired, starting input enabling of a corresponding pin, copying contents in a current input cache of the pin into an input cache of the internal port, and realizing the function of inputting information from the outside of the processor.
In a preferred embodiment, in the above apparatus, the dynamic reconfiguration table is initially set at the time of processor design; the dynamic reconfiguration table can still be set by programs/instructions according to the needs of the application when the processor is in a running state.
In a preferred embodiment, in the above-described apparatus, when it is not necessary that all the internal ports are dynamically reconfigurable, the value of M in the dynamic reconfiguration table may be decreased; the number of bits of the registers that are formed in the dynamic reconfiguration table may be reduced in the event that all pins are not required to be dynamically reconfigurable.
In a preferred embodiment, in the above-mentioned device, each dynamic reconfiguration table is provided with a plurality of dynamic reconfiguration sub-tables, wherein the same internal port number can be simultaneously present in the plurality of dynamic reconfiguration sub-tables, so that the output of a certain internal port can be simultaneously output to a plurality of pins.
In a preferred embodiment, in the above technical solution of the apparatus, in the dynamic reconfiguration sub-table, a plurality of different internal port numbers may be configured as the same pin number, so as to implement function multiplexing of the pin.
In a preferred embodiment, in the above-described apparatus, when a plurality of dynamic reconfiguration modules are provided, the dynamic reconfiguration modules are executed concurrently, and each dynamic reconfiguration module is responsible for processing a different part of the dynamic reconfiguration table or a different dynamic reconfiguration sub-table.
A second aspect of the present invention provides a method for implementing dynamic reconfiguration of pin functions in a processor, the method comprising the steps of:
setting at least one dynamic reconfiguration table; the dynamic reconfiguration table is used for storing pin serial numbers currently configured to a single or a plurality of internal ports, each dynamic reconfiguration table is respectively composed of M-1 registers, M is the number of the configurable internal ports of the dynamic reconfiguration table, and the content of the ith register of the dynamic reconfiguration table is the pin serial number to which the ith internal port is configured; the internal port is an IO port for information exchange between an internal functional module of the processor and the outside of the processor, and the pin is a GPIO pin;
when an output processing submodule of a dynamic reconfiguration module detects that an output request mark of a certain internal port is set, inquiring a corresponding pin serial number in a specified dynamic reconfiguration table according to the serial number of the internal port, copying contents to be sent from an output cache of the internal port to an output cache of a pin corresponding to the pin serial number if the corresponding pin serial number is inquired, and starting output enabling of the pin to enable the contents to be output to the outside of a processor through the pin;
when the input processing submodule of the dynamic reconfiguration module detects that an input request mark of a certain internal port is set, the corresponding pin serial number is inquired in a specified dynamic reconfiguration table according to the serial number of the internal port, if the corresponding pin serial number is inquired, the input enabling of the corresponding pin is started, the content in the current input cache of the pin is copied into the input cache of the internal port, and the function of inputting information from the outside of the processor is realized.
In a preferred embodiment, in an aspect of the above method, the dynamic reconfiguration table is initially set at the time of processor design; the dynamic reconfiguration table can still be set by programs/instructions according to the needs of the application when the processor is in a running state.
As a preferred embodiment, in the technical solution of the above method, when it is not necessary that all the internal ports are dynamically reconfigurable, the value of M of the dynamic reconfiguration table may be decreased; the number of bits of the registers that are formed in the dynamic reconfiguration table may be reduced in the event that all pins are not required to be dynamically reconfigurable.
In a preferred embodiment, in the above method, each dynamic reconfiguration table has a plurality of dynamic reconfiguration sub-tables, wherein the same internal port number can be simultaneously present in the plurality of dynamic reconfiguration sub-tables, so that the output of a certain internal port can be simultaneously output to a plurality of pins.
As a preferred embodiment, in the technical solution of the above method, in the dynamic reconfiguration sub-table, a plurality of different internal port numbers may be configured as the same pin number, so as to implement function multiplexing of the pin.
In a preferred embodiment, in the above method, when there are a plurality of dynamic reconfiguration modules, the dynamic reconfiguration modules are executed concurrently, and each dynamic reconfiguration module is responsible for processing a different part of the dynamic reconfiguration table or a different dynamic reconfiguration sub-table.
Compared with the prior art, the invention has the beneficial effects that:
the invention can realize the function of dynamically reconfiguring the additional input/output function of the pin in the processor, thus the pin function of the processor is not fixed and can be dynamically reconfigured, a user can dynamically reconfigure the pin function of the processor chip through a program/instruction when using the processor chip or even under the running state of the processor chip, namely, the user can dynamically reconfigure the input/output of any functional module in the processor to any pin of the processor chip through the program/instruction when using the processor chip or even under the running state of the processor chip, thereby improving the convenience and flexibility of the processor in application and improving the user experience.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a functional block diagram of an apparatus for implementing dynamic reconfiguration of pin functions in a processor according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Processor chips are externally contacted through chip PINs (PINs), common chip PIN types include power, ground, analog signals, digital signals, and the like; the present invention relates to chip pins of digital signal class, wherein the chip pins for transceiving digital signals are often referred to as GPIO pins (hereinafter referred to as pins) of a processor chip.
Each processor chip is designed to implement a number of internal functional blocks, such as: UART function, SPI function, etc. The IO port through which the internal functional module exchanges information with the outside of the internal functional module is an internal port (hereinafter, referred to as an internal port) of the internal functional module, for example: the UART function has 2 internal ports, one being a transmit internal port TX and the other being a receive internal port RX.
One or more internal ports of a functional module are connected to one or more pins to enable information exchange between the internal functional module and the outside of the chip. In particular, a plurality of internal ports belonging to one or more internal functional modules can be simultaneously connected to the same pin to realize the functional multiplexing of the pin. Hereinafter, a pin to which one or a plurality of internal ports are connected is referred to as a pin to which one or a plurality of pin functions are added.
The internal ports can be broadly classified into 3 types, a pure input type, a pure output type, and a type that can be both input and output. For a pure input type of internal port, the internal port should be designed to implement input request flags and (input) cache. For a pure output type of internal port, the internal port is usually designed to implement an output request flag and (output) buffer. For an internal port capable of being input and output, the internal port is generally designed to realize an input request mark and an output request mark, and the design of the cache is dependent on whether the internal port is half-duplex or full-duplex; in the case of half-duplex, one buffer is designed to implement, otherwise two buffers are designed to implement, one to serve as an input buffer and the other to serve as an output buffer.
Example one
Referring to fig. 1, the apparatus according to an embodiment of the present invention includes at least one dynamic reconfiguration table 1 and at least one dynamic reconfiguration module 2, and the principles of the modules will be described in detail below.
The dynamic reconfiguration table 1 is used for storing pin numbers currently configured to a single or multiple internal ports, each dynamic reconfiguration table is composed of M-1 registers, M is the number of the configurable internal ports of the dynamic reconfiguration table, and the content of the ith register of the dynamic reconfiguration table is the pin number to which the ith internal port is configured, for example: assuming that the serial number of the internal port TX sent by the serial port is 8, and the internal port is configured on the pin with the serial number of 6, the content of the register No. 8 of the dynamic reconfiguration table is 6.
The dynamic reconfiguration table is initially set at processor design time. The dynamic reconfiguration table can still be set by programs/instructions according to the needs of the application when the processor is in a running state.
Dynamic reconfiguration tables of different sizes can be designed according to factors such as practical application requirements and cost of the processor chip, for example: the value of M of the dynamic reconfiguration table may be reduced in the event that all ports are not required to be dynamically reconfigurable. Alternatively, the number of bits of the registers that are formed in the dynamic reconfiguration table may be reduced in the event that all pins are not required to be dynamically reconfigurable.
A plurality of dynamic reconfiguration sub-tables can be designed according to factors such as the actual application requirement, the function and the cost of the processor chip, so that the IO processing efficiency is improved. In the case where there are multiple dynamic reconfiguration sub-tables in each dynamic reconfiguration table, the same internal port number may appear in the multiple dynamic reconfiguration sub-tables at the same time, so that the output of a certain internal port may be output to multiple pins at the same time.
In the dynamic reconfiguration sub-table, a plurality of different internal port serial numbers can be configured as the same pin serial number to realize the function multiplexing of the pin.
The dynamic reconfiguration modules 2 are used for the process responsible for dynamic reconfiguration, each of which includes, but is not limited to, an input processing submodule 21 and an output processing submodule 22 which are operable in parallel, one responsible for input processing and the other responsible for output processing, and their main operations include, but are not limited to:
the output processing sub-module 22 may be configured to, when it is detected that the output request flag of a certain internal port is set, query the corresponding pin number in the specified dynamic reconfiguration table according to the pin number of the internal port, copy, if the corresponding pin number is queried, the content to be sent from the output cache of the internal port to the output cache of the pin corresponding to the pin number, and start the output enable of the pin so that the content is output to the outside of the processor through the pin;
the input processing sub-module 21 may be configured to, when it is detected that the input request flag of a certain internal port is set, query the corresponding pin number in the specified dynamic reconfiguration table according to the pin number of the internal port, if the corresponding pin number is queried, start the input enable of the corresponding pin, and copy the content in the current input cache of the pin to the input cache of the internal port, thereby implementing a function of inputting information from outside the processor.
The dynamic reconfiguration modules with different performances and numbers can be designed according to factors such as actual application requirements, functions and cost of the processor chip, when the number of the dynamic reconfiguration modules is multiple, each dynamic reconfiguration module can be executed concurrently, and each dynamic reconfiguration module is responsible for processing different parts of the dynamic reconfiguration table or different dynamic reconfiguration sub-tables so as to improve the IO processing efficiency of the processor chip.
Example two
The second embodiment of the invention provides a method for realizing dynamic reconfiguration of a pin function in a processor, which comprises the following steps:
step S1, setting at least one dynamic reconfiguration table;
the dynamic reconfiguration table 1 is used for storing pin numbers currently configured to a single or multiple internal ports, each dynamic reconfiguration table is composed of M-1 registers, M is the number of the configurable internal ports of the dynamic reconfiguration table, and the content of the ith register of the dynamic reconfiguration table is the pin number to which the ith internal port is configured, for example: assuming that the serial number of the internal port TX sent by the serial port is 8, and the internal port is configured on the pin with the serial number of 6, the content of the register No. 8 of the dynamic reconfiguration table is 6.
The dynamic reconfiguration table is initially set at processor design time. The dynamic reconfiguration table can still be set by programs/instructions according to the needs of the application when the processor is in a running state.
Dynamic reconfiguration tables of different sizes can be designed according to factors such as practical application requirements and cost of the processor chip, for example: the value of M of the dynamic reconfiguration table may be reduced in the event that all ports are not required to be dynamically reconfigurable. Alternatively, the number of bits of the registers that are formed in the dynamic reconfiguration table may be reduced in the event that all pins are not required to be dynamically reconfigurable.
A plurality of dynamic reconfiguration sub-tables can be designed according to factors such as the actual application requirement, the function and the cost of the processor chip, so that the IO processing efficiency is improved. In the case where there are multiple dynamic reconfiguration sub-tables in each dynamic reconfiguration table, the same internal port number may appear in the multiple dynamic reconfiguration sub-tables at the same time, so that the output of a certain internal port may be output to multiple pins at the same time.
In the dynamic reconfiguration sub-table, a plurality of different internal port serial numbers can be configured as the same pin serial number to realize the function multiplexing of the pin.
Step S2, when the output processing submodule of the dynamic reconfiguration module detects that the output request mark of a certain internal port is set, the corresponding pin serial number is inquired in the appointed dynamic reconfiguration table according to the serial number of the internal port, if the corresponding pin serial number is inquired, the content to be sent is copied from the output cache of the internal port to the output cache of the pin corresponding to the pin serial number, and the output of the pin is started to enable the content to be output to the outside of the processor through the pin;
step S3, when the input processing submodule of the dynamic reconfiguration module detects that the input request flag of a certain internal port is set, querying a corresponding pin number in the specified dynamic reconfiguration table according to the serial number of the internal port, if the corresponding pin number is queried, starting the input enable of the corresponding pin, and copying the content in the current input buffer of the pin to the input buffer of the internal port, thereby implementing the function of inputting information from the external of the processor.
The dynamic reconfiguration modules with different performances and numbers can be designed according to factors such as actual application requirements, functions and cost of the processor chip, when the number of the dynamic reconfiguration modules is multiple, each dynamic reconfiguration module can be executed concurrently, and each dynamic reconfiguration module is responsible for processing different parts of the dynamic reconfiguration table or different dynamic reconfiguration sub-tables so as to improve the IO processing efficiency of the processor chip.
It should be noted that, the apparatus for implementing dynamic reconfiguration of pin functions in a processor provided in the foregoing embodiments is only illustrated by the division of the functional modules, and in practical applications, the function allocation may be completed by different functional modules according to needs, that is, the internal structure of the system is divided into different functional modules, so as to complete all or part of the functions described above.
Those skilled in the art will appreciate that all or part of the steps in the method of implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium.
The above embodiments are preferred embodiments of the present invention, but the present invention is not limited to the above embodiments, and any other changes, modifications, substitutions, combinations, and simplifications which do not depart from the spirit and principle of the present invention should be construed as equivalents thereof, and all such changes, modifications, substitutions, combinations, and simplifications are intended to be included in the scope of the present invention.
Claims (10)
1. An apparatus for implementing dynamic reconfiguration of pin functions in a processor, the apparatus comprising at least one dynamic reconfiguration table and at least one dynamic reconfiguration module,
the dynamic reconfiguration table is used for storing pin serial numbers currently configured to a single or a plurality of internal ports, each dynamic reconfiguration table is respectively composed of M-1 registers, M is the number of the configurable internal ports of the dynamic reconfiguration table, and the content of the ith register of the dynamic reconfiguration table is the pin serial number to which the ith internal port is configured; the internal port is an IO port for information exchange between an internal functional module of the processor and the outside of the processor, and the pin is a GPIO pin;
the dynamic reconfiguration modules are used for being responsible for processing dynamic reconfiguration, and each dynamic reconfiguration module at least comprises an input processing submodule and an output processing submodule which can be operated in parallel;
the output processing submodule is used for inquiring a corresponding pin serial number in a specified dynamic reconfiguration table according to the serial number of an internal port when detecting that an output request mark of the internal port is set, copying contents to be sent from an output cache of the internal port to an output cache of a pin corresponding to the pin serial number if the corresponding pin serial number is inquired, and starting output enabling of the pin to enable the contents to be output to the outside of the processor through the pin;
the input processing submodule is used for inquiring a corresponding pin serial number in a specified dynamic reconfiguration table according to the serial number of an internal port when detecting that an input request mark of the internal port is set, if the corresponding pin serial number is inquired, starting input enabling of a corresponding pin, copying contents in a current input cache of the pin into an input cache of the internal port, and realizing the function of inputting information from the outside of the processor.
2. The apparatus of claim 1, wherein the dynamic reconfiguration table is initially set at the time of processor design; the dynamic reconfiguration table can still be set by programs/instructions according to the needs of the application when the processor is in a running state.
3. The apparatus of claim 1, wherein the M value of the dynamic reconfiguration table is decreased when all of the internal ports are not required to be dynamically reconfigurable; the number of bits of the registers that are formed in the dynamic reconfiguration table may be reduced in the event that all pins are not required to be dynamically reconfigurable.
4. The apparatus of claim 1, wherein each dynamic reconfiguration table has a plurality of dynamic reconfiguration sub-tables, and wherein the same internal port number can be present in the plurality of dynamic reconfiguration sub-tables at the same time, so that the output of a certain internal port can be output to a plurality of pins at the same time;
in the dynamic reconfiguration sub-table, a plurality of different internal port serial numbers can be configured as the same pin serial number to realize the function multiplexing of the pin.
5. An apparatus for implementing pin function dynamic reconfiguration in a processor according to claim 4, wherein when there are a plurality of dynamic reconfiguration modules, the respective dynamic reconfiguration modules are executed concurrently, each responsible for handling a different part of the dynamic reconfiguration table or a different dynamic reconfiguration sub-table.
6. A method for implementing dynamic reconfiguration of pin functions in a processor, the method comprising the steps of:
setting at least one dynamic reconfiguration table; the dynamic reconfiguration table is used for storing pin serial numbers currently configured to a single or a plurality of internal ports, each dynamic reconfiguration table is respectively composed of M-1 registers, M is the number of the configurable internal ports of the dynamic reconfiguration table, and the content of the ith register of the dynamic reconfiguration table is the pin serial number to which the ith internal port is configured; the internal port is an IO port for information exchange between an internal functional module of the processor and the outside of the processor, and the pin is a GPIO pin;
when an output processing submodule of a dynamic reconfiguration module detects that an output request mark of a certain internal port is set, inquiring a corresponding pin serial number in a specified dynamic reconfiguration table according to the serial number of the internal port, copying contents to be sent from an output cache of the internal port to an output cache of a pin corresponding to the pin serial number if the corresponding pin serial number is inquired, and starting output enabling of the pin to enable the contents to be output to the outside of a processor through the pin;
when the input processing submodule of the dynamic reconfiguration module detects that an input request mark of a certain internal port is set, the corresponding pin serial number is inquired in a specified dynamic reconfiguration table according to the serial number of the internal port, if the corresponding pin serial number is inquired, the input enabling of the corresponding pin is started, the content in the current input cache of the pin is copied into the input cache of the internal port, and the function of inputting information from the outside of the processor is realized.
7. The method of claim 6, wherein the dynamic reconfiguration table is initially set at the time of processor design; the dynamic reconfiguration table can still be set by programs/instructions according to the needs of the application when the processor is in a running state.
8. The method of claim 6, wherein the M value of the dynamic reconfiguration table is decreased when all of the ports are not required to be dynamically reconfigurable; the number of bits of the registers that are formed in the dynamic reconfiguration table may be reduced in the event that all pins are not required to be dynamically reconfigurable.
9. The method of claim 6, wherein each dynamic reconfiguration table has a plurality of dynamic reconfiguration sub-tables, and wherein the same internal port number can be simultaneously present in the plurality of dynamic reconfiguration sub-tables, so that the output of one internal port can be simultaneously output to a plurality of pins;
in the dynamic reconfiguration sub-table, a plurality of different internal port serial numbers can be configured as the same pin serial number to realize the function multiplexing of the pin.
10. The method of claim 9, wherein when there are multiple dynamic reconfiguration modules, the dynamic reconfiguration modules are executed concurrently, each responsible for handling a different portion of the dynamic reconfiguration table or a different dynamic reconfiguration sub-table.
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