CN112327144B - Measurement circuit for measuring chip through IO pin - Google Patents
Measurement circuit for measuring chip through IO pin Download PDFInfo
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- CN112327144B CN112327144B CN202110000871.3A CN202110000871A CN112327144B CN 112327144 B CN112327144 B CN 112327144B CN 202110000871 A CN202110000871 A CN 202110000871A CN 112327144 B CN112327144 B CN 112327144B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2896—Testing of IC packages; Test features related to IC packages
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Abstract
The invention provides a measuring circuit for measuring a chip through an IO pin, when analog quantity to be measured is a first positive voltage to be measured, the first positive voltage to be measured, which is at a high voltage, of the chip is divided to a preset voltage through a voltage division control circuit, the preset voltage is in a voltage domain of a power voltage end, and then the preset voltage can be transmitted to the IO pin for measurement after passing through a switching circuit and a current limiting circuit; and when the analog quantity to be measured is a second positive voltage to be measured or current to be measured, the analog quantity to be measured is output through the through control circuit and is output to the IO pin through the switch circuit and the current limiting circuit to be measured, and then the analog quantity of the chip can be measured through the IO pin after the chip is packaged on the basis that the number of the packaging pins is not increased. Meanwhile, the first positive voltage to be measured is converted into the preset voltage in the voltage domain of the power supply voltage end, and a high-voltage device does not need to be arranged on an IO circuit where the IO pin is located, so that the high transmission speed of the IO pin is ensured.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a measuring circuit for measuring a chip through an IO pin.
Background
In the modern integrated circuit industry, along with the continuous development of advanced processes, the integration level of chips is higher and higher, and the functions are more and more. In order to ensure the normal operation of each circuit, in addition to placing the normal line contact positions (IO pins) of the driver chip on the Die (Die), a test Pad (Testing Pad) is usually placed to facilitate the pressure test and analog quantity measurement of the chip, and to perform problem analysis and tracing when a problem occurs. For some common chips, the number of package pins is uniform, and the test pads are not typically packaged out. After packaging, pressure testing is not needed usually, but the measurement function of the analog quantity in the chip is kept, the analysis and tracking of the problem after packaging are facilitated, and the research and development period of the chip can be greatly reduced. The reduction of the research and development period of the chip can greatly reduce the research and development cost of the chip, realize mass production quickly and finally increase the competitive advantage of the chip. Therefore, how to measure the analog quantity of the chip after packaging is one of the major research directions nowadays.
Disclosure of Invention
In view of this, the present invention provides a measurement circuit for measuring a chip through an IO pin, which can effectively solve the technical problems existing in the prior art, and can measure analog quantities, such as a first positive voltage to be measured, a second positive voltage to be measured, and a current to be measured, on the chip through the IO pin after packaging without increasing the number of package pins.
In order to achieve the purpose, the technical scheme provided by the invention is as follows:
a measurement circuit to measure a chip through an IO pin, comprising: the device comprises a current limiting circuit, a switching circuit, a pull-up circuit, a voltage division control circuit and a through control circuit;
the first end of the current limiting circuit is electrically connected with an IO pin, and the second end of the current limiting circuit is electrically connected with the switch circuit;
the switch circuit is used for responding to a first level of a starting control signal and controlling the communication among the output end of the pull-up circuit, the output end of the voltage division control circuit and the output end of the through control circuit and the second end of the current limiting circuit;
the input end of the pull-up circuit is electrically connected with a power supply voltage end, and the pull-up circuit is used for responding to the first level of the starting control signal and controlling the disconnection between the power supply voltage end and the output end of the pull-up circuit;
the input end of the voltage division control circuit is electrically connected with a measurement node, the measurement node is used for accessing an analog quantity to be measured, the analog quantity to be measured is a first positive voltage to be measured, a second positive voltage to be measured or a current to be measured of the chip, the voltage division control circuit is used for responding to the first level of the starting control signal when the analog quantity to be measured is the first positive voltage to be measured, dividing the first positive voltage to be measured to a preset voltage and then outputting the voltage, and the preset voltage is in a voltage domain of the power supply voltage end; the direct-current control circuit is used for responding to the first level of a direct-current control signal when the analog quantity to be detected is the second positive voltage to be detected or the current to be detected, the analog quantity to be detected is output, the first positive voltage to be detected is greater than the output voltage of the power supply voltage end, and the second positive voltage to be detected is less than the output voltage of the power supply voltage end.
Optionally, the current limiting circuit includes a current limiting resistor, a first end of the current limiting resistor is electrically connected to the IO pin, and a second end of the current limiting resistor is electrically connected to the switching circuit.
Optionally, the switching circuit includes: the circuit comprises a first transistor, a second transistor and a first inverter, wherein the conduction types of the first transistor and the second transistor are opposite;
the first end of the first transistor and the first end of the second transistor are both connected with the second end of the current limiting circuit, the second end of the first transistor and the second end of the second transistor are both connected with the output end of the pull-up circuit and the output end of the voltage division control circuit, the control end of the first transistor is electrically connected with the output end of the first phase inverter, the input end of the first phase inverter is connected with the starting control signal, and the control end of the second transistor is connected with the starting control signal.
Optionally, the switching circuit further includes: a first level shifter and a third transistor;
the control end of the first level shifter is connected to the starting control signal, the input end of the first level shifter is connected to a first enabling level signal, the first output end of the first level shifter is floated, the second output end of the first level shifter is electrically connected with the control end of the third transistor, the first end of the third transistor is electrically connected with the second end of the first transistor, the second end of the second transistor and the output end of the pull-up circuit, and the second end of the third transistor is electrically connected with the output end of the voltage division control circuit;
the first level shifter is used for responding to a first level of the starting control signal and controlling the first enabling level signal to be output through the second output end of the first level shifter, and the third transistor is turned on in response to the first enabling level signal.
Optionally, the switching circuit further includes: and a first input end of the first NAND gate is connected with the starting control signal, a second input end of the first NAND gate is connected with the auxiliary control signal, and an output end of the first NAND gate is electrically connected with a control end of the first level shifter.
Optionally, the pull-up circuit includes: a first end of the fourth transistor is electrically connected with the power supply voltage end, a second end of the fourth transistor is an output end of the pull-up circuit, and a control end of the fourth transistor is connected to the start control signal.
Optionally, the pull-up circuit further includes: a NOR gate and a second inverter;
the first input end of the NOR gate is connected with the opening control signal, the second end of the NOR gate is connected with the auxiliary control signal, the output end of the NOR gate is electrically connected with the input end of the second phase inverter, and the output end of the second phase inverter is electrically connected with the control end of the fourth transistor.
Optionally, the voltage division control circuit includes: the first level shifter, the voltage division circuit, the fifth transistor, the sixth transistor and the first NAND gate;
the control end of the second level shifter is connected to the output end of the second nand gate, the input end of the second level shifter is connected to a second enable level signal, the first output end of the second level shifter is electrically connected with the control end of the fifth transistor, and the second output end of the second level shifter is electrically connected with the control end of the sixth transistor;
a first end of the fifth transistor is electrically connected with the measurement node, a second end of the fifth transistor is electrically connected with a first end of the voltage division circuit, a second end of the voltage division circuit is electrically connected with a first end of the sixth transistor, a second end of the sixth transistor is electrically connected with a ground end, and an output end of the voltage division circuit is an output end of the voltage division control circuit;
a first input end of the second nand gate is connected with the starting control signal, a second input end of the second nand gate is connected with the test control signal, and an output end of the second nand gate is electrically connected with a control end of the second level shifter;
when the analog quantity to be measured is the first positive voltage to be measured, the second level shifter responds to the output signal of the second nand gate, the second enable level signal is controlled to be output through the second output end of the second level shifter, a third enable level signal with the level opposite to that of the second enable level signal is controlled to be output through the first output end of the second level shifter, the fifth transistor responds to the third enable level signal to be conducted, and the sixth transistor responds to the second enable level signal to be conducted.
Optionally, the auxiliary control signal is controlled and output by the chip, and the start control signal is controlled and output by an external control circuit independent from the chip.
Optionally, the direct current control circuit includes: a seventh transistor, a first end of which is electrically connected to the measurement node, a second end of which is an output end of the pass-through control circuit, and a control end of which is connected to the pass-through control signal.
Compared with the prior art, the technical scheme provided by the invention at least has the following advantages:
the invention provides a measuring circuit for measuring a chip through an IO pin, which comprises: the device comprises a current limiting circuit, a switching circuit, a pull-up circuit, a voltage division control circuit and a through control circuit; the first end of the current limiting circuit is electrically connected with an IO pin, and the second end of the current limiting circuit is electrically connected with the switch circuit; the switch circuit is used for responding to a first level of a starting control signal and controlling the communication among the output end of the pull-up circuit, the output end of the voltage division control circuit and the output end of the through control circuit and the second end of the current limiting circuit; the input end of the pull-up circuit is electrically connected with a power supply voltage end, and the pull-up circuit is used for responding to the first level of the starting control signal and controlling the disconnection between the power supply voltage end and the output end of the pull-up circuit; the input end of the voltage division control circuit is electrically connected with a measurement node, the measurement node is used for accessing an analog quantity to be measured, the analog quantity to be measured is a first positive voltage to be measured, a second positive voltage to be measured or a current to be measured of the chip, the voltage division control circuit is used for responding to the first level of the starting control signal when the analog quantity to be measured is the first positive voltage to be measured, dividing the first positive voltage to be measured to a preset voltage and then outputting the voltage, and the preset voltage is in a voltage domain of the power supply voltage end; the direct-current control circuit is used for responding to the first level of a direct-current control signal when the analog quantity to be detected is the second positive voltage to be detected or the current to be detected, the analog quantity to be detected is output, the first positive voltage to be detected is greater than the output voltage of the power supply voltage end, and the second positive voltage to be detected is less than the output voltage of the power supply voltage end.
According to the technical scheme provided by the invention, when the analog quantity to be measured is the first positive voltage to be measured, which is at a high voltage, of the chip is divided to a preset voltage through the voltage division control circuit, the preset voltage is in a voltage domain of a power voltage end, the preset voltage can be transmitted to the IO pin through the switching circuit and the current limiting circuit, and then the preset voltage can be measured through the IO pin; and when the analog quantity to be measured is the second positive voltage to be measured or the current to be measured, outputting the analog quantity to be measured through the through control circuit, and outputting the analog quantity to be measured to the IO pin through the switch circuit and the current limiting circuit to measure, so that the purpose of measuring the analog quantity to be measured of the chip is achieved, and then on the basis of not increasing the number of the packaging pins, the analog quantity measurement can be carried out on the chip through the IO pin after the packaging. Meanwhile, the first positive voltage to be measured is converted into the preset voltage in the voltage domain of the power supply voltage end, so that a high-voltage device does not need to be arranged on an IO circuit where the IO pin is located, and the high transmission speed of the IO pin is ensured.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a measurement circuit for measuring a chip through an IO pin according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of another measurement circuit for measuring a chip through an IO pin according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a measurement circuit, an IO circuit, and a stress test circuit of a measurement chip through an IO pin according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As described in the background, for some common types of chips, the number of package pins is uniform, and the test pads are typically not packaged out. After packaging, pressure testing is not needed usually, but the measurement function of the analog quantity in the chip is kept, the analysis and tracking of the problem after packaging are facilitated, and the research and development period of the chip can be greatly reduced. The reduction of the research and development period of the chip can greatly reduce the research and development cost of the chip, realize mass production quickly and finally increase the competitive advantage of the chip. Therefore, how to measure the analog quantity of the chip after packaging is one of the major research directions nowadays.
Based on this, the embodiment of the invention provides a measurement circuit for measuring a chip through an IO pin, which can effectively solve the technical problems in the prior art, and can measure analog quantities, such as a first positive voltage to be measured, a second positive voltage to be measured and a current to be measured, of the chip through the IO pin after packaging on the basis of not increasing the number of packaging pins.
To achieve the above object, the technical solutions provided by the embodiments of the present invention are described in detail below, specifically with reference to fig. 1 to 3.
Referring to fig. 1, a schematic structural diagram of a measurement circuit for measuring a chip through an IO pin according to an embodiment of the present invention is shown, where the measurement circuit for measuring a chip through an IO pin includes: current limiting circuit 100, switching circuit 200, pull-up circuit 300, voltage divider control circuit 400, and shoot-through control circuit 500.
A first end of the current limiting circuit 100 is electrically connected to an IO pin, and a second end of the current limiting circuit 100 is electrically connected to the switching circuit 200.
The switch circuit 200 is configured to control communication between the output terminal of the pull-up circuit 300, the output terminal of the voltage division control circuit 400, and the output terminal of the shoot-through control circuit 500 and the second terminal of the current limiting circuit 100 in response to a first level of an on control signal TMEN.
The input terminal of the pull-up circuit 300 is electrically connected to a power supply voltage terminal VCC, and the pull-up circuit 300 is configured to control disconnection between the power supply voltage terminal VCC and the output terminal of the pull-up circuit 300 in response to the first level of the start control signal TMEN.
The input end of the voltage division control circuit 300 is electrically connected with a measurement node TEST, the measurement node TEST is used for accessing an analog quantity to be measured, the analog quantity to be measured is a first positive voltage VMON to be measured, a second positive voltage VMON' to be measured or a current VMONI to be measured of the chip, the voltage division control circuit 300 is used for responding to the first level of the start control signal TMEN when the analog quantity to be measured is the first positive voltage VMON to be measured, and outputting the first positive voltage VMON to be measured after voltage division is carried out to a preset voltage Vdet, and the preset voltage Vdet is in a voltage domain of the power supply voltage end VCC; the direct control circuit is used for responding to a first level of a direct control signal TM when the analog quantity to be detected is the second positive voltage VOMN' to be detected or the current VOMNI to be detected, and outputting the analog quantity to be detected, wherein the first positive voltage to be detected is greater than the output voltage of the power voltage end, and the second positive voltage to be detected is less than the output voltage of the power voltage end. The first positive voltage to be tested can be voltage generated by a charge pump circuit in the chip, and the second positive voltage to be tested is voltage in the chip, so that the voltage needs to be selected according to actual required test voltage.
It can be understood that, according to the technical scheme provided by the embodiment of the present invention, when the analog quantity to be measured is the first positive voltage to be measured, the voltage division control circuit divides the first positive voltage to be measured, at which the chip is at a high voltage, to a preset voltage, the preset voltage is in a voltage domain of a power voltage end, and then the preset voltage can be transmitted to the IO pin through the switching circuit and the current limiting circuit, and then the preset voltage can be measured through the IO pin; and when the analog quantity to be measured is the second positive voltage to be measured or the current to be measured, outputting the analog quantity to be measured through the through control circuit, and outputting the analog quantity to be measured to the IO pin through the switch circuit and the current limiting circuit to measure, so that the purpose of measuring the analog quantity to be measured of the chip is achieved, and then on the basis of not increasing the number of the packaging pins, the analog quantity measurement can be carried out on the chip through the IO pin after the packaging. Meanwhile, the first positive voltage to be measured is converted into the preset voltage in the voltage domain of the power supply voltage end, so that a high-voltage device does not need to be arranged on an IO circuit where the IO pin is located, and the high transmission speed of the IO pin is ensured.
That is, when analog quantity measurement is performed on a chip after packaging, and when the analog quantity to be measured is the first positive voltage to be measured, the first level of the control signal is turned on to control the switching circuit and the voltage division control circuit to be turned on, the through control circuit responds to the second level of the through control signal to be turned off, the voltage division control circuit divides the first positive voltage to be measured of the chip to preset voltage, then the preset voltage can be transmitted to the IO pin through the switching circuit and the current limiting circuit, and finally the preset voltage can be measured through the IO pin. And when the analog quantity to be measured is second positive voltage to be measured or current to be measured, the voltage division control circuit responds to the first level control of the starting control signal to close the public, the switch circuit still responds to the first level of the starting control signal to start working at the moment, the direct control circuit responds to the first level of the direct control signal (the first level of the direct control signal and the second level of the direct control signal are opposite levels) to start working, and the direct control circuit outputs the second positive voltage to be measured or the current to be measured, and transmits the second positive voltage to be measured or the current to the IO pin for measurement after passing through the switch circuit and the current limiting circuit. When analog quantity measurement is carried out on the chip after packaging, the first level of the starting control signal controls the pull-up circuit to be in a closed state, namely the pull-up circuit is switched off between the power supply voltage end and the output end of the pull-up circuit, and therefore the fact that the voltage of the power supply voltage end is output by the pull-up circuit to influence the measurement of the analog quantity of the chip is avoided.
And after the chip completely measures the analog quantity, when the control starting signal outputs a second level opposite to the first level, the second level of the control starting signal controls the switch circuit and the voltage division control circuit to be in a closed working state, the direct control circuit responds to the second level of the direct control signal to be in a closed working state, the pull-up circuit responds to the second level of the control starting signal to be in an open working state, the power supply voltage end is communicated with the output end of the pull-up circuit, and therefore the condition that the coupling noise of the IO pin is transmitted to the inside of the chip through the measuring circuit can be improved.
Fig. 2 is a schematic structural diagram of another measurement circuit for measuring a chip through an IO pin according to an embodiment of the present invention.
As shown in fig. 2, the current limiting circuit 100 provided by the present invention plays a role of current limiting protection, wherein the current limiting circuit 100 includes a current limiting resistor Rb, a first end of the current limiting resistor Rb is electrically connected to an IO pin, and a second end of the current limiting resistor Rb is electrically connected to the switching circuit 200.
As shown in fig. 2, the switching circuit 200 provided in the present invention includes: a first transistor M1, a second transistor M2 and a first inverter INV1, the conduction types of the first transistor M1 and the second transistor M2 are opposite.
The first end of the first transistor M1 and the first end of the second transistor M2 are both connected to the second end of the current limiting circuit 100, the second end of the first transistor M1 and the second end of the second transistor M2 are both connected to the output end of the pull-up circuit 300 and the output end of the voltage division control circuit 400, the control end of the first transistor M1 is electrically connected to the output end of the first inverter INV1, the input end of the first inverter INV1 is connected to the start control signal TMEN, and the control end of the second transistor M2 is connected to the start control signal TMEN.
Further, the switch circuit 200 provided by the present invention further includes: a first level shifter LS1 and a third transistor M3.
A control terminal of the first level shifter LS1 is connected to the turn-on control signal TMEN, an input terminal of the first level shifter LS1 is connected to the first enable level signal HV1, a first output terminal of the first level shifter LS1 is floating, a second output terminal of the first level shifter LS1 is electrically connected to a control terminal of the third transistor M3, a first terminal of the third transistor M3 is electrically connected to a second terminal of the first transistor M1, a second terminal of the second transistor M2 and an output terminal of the pull-up circuit 300, and a second terminal of the third transistor M3 is electrically connected to an output terminal of the voltage division control circuit 400.
The first level shifter LS1 is used for controlling the first enable level signal HV1 to be output through the second output terminal of the first level shifter LS1 in response to the first level of the turn-on control signal TMEN, and the third transistor M3 is turned on in response to the first enable level signal HV 1.
Further, the switching circuit 200 provided in the embodiment of the present invention further includes: a first input end of the first nand gate is connected to the start control signal TMEN, a second input end of the first nand gate is connected to the auxiliary control signal FTMEN, and an output end of the first nand gate is electrically connected to a control end of the first level shifter LS 1.
As shown in fig. 2, the pull-up circuit 300 according to the embodiment of the present invention includes: a fourth transistor M4, wherein a first terminal of the fourth transistor M4 is electrically connected to the power voltage terminal VCC, a second terminal of the fourth transistor M4 is an output terminal of the pull-up circuit 300, and a control terminal of the fourth transistor M4 is connected to the on control signal TMEN.
Further, the pull-up circuit 300 according to the embodiment of the present invention further includes: a nor gate and a second inverter INV 2.
The first input end of the nor gate is connected to the opening control signal TMEN, the second end of the nor gate is connected to the auxiliary control signal FTMEN, the output end of the nor gate is electrically connected to the input end of the second inverter INV2, and the output end of the second inverter INV2 is electrically connected to the control end of the fourth transistor M4.
As shown in fig. 2, the voltage division control circuit 400 according to the embodiment of the present invention includes: a second level shifter LS2, a voltage divider circuit, a fifth transistor M5, a sixth transistor M6, and a second nand gate.
A control end of the second level shifter LS2 is connected to an output end of the second nand gate, an input end of the second level shifter LS2 is connected to the second enable level signal HV2, a first output end of the second level shifter LS2 is electrically connected to a control end of the fifth transistor M5, and a second output end of the second level shifter LS2 is electrically connected to a control end of the sixth transistor M6.
A first end of the fifth transistor M5 is electrically connected to the measurement node TEST, a second end of the fifth transistor M5 is electrically connected to a first end of the voltage divider circuit, a second end of the voltage divider circuit is electrically connected to a first end of the sixth transistor M6, a second end of the sixth transistor M6 is electrically connected to a ground GND, and an output end of the voltage divider circuit is an output end of the voltage divider control circuit 400.
The first input end of the second nand gate is connected to the start control signal TMEN, the second input end of the second nand gate is connected to the test control signal TMEN', and the output end of the second nand gate is electrically connected to the control end of the second level shifter LS 2.
When the analog quantity to be measured is the first positive voltage to be measured, the turn-on control signal is at a first level, the second nand gate outputs an active level in response to the first level of the turn-on control signal and the test control signal TMEN', the second level shifter LS2 is configured to control the second enable level signal HV2 to be output through the second output terminal of the second level shifter LS2 in response to the output signal of the second nand gate, and control a third enable level signal HV3 with a level opposite to that of the second enable level signal HV2 to be output through the first output terminal of the second level shifter LS2, the fifth transistor M5 is turned on in response to the third enable level signal HV3, and the sixth transistor M6 is turned on in response to the second enable level signal HV 2. Optionally, the voltage dividing circuit provided in the embodiment of the present invention may be composed of a voltage dividing resistor, and the present invention is not limited specifically.
As shown in fig. 2, the pass-through control circuit 500 according to the embodiment of the present invention includes: a seventh transistor M7, a first terminal of the seventh transistor M7 is electrically connected to the measurement node TEST, a second terminal of the seventh transistor M7 is an output terminal of the pass control circuit 500, and a control terminal of the seventh transistor M7 is connected to the pass control signal TM.
Referring to fig. 2, the embodiment of the invention will be described by taking as an example that the first transistor M1, the fourth transistor M4, and the fifth transistor M5 are P-type transistors, the second transistor M2, the third transistor M3, the sixth transistor M6, and the seventh transistor are N-type transistors, the first level of the through control signal TM is high, the second level of the through control signal TM is low, the first level of the on control signal TMEN is high, the second level of the on signal TMEN is low, and the first enable level signal HV1 and the second enable level signal HV2 are high.
When the analog quantity to be measured is the first positive voltage to be measured, the seventh transistor M7 is turned off in response to the second level of the direct-connection control signal TM; wherein the first transistor M1 and the second transistor M2 are turned on when the on control signal TMEN is at a first level; meanwhile, when the auxiliary control signal FTMEN and the test control signal TMEN' are enabled, the second output terminal of the first level shifter LS1 outputs the first enable level signal to control the third transistor M3 to be turned on, so that the switch circuit 300 is turned on. And the first output end of the second level shifter LS2 outputs a third enable level signal HV3 with a low level, so that the fifth transistor M5 is turned on, the second output end of the second level shifter LS2 outputs a second enable level signal HV2 with a high level, so that the sixth transistor M6 is turned on, the voltage divider circuit divides the first positive voltage to be measured of the chip accessed by the measurement node TEST to a preset voltage, the preset voltage is transmitted to the IO pin through the paths of the third transistor M3, the first transistor M1, the second transistor M2 and the current limiting resistor Rb, and finally the measurement of the first positive voltage to be measured of the chip is performed through the IO pin, so that the measurement of the analog quantity of the packaged chip is completed.
When the analog quantity to be measured is a second positive voltage to be measured or a current to be measured, the seventh transistor M7 is turned on in response to the first level of the direct control signal TM, the seventh transistor M7 outputs the second positive voltage to be measured or the current to be measured, and then the second positive voltage to be measured or the current to be measured is transmitted to the IO pin through the paths of the third transistor M3, the first transistor M1, the second transistor M2 and the current-limiting resistor Rb for measurement; and the turn-on control signal TMEN is at the first level, the first transistor M1 and the second transistor M2 are turned on; meanwhile, the auxiliary control signal FTMEN is enabled, the test control signal TMEN' is disabled, the second output terminal of the first level shifter LS1 outputs the first enable level signal, and the third transistor M3 is controlled to be turned on, so that the switch circuit 300 is turned on. And, the second level shifter LS2 controls the fifth transistor M5 and the sixth transistor M6 to be turned off.
When the turn-on control signal TMEN is at the second level and the pass-through control signal TM is at the second level, at this time, the first transistor M1, the second transistor M2, the third transistor M3, the fifth transistor M5, the sixth transistor M6 and the seventh transistor M7 are turned off, the fourth transistor M4 of the pull-up circuit 300 is turned on, and the fourth transistor M4 outputs the voltage of the power supply voltage terminal, so that the coupling noise of the IO pin is improved from being transmitted to the inside of the chip through the measurement circuit.
In any of the above embodiments of the present invention, the auxiliary control signal provided by the present invention is controlled and output by the chip, and the start control signal is controlled and output by an external control circuit that is independent from the chip, so that the output control signal is controlled by two different circuit structures to control the measurement circuit, thereby reducing the risk that the IO circuit connected to the IO pin cannot normally operate due to the misoperation.
In an embodiment of the invention, when the conduction types of the fifth transistor and the seventh transistor provided by the invention are opposite, the through control signal may be a signal of the first output terminal of the second level shifter.
In order to further describe the technical solution provided by the embodiment of the present invention, referring to fig. 3, a schematic structural diagram of a measurement circuit, an IO circuit, and a stress Test circuit of a measurement chip through an IO pin provided by the embodiment of the present invention is changed to a circuit including a Test pin before packaging. IO in the IO circuit is an output signal and is connected to the internal chip; PU _ N is a control signal output by the chip control, VCC is a high-voltage power supply voltage end, VSS is a low-voltage power supply end, and Schmitt is a Schmitt trigger. In the pressure test circuit, a Tset pin is a contact position of a chip before packaging for pressure test and analog quantity test, EN is a first enabling signal during test, EN1 is a second enabling signal during test, LS3 is a third level shifter, LS4 is a fourth level shifter, VMON is a first positive voltage to be tested, VOMN' is a second positive voltage to be tested, VOMNI is current to be tested, HVPP is high voltage generated by a charge pump in the chip, and HV3 is a fourth enabling level signal.
In the testing process before packaging, when a first enable signal EN is enabled, a transistor connected with a third level shifter is controlled to be conducted, so that a VMON pin and a Test pin are directly connected, and high voltage is applied to a measuring node through the Test pin during pressure testing and then is directly transmitted to the VMON pin for pressure testing; the analog high voltage measurement is transmitted to the Test pin through the VMON for testing. And when the second enable signal EN1 is enabled, controlling the transistor connected with the fourth level shifter to be conducted, so that the VMON 'or the VMONI is directly connected with the Test pin, and then transmitting the VMON' or the VMONI to the Test pin for testing.
After packaging, the Test pin cannot be packaged, so that the analog quantity can be measured through the measurement circuit of the IO pin measurement chip provided by the embodiment of the invention, and effective help is provided for analyzing and tracking the packaged problem.
The embodiment of the invention provides a measuring circuit for measuring a chip through an IO pin, which comprises: the device comprises a current limiting circuit, a switching circuit, a pull-up circuit, a voltage division control circuit and a through control circuit; the first end of the current limiting circuit is electrically connected with an IO pin, and the second end of the current limiting circuit is electrically connected with the switch circuit; the switch circuit is used for responding to a first level of a starting control signal and controlling the communication among the output end of the pull-up circuit, the output end of the voltage division control circuit and the output end of the through control circuit and the second end of the current limiting circuit; the input end of the pull-up circuit is electrically connected with a power supply voltage end, and the pull-up circuit is used for responding to the first level of the starting control signal and controlling the disconnection between the power supply voltage end and the output end of the pull-up circuit; the input end of the voltage division control circuit is electrically connected with a measurement node, the measurement node is used for accessing an analog quantity to be measured, the analog quantity to be measured is a first positive voltage to be measured, a second positive voltage to be measured or a current to be measured of the chip, the voltage division control circuit is used for responding to the first level of the starting control signal when the analog quantity to be measured is the first positive voltage to be measured, dividing the first positive voltage to be measured to a preset voltage and then outputting the voltage, and the preset voltage is in a voltage domain of the power supply voltage end; the direct-current control circuit is used for responding to the first level of a direct-current control signal when the analog quantity to be detected is the second positive voltage to be detected or the current to be detected, the analog quantity to be detected is output, the first positive voltage to be detected is greater than the output voltage of the power supply voltage end, and the second positive voltage to be detected is less than the output voltage of the power supply voltage end.
According to the technical scheme provided by the embodiment of the invention, when the analog quantity to be measured is the first positive voltage to be measured, which is at a high voltage, of the chip is divided to a preset voltage through the voltage division control circuit, the preset voltage is in a voltage domain of a power voltage end, then the preset voltage can be transmitted to the IO pin through the switching circuit and the current limiting circuit, and then the preset voltage can be measured through the IO pin; and when the analog quantity to be measured is the second positive voltage to be measured or the current to be measured, outputting the analog quantity to be measured through the through control circuit, and outputting the analog quantity to be measured to the IO pin through the switch circuit and the current limiting circuit to measure, so that the purpose of measuring the analog quantity to be measured of the chip is achieved, and then on the basis of not increasing the number of the packaging pins, the analog quantity measurement can be carried out on the chip through the IO pin after the packaging. Meanwhile, the first positive voltage to be measured is converted into the preset voltage in the voltage domain of the power supply voltage end, so that a high-voltage device does not need to be arranged on an IO circuit where the IO pin is located, and the high transmission speed of the IO pin is ensured.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. A measurement circuit for measuring a chip through an IO pin, comprising: the device comprises a current limiting circuit, a switching circuit, a pull-up circuit, a voltage division control circuit and a through control circuit;
the first end of the current limiting circuit is electrically connected with an IO pin, and the second end of the current limiting circuit is electrically connected with the switch circuit;
the switch circuit is used for responding to a first level of a starting control signal and controlling the communication among the output end of the pull-up circuit, the output end of the voltage division control circuit and the output end of the through control circuit and the second end of the current limiting circuit;
the input end of the pull-up circuit is electrically connected with a power supply voltage end, and the pull-up circuit is used for responding to the first level of the starting control signal and controlling the disconnection between the power supply voltage end and the output end of the pull-up circuit;
the input end of the voltage division control circuit is electrically connected with a measurement node, the measurement node is used for accessing an analog quantity to be measured, the analog quantity to be measured is a first positive voltage to be measured, a second positive voltage to be measured or a current to be measured of the chip, the voltage division control circuit is used for responding to the first level of the starting control signal when the analog quantity to be measured is the first positive voltage to be measured, dividing the first positive voltage to be measured to a preset voltage and then outputting the voltage, and the preset voltage is in a voltage domain of the power supply voltage end; the direct-current control circuit is used for responding to a first level of a direct-current control signal to output the analog quantity to be detected when the analog quantity to be detected is the second positive voltage to be detected or the current to be detected, wherein the first positive voltage to be detected is greater than the output voltage of the power supply voltage end, and the second positive voltage to be detected is less than the output voltage of the power supply voltage end;
the voltage division control circuit includes: the first level shifter, the voltage division circuit, the fifth transistor, the sixth transistor and the first NAND gate;
the control end of the second level shifter is connected to the output end of the second nand gate, the input end of the second level shifter is connected to a second enable level signal, the first output end of the second level shifter is electrically connected with the control end of the fifth transistor, and the second output end of the second level shifter is electrically connected with the control end of the sixth transistor;
a first end of the fifth transistor is electrically connected with the measurement node, a second end of the fifth transistor is electrically connected with a first end of the voltage division circuit, a second end of the voltage division circuit is electrically connected with a first end of the sixth transistor, a second end of the sixth transistor is electrically connected with a ground end, and an output end of the voltage division circuit is an output end of the voltage division control circuit;
a first input end of the second nand gate is connected with the starting control signal, a second input end of the second nand gate is connected with the test control signal, and an output end of the second nand gate is electrically connected with a control end of the second level shifter;
when the analog quantity to be measured is the first positive voltage to be measured, the second level shifter responds to the output signal of the second nand gate, the second enable level signal is controlled to be output through the second output end of the second level shifter, a third enable level signal with the level opposite to that of the second enable level signal is controlled to be output through the first output end of the second level shifter, the fifth transistor responds to the third enable level signal to be conducted, and the sixth transistor responds to the second enable level signal to be conducted.
2. The measurement circuit of the measurement chip through the IO pin according to claim 1, wherein the current limiting circuit includes a current limiting resistor, a first end of the current limiting resistor is electrically connected to the IO pin, and a second end of the current limiting resistor is electrically connected to the switch circuit.
3. The measurement circuit of an IO pin measurement chip according to claim 1, wherein the switch circuit includes: the circuit comprises a first transistor, a second transistor and a first inverter, wherein the conduction types of the first transistor and the second transistor are opposite;
the first end of the first transistor and the first end of the second transistor are both connected with the second end of the current limiting circuit, the second end of the first transistor and the second end of the second transistor are both connected with the output end of the pull-up circuit and the output end of the voltage division control circuit, the control end of the first transistor is electrically connected with the output end of the first phase inverter, the input end of the first phase inverter is connected with the starting control signal, and the control end of the second transistor is connected with the starting control signal.
4. The measurement circuit of the measurement chip through the IO pin according to claim 3, wherein the switch circuit further includes: a first level shifter and a third transistor;
the control end of the first level shifter is connected to the starting control signal, the input end of the first level shifter is connected to a first enabling level signal, the first output end of the first level shifter is floated, the second output end of the first level shifter is electrically connected with the control end of the third transistor, the first end of the third transistor is electrically connected with the second end of the first transistor, the second end of the second transistor and the output end of the pull-up circuit, and the second end of the third transistor is electrically connected with the output end of the voltage division control circuit;
the first level shifter is used for responding to a first level of the starting control signal and controlling the first enabling level signal to be output through the second output end of the first level shifter, and the third transistor is turned on in response to the first enabling level signal.
5. The measurement circuit of an IO pin measurement chip according to claim 4, wherein the switch circuit further includes: and a first input end of the first NAND gate is connected with the starting control signal, a second input end of the first NAND gate is connected with the auxiliary control signal, and an output end of the first NAND gate is electrically connected with a control end of the first level shifter.
6. The measurement circuit of an IO pin measurement chip according to claim 1, wherein the pull-up circuit includes: a first end of the fourth transistor is electrically connected with the power supply voltage end, a second end of the fourth transistor is an output end of the pull-up circuit, and a control end of the fourth transistor is connected to the start control signal.
7. The measurement circuit of an IO pin measurement chip according to claim 6, wherein the pull-up circuit further includes: a NOR gate and a second inverter;
the first input end of the NOR gate is connected with the opening control signal, the second end of the NOR gate is connected with the auxiliary control signal, the output end of the NOR gate is electrically connected with the input end of the second phase inverter, and the output end of the second phase inverter is electrically connected with the control end of the fourth transistor.
8. The measurement circuit of the measurement chip through the IO pin according to claim 5 or 7, wherein the auxiliary control signal is controlled and outputted by the chip, and the turn-on control signal is controlled and outputted by an external control circuit independent from the chip.
9. The measurement circuit of the measurement chip through the IO pin according to claim 1, wherein the pass-through control circuit includes: a seventh transistor, a first end of which is electrically connected to the measurement node, a second end of which is an output end of the pass-through control circuit, and a control end of which is connected to the pass-through control signal.
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| CN115065358B (en) * | 2022-07-26 | 2024-05-17 | 广东高云半导体科技股份有限公司 | IO driving circuit and chip |
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| CN103472347A (en) * | 2012-06-08 | 2013-12-25 | 富泰华工业（深圳）有限公司 | Auxiliary testing circuit, chip with auxiliary testing circuit and circuit board with auxiliary testing circuit |
| CN205945689U (en) * | 2016-08-17 | 2017-02-08 | 杰华特微电子（杭州）有限公司 | Multiplexing chip of chip fin |
| CN108459218B (en) * | 2018-02-05 | 2021-05-14 | 天地融电子（天津）有限公司 | Test circuit |
| CN108469582B (en) * | 2018-02-05 | 2020-09-08 | 天地融电子（天津）有限公司 | Test circuit |
| CN109031089B (en) * | 2018-06-13 | 2024-06-25 | 茂睿芯（深圳）科技有限公司 | Synchronous rectification chip, automatic detection circuit and automatic detection method for power supply of synchronous rectification chip |
| CN208384022U (en) * | 2018-07-03 | 2019-01-15 | 深圳市金锐显数码科技有限公司 | A kind of detection circuit for USB power supply |
| CN208890363U (en) * | 2018-12-03 | 2019-05-21 | 福建超瑞创原信息技术有限公司 | A kind of IO current-limiting circuit and equipment with the circuit |
| CN110190841B (en) * | 2019-06-06 | 2023-08-01 | 深圳市兆威机电股份有限公司 | IO port multiplexing control circuit and electronic equipment |
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