CN112289813B

CN112289813B - Array substrate, display panel and display device

Info

Publication number: CN112289813B
Application number: CN202011180461.3A
Authority: CN
Inventors: 胡良; 陈鑫; 李家欣; 蔡雨
Original assignee: Hubei Changjiang New Display Industry Innovation Center Co Ltd
Current assignee: Hubei Changjiang New Display Industry Innovation Center Co Ltd
Priority date: 2020-10-29
Filing date: 2020-10-29
Publication date: 2022-10-14
Anticipated expiration: 2040-10-29
Also published as: CN112289813A

Abstract

The application discloses array substrate, display panel and display device. The array substrate comprises a substrate and a first transistor positioned on one side of the substrate; the first transistor includes a first semiconductor layer including a channel region and source and drain regions respectively located at both sides of the channel region in a first direction; a first barrier structure including a first sub-barrier structure and a second sub-barrier structure; the first sub-blocking structure is positioned on one side of the first semiconductor layer, which is far away from the substrate base plate, and at least partially covers the channel region in the direction vertical to the plane of the substrate base plate; the second sub-barrier structure is located on at least one side of the channel region in a second direction, wherein the first direction intersects the second direction. According to the embodiment of the application, the stability of the transistor can be improved.

Description

Array substrate, display panel and display device

Technical Field

The application relates to the technical field of display, in particular to an array substrate, a display panel and a display device.

Background

With the development of display technology, the requirements of users on the display performance of display devices are higher and higher. In a display device, a light-emitting element is generally controlled to emit light for display by a driver circuit, and the driver circuit includes a transistor, and if the transistor is unstable, the display performance of the display device is affected.

Therefore, how to improve the stability of the transistor is an urgent technical problem to be solved by those skilled in the art.

Disclosure of Invention

The application provides an array substrate, a display panel and a display device, which can improve the stability of a transistor.

In one aspect, an embodiment of the present application provides an array substrate, which includes a substrate and a first transistor located on one side of the substrate; the first transistor comprises a first semiconductor layer, wherein the first semiconductor layer comprises a channel region and a source region and a drain region which are respectively positioned at two sides of the channel region in the first direction; a first barrier structure including a first sub-barrier structure and a second sub-barrier structure; the first sub-blocking structure is positioned on one side of the first semiconductor layer, which is far away from the substrate base plate, and at least partially covers the channel region in the direction vertical to the plane of the substrate base plate; the second sub-barrier structure is located on at least one side of the channel region in a second direction, wherein the first direction intersects the second direction.

In another aspect, an embodiment of the present application provides a display panel, which includes the array substrate according to the above embodiment.

In another aspect, an embodiment of the present application provides a display device, which includes the display panel described in the above embodiments.

According to the array substrate, the display panel and the display device provided by the embodiment of the application, the first blocking structure is arranged around the channel region of the first semiconductor layer, on one hand, the first blocking structure can be used for blocking hydrogen from diffusing to the channel region of the first semiconductor layer, so that the short channel effect of the channel region is avoided; on the other hand, the first blocking structure can be used for blocking light rays from irradiating the channel region of the first semiconductor layer, so that the phenomenon of current leakage in the channel region is avoided. That is, according to the embodiment of the present application, the stability of the first transistor can be improved.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, when taken in conjunction with the accompanying drawings, in which like or similar reference characters designate like or similar features, and which are not necessarily drawn to scale.

Fig. 1 is a schematic perspective view illustrating an array substrate according to an embodiment of the present disclosure;

fig. 2 to 5 are schematic views illustrating a manufacturing process of an array substrate according to an embodiment of the present disclosure;

fig. 6 is a schematic perspective view illustrating an array substrate according to another embodiment of the present application;

fig. 7 is a schematic cross-sectional view illustrating an array substrate according to another embodiment of the present disclosure;

fig. 8 is a schematic cross-sectional view of an array substrate according to another embodiment of the present disclosure;

fig. 9 to 14 are schematic views illustrating a flow structure of a partial film layer of an array substrate according to an embodiment of the present disclosure;

fig. 15 is a schematic structural diagram of a display panel according to an embodiment of the present application;

fig. 16 is a schematic structural diagram of a display device according to an embodiment of the present application;

Detailed Description

Features of various aspects and exemplary embodiments of the present application will be described in detail below, and in order to make objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by illustrating examples thereof.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.

It will be understood that when a layer, region or layer is referred to as being "on" or "over" another layer, region or layer in describing the structure of the component, it can be directly on the other layer, region or layer or intervening layers or regions may also be present. Also, if the component is turned over, one layer or region may be "under" or "beneath" another layer or region.

The array substrate generally includes a plurality of layers stacked one on another, and the inventors of the present application have found that some of the layers of the array substrate are hydrogen-rich layers, i.e., the layers contain rich hydrogen, such as a capacitor insulating Layer, an Inter Layer Dielectric (ILD), a Thin-Film Encapsulation (TFE), and the like. Hydrogen from these layers diffuses into the channel region of the semiconductor layer of the transistor, for example, hydrogen diffuses into the channel region of the semiconductor layer including metal oxide, which may cause short channel effect in the channel region, and thus affect the stability of the transistor. In addition, after the channel region of the semiconductor layer of the transistor is irradiated with light, a leakage current phenomenon occurs, and the stability of the transistor is also affected.

In view of the above technical problems, embodiments of the present invention provide an array substrate, a display panel and a display device, and specific structures of the array substrate, the display panel and the display device provided in the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

Fig. 1 illustrates a schematic perspective structure of an array substrate according to an embodiment of the present application. As shown in fig. 1, an array substrate 100 provided in the present embodiment includes a substrate 01, a first transistor 10, and a first blocking structure 30. The first transistor 10 and the first barrier structure 30 are located on the same side of the substrate base 01.

The first transistor 10 includes a first semiconductor layer 11. It is understood that the first semiconductor layer 11 is an active layer of the first transistor 10. The first semiconductor layer 11 includes a channel region 111, a source region 112, and a drain region 113. The source region 112 and the drain region 113 are respectively located on both sides of the channel region 111 in the first direction X.

The first barrier structure 30 includes a first sub-barrier structure 31 and a second sub-barrier structure 32. The first sub-barrier structure 31 is located on a side of the first semiconductor layer 11 away from the substrate base plate 01. In the direction Z perpendicular to the plane of the substrate base 01, the first sub-barrier structure 31 at least partially covers the channel region 111, that is, the orthographic projection of the first sub-barrier structure 31 on the substrate base 01 at least partially overlaps with the orthographic projection of the channel region 111 on the substrate base 01, and in the direction perpendicular to the plane of the substrate base 01, the channel region 111 can be protected by blocking.

The second sub-blocking structure 32 is located on at least one side of the channel region 111 in the second direction Y, and further can block and protect at least one side of the channel region 111 in the second direction Y. The first direction X and the second direction Y intersect. Illustratively, the first direction X and the second direction Y are perpendicular. Fig. 1 shows that the channel region 111 is provided with the second sub-barrier structures 32 on both sides in the second direction Y, and therefore, both sides of the channel region 111 can be barrier-protected in the second direction Y. In addition, since the channel region 111 has the source region 112 and the drain region 113 distributed on both sides in the first direction X, it may not be necessary to provide the blocking structure on both sides of the channel region 111 in the first direction X.

In some alternative embodiments, the first semiconductor layer 11 may include a metal oxide. For example, indium Gallium Zinc Oxide (IGZO). As described above, after the channel region of the semiconductor layer of metal oxide is affected by hydrogen, a short channel effect occurs. According to the embodiment of the present application, the first blocking structure 30 is disposed around the channel region 111 of the first semiconductor layer 10, and the first blocking structure 30 may be a hydrogen blocking structure, that is, the first blocking structure 30 may be used to block hydrogen from diffusing to the channel region 111 of the first semiconductor layer 10, so as to avoid a short channel effect occurring in the channel region 111, and further improve the stability of the first transistor 10.

In other alternative embodiments, the specific material included in the first semiconductor layer 11 may not be limited. The first semiconductor layer 11 may be a metal oxide semiconductor layer or a silicon semiconductor layer. Illustratively, the first semiconductor layer 11 may include silicon. Such as Low Temperature Polysilicon (LTPS). As described above, after the channel region of the semiconductor layer is irradiated with light, a leakage current phenomenon may occur. According to the embodiment of the present disclosure, the first blocking structure 30 is disposed around the channel region 111 of the first semiconductor layer 10, and the first blocking structure 30 may be a light shielding structure, for example, the first blocking structure 30 may include a non-metal material, and the non-metal material may be a black material, so that the first blocking structure 30 may be used to block light from irradiating the channel region 111 of the first semiconductor layer 10, thereby preventing the channel region 111 from having a leakage current phenomenon, and further improving the stability of the first transistor 10.

In still other alternative embodiments, the first blocking structure 30 may be used to block hydrogen from diffusing into the channel region 111 of the first semiconductor layer 10 and to block light from irradiating the channel region 111 of the first semiconductor layer 10, so as to prevent short channel effect from occurring in the channel region 111 and prevent leakage current from occurring in the channel region 111, thereby improving stability of the first transistor 10.

Illustratively, the first barrier structure 30 may comprise a non-metallic material. The non-metallic material may include at least one of graphite, carbon nanotubes, polypyrrole, polyaniline. The non-metal materials are all black materials, so that the first blocking structure 30 can block hydrogen from diffusing to the channel region 111 and can block light.

In some alternative embodiments, the substrate 01 may be a flexible substrate, for example, the substrate 01 may include Polyimide (PI). The base substrate 01 may be a rigid substrate, for example, the base substrate 01 may be a glass substrate.

It should be noted that fig. 1 only shows one first transistor 10, and the array substrate 100 may include a plurality of first transistors 10, which is not limited in the present application. In addition, not only the first semiconductor layer 11 of the first transistor 10 is illustrated in fig. 1, it should be understood that the first transistor 10 further includes a gate electrode 12, a source electrode 13, a drain electrode 14, and the like, and the array substrate 100 further includes an insulating layer and the like, for which the following embodiments will be described.

In some alternative embodiments, the first transistor 10 includes the first gate 12, and the first sub-blocking structure 31 may be multiplexed into the first gate 12. Therefore, the film structure can be simplified, and the cost can be reduced.

In other alternative embodiments, the second sub-barrier structure 32 may also be multiplexed as the first gate 12. The first sub-barrier structure 31 and the second sub-barrier structure 32 are multiplexed into the first gate 12 at the same time, which is equivalent to increasing the area of the first gate 12, so that the control capability of the first gate 12 is enhanced, and the stability of the first transistor 10 can be further improved.

Illustratively, the first barrier structure 30 may include a metal material. The metal material may include at least one of titanium (Ti), aluminum (Al), molybdenum (Mo). When the first barrier structure 30 is formed of the metal material, the first barrier structure 30 can serve not only as the first gate electrode 12 of the first transistor 10 but also as a hydrogen blocking and light shielding function.

Illustratively, the first barrier structure 30 may be a metal stack structure. For example, the first barrier structure 30 may include three metal layers stacked, the outer two metal layers may be made of titanium, and the middle metal layer may be made of aluminum. For another example, the first barrier structure 30 may include two metal layers stacked one on top of the other, wherein the material of one metal layer is titanium and the material of the other metal layer is molybdenum.

Illustratively, when the first barrier structure 30 includes a metal material, a non-metal element with a strong electronegativity may be doped in the metal material. Such as doping nitrogen element, fluorine element, phosphorus element, etc. The non-metallic elements have strong electronegativity and strong adsorbability to hydrogen, so that the blocking effect on hydrogen can be enhanced.

It should be understood that when the first sub-barrier structure 31 and the second sub-barrier structure 32 are multiplexed as the first gate 12 at the same time, the first sub-barrier structure 31 and the second sub-barrier structure 32 should be disposed in an insulating manner from the first semiconductor layer 11. When the first sub-barrier structure 31 and the second sub-barrier structure 32 are not reused as the first gate 12, the first sub-barrier structure 31 and the second sub-barrier structure 32 may be disposed in an insulating manner or in a non-insulating manner with respect to the first semiconductor layer 11, which is not limited in this application.

In some alternative embodiments, the first sub-barrier structure 31 and the second sub-barrier structure 32 may be an integral structure, and thus, the first sub-barrier structure 31 and the second sub-barrier structure 32 may be formed simultaneously in the same process step, so as to save process steps and cost.

In order to enable the first sub-barrier structure 31 to completely cover the channel region 111 in the second direction Y, the length of the first sub-barrier structure 31 in the second direction Y may be greater than the length of the channel region 111 in the second direction Y. In addition, in order to enable the second sub barrier structure 32 to completely cover the channel region 111 in the direction Z perpendicular to the plane of the substrate base 01, the length of the second sub barrier structure 32 in the direction Z perpendicular to the plane of the substrate base 01 may be greater than or equal to the length of the channel region 111 in the direction Z perpendicular to the plane of the substrate base 01.

Fig. 2 to 5 are schematic views illustrating a manufacturing process structure of an array substrate according to an embodiment of the present disclosure. The structural views shown in fig. 2 to 5 may be sectional views alongbase:Sub>A-base:Sub>A direction in fig. 1, and the insulating layer 02 in fig. 3 to 5 is not shown in fig. 1.

As shown in fig. 2, a first semiconductor layer 11 may be formed on one side of a base substrate 01. As shown in fig. 3, an insulating layer 02 may be formed on a side of the first semiconductor layer 11 away from the substrate 01, and the insulating layer 02 may cover the first semiconductor layer 11. Illustratively, the insulating layer 02 may be a Gate Insulator (GI). As shown in fig. 4, the insulating layer 02 may be subjected to patterning processing. For example, the insulating layer 02 is etched to obtain a cavity structure penetrating through the insulating layer 02 to accommodate the second sub-barrier structure 32 formed in the subsequent process. Further, as shown in fig. 5, material deposition is performed on a side of the insulating layer 02 facing away from the substrate base 01, and the first sub-barrier structure 31 and the second sub-barrier structure 32 are formed at the same time, that is, the first sub-barrier structure 31 and the second sub-barrier structure 32 are formed as an integral structure.

In some alternative embodiments, in order to enable the first sub-barrier structure 31 and/or the second sub-barrier structure 32 to completely cover the channel region 111 in the first direction X, the length of the first sub-barrier structure 31 and/or the second sub-barrier structure 32 in the first direction X is greater than or equal to the length of the channel region 111 in the first direction X.

Fig. 6 is a schematic perspective view illustrating an array substrate according to another embodiment of the present disclosure. As shown in fig. 6, the array substrate 100 provided in the embodiment of the present invention may further include a second barrier structure 40. The second blocking structure 40 is located on a side of the first semiconductor layer 11 facing away from the first sub-blocking structure 31, and an orthographic projection of the second blocking structure 40 on the first semiconductor layer 11 at least partially overlaps the channel region 111.

Similarly, the second blocking structure 40 can be used to block hydrogen from diffusing into the channel region 111 of the first semiconductor layer 10 and also be used to block light from irradiating the channel region 111 of the first semiconductor layer 10, so as to prevent the short channel effect from occurring in the channel region 111 and prevent the leakage current from occurring in the channel region 111, thereby improving the stability of the first transistor 10.

By providing the second barrier structure 40, the channel region 111 can be protected on the side of the first semiconductor layer 11 away from the first sub-barrier structure 31, so that a larger area of the channel region 111 can be protected.

In some alternative embodiments, with continued reference to fig. 6, the second sub-barrier structure 32 may be disposed in contact with the second barrier structure 40, and the first barrier structure 30 and the second barrier structure 40 together surround the channel region 111. The first barrier structures 30 and the second barrier structures 40 surround the channel region 111, thereby protecting the channel region 111 in all directions.

In order to enable the second sub-barrier structure 32 to completely cover the channel region 111 in the second direction Y, the length of the second barrier structure 40 in the second direction Y may be greater than or equal to the length of the channel region 111 in the second direction Y.

In some alternative embodiments, the second blocking structure 40 may also be multiplexed as the first gate 12. The first sub-blocking structure 31, the second sub-blocking structure 32 and the second blocking structure 40 are multiplexed into the first gate 12 at the same time, so that the area of the first gate 12 is further increased, the control capability of the first gate 12 is enhanced, and the stability of the first transistor 10 can be further improved.

In some alternative embodiments, as shown in fig. 6 and 7, the array substrate 100 further includes a second transistor 20. The second transistor 20 includes a second semiconductor layer 21. The second semiconductor layer 21 includes silicon, and the second transistor 20 is a silicon transistor. For example, the second transistor 20 may be a low temperature polysilicon thin film transistor.

Fig. 7 is a sectional view taken along line B-B in fig. 6. In order to clearly show the first transistor 10 and the second transistor 20, other film layer structures such as the insulating layer, the capacitor structure, and the like in fig. 7 are not shown in fig. 6.

For example, the array substrate 100 may include a pixel circuit. The pixel circuit may include the first transistor 10 and the second transistor 20 in the embodiment of the present application. The first transistor 10 is an oxide transistor, and the oxide transistor has a relatively small leakage current, and can be used as a switching transistor in a pixel circuit to reduce power consumption. The second transistor 20 is a silicon transistor, which has relatively high mobility and can be used as a driving transistor in a pixel circuit.

In order to make the source-drain metal of the second transistor 20 and the second semiconductor layer 21 contact better, the second semiconductor layer 21 needs to be cleaned by hydrofluoric acid, and hydrogen diffuses into the channel region of the first semiconductor layer 11, which may cause a short channel effect in the channel region of the first semiconductor layer 11. With continued reference to fig. 7, the second semiconductor layer 21 may be located on a side of the first semiconductor layer 11 close to the substrate base plate 01. That is, the second semiconductor layer 21 and the second semiconductor layer 11 are provided in different layers, and the influence of the hydrofluoric acid cleaning on the first semiconductor layer 11 is avoided as much as possible.

In some alternative embodiments, with continued reference to fig. 7, the array substrate 100 further includes a capacitor 60. The capacitor 60 includes a first plate 61 and a second plate 62. The second transistor 20 includes a second gate 22. The second gate 22 is multiplexed into the first plate 61 of the capacitor 60. It should be understood that the orthographic projections of the second plate 62 and the second gate 22 on the substrate base 01 overlap. The second plate 62 of the capacitor 60 may be disposed in a different layer than the second barrier structure 40.

In other alternative embodiments, as shown in fig. 8, the second plate 62 of the capacitor 60 may be disposed in the same layer as the second barrier structure 40, and the second plate 62 of the capacitor 60 and the second barrier structure 40 are made of the same material. Thus, the second plate 62 of the capacitor 60 and the second blocking structure 40 can be formed simultaneously in the same process step, thereby saving the process and reducing the cost.

Illustratively, the material of the second plate 62 of the capacitor 60 and the second barrier structure 40 may include molybdenum. Of course, the second plate 62 of the capacitor 60 and the second blocking structure 40 may be formed of other materials, which is not limited in this application.

In some alternative embodiments, with continued reference to fig. 7, the first transistor 10 includes a first source 13 and a first drain 14, and the second transistor 20 includes a second source 23 and a second drain 24. The array substrate 100 may further include a buffer layer 03, a first gate insulating layer 51, a capacitor insulating layer 52, a first interlayer dielectric layer 53, a second gate insulating layer 54, a third gate insulating layer 55, and a second interlayer dielectric layer 56, which are stacked.

The buffer layer 03 is located between the base substrate 01 and the second semiconductor layer 21. The material of the buffer layer 03 may include at least one of silicon nitride and silicon oxide. Through setting up buffer layer 03, can be better prevent that steam, oxygen etc. from invading to second semiconductor layer 21, avoid second semiconductor layer 21 to receive the harm.

The first gate insulating layer 51 is disposed between the second semiconductor layer 21 and the second gate 22, and the first gate insulating layer 51 covers the second semiconductor layer 21. The capacitor insulating layer 52 is located on a side of the second gate 22 away from the substrate base 01, and the capacitor insulating layer 52 covers the second gate 22. The first interlayer dielectric layer 53 is located on the side of the capacitance insulation layer 52 facing away from the substrate base plate 01. The second gate insulating layer 54 is located on a side of the first interlayer dielectric layer 53 facing away from the substrate base 01, and the second semiconductor layer 11 is located on a side of the second gate insulating layer 54 facing away from the substrate base 01. The third gate insulating layer 55 is located between the first semiconductor layer 11 and the first sub-blocking structure 31, and the third gate insulating layer 55 covers the first semiconductor layer 11. The second interlayer dielectric layer 56 is located on a side of the first sub-barrier structure 31 departing from the substrate base plate 01, and the second interlayer dielectric layer 56 covers the first sub-barrier structure 31.

The first source 13, the first drain 14, the second source 23 and the second drain 24 are all located on one side of the second interlayer dielectric layer 56 away from the substrate base plate 01, the first source 13 and the first drain 14 are respectively connected with the source region and the drain region of the first semiconductor layer 11 through the first via hole 15, and the second source 23 and the second drain 24 are respectively connected with the source region and the drain region of the second semiconductor layer 21 through the second via hole 25.

In fig. 7 and 8, in order to clearly show the second sub barrier structure 32, at least a portion of the channel region of the first semiconductor layer 11 is blocked by the second sub barrier structure 32. It is understood that the second sub-blocking structure 32 may penetrate the third gate insulating layer 55. In addition, as described above, the interlayer dielectric layer of the array substrate is a hydrogen-rich film layer, that is, the first interlayer dielectric layer 53 is a hydrogen-rich film layer, the second blocking structure 40 may be disposed between the first interlayer dielectric layer 53 and the first semiconductor layer 11, and specifically, the second blocking structure 40 may be disposed between the first interlayer dielectric layer 53 and the second gate insulating layer 54.

As shown in fig. 7, the second plate 62 of the capacitor 60 and the second blocking structure 40 may be disposed in different layers. Specifically, the second plate 62 of the capacitor 60 may be disposed between the first interlayer dielectric layer 53 and the capacitor insulating layer 52.

In order to save the process, as shown in fig. 8, the second plate 62 of the capacitor 60 and the second blocking structure 40 may be disposed in the same layer. Specifically, the second plate 62 of the capacitor 60 and the second blocking structure 40 are both disposed between the first interlayer dielectric layer 53 and the second gate insulating layer 54.

In some alternative embodiments, as shown in fig. 8, the array substrate 100 further includes a source connection layer 231 and a drain connection layer 241, and the source connection layer 231 and the drain connection layer 241 are located on a side of the third gate insulation layer 55 facing away from the substrate 01. The second via 25 includes a first sub-via 251 and a second sub-via 252, the second source 23 and the second drain 24 are respectively connected to the source connection layer 231 and the drain connection layer 241 through the first sub-via 251, and the source connection layer 231 and the drain connection layer 241 are respectively connected to the source region and the drain region of the second semiconductor layer 21 through the second sub-via 252.

Through the arrangement mode of the two shallow holes of the first sub-via hole 251 and the second sub-via hole 252, the etching difficulty of the via hole can be reduced. In addition, the second sub via hole 252 may be formed at the same time as the receiving cavity for receiving the second sub barrier structure 32, and then the second semiconductor layer 21 may be cleaned by hydrofluoric acid, since the first via hole 15 connecting the first semiconductor layer 11 with the first source electrode 13 and the first drain electrode 14 is not formed at this time, the influence of the hydrofluoric acid cleaning on the first semiconductor layer 11 may be avoided.

For a clear explanation of how to avoid the effect of the hydrofluoric acid cleaning on the first semiconductor layer 11, please refer to fig. 9 to 14. Fig. 9 to 14 are schematic views illustrating a flow structure of a partial film layer of an array substrate according to an embodiment of the present disclosure. The structural diagrams shown in fig. 9 to 14 may be cross-sectional views along the direction B-B in fig. 6, and fig. 6 does not show other film structures such as the insulating layer and the capacitor structure in fig. 9 to 14.

As shown in fig. 9, a metal material may be evaporated on the side of the first interlayer dielectric layer 53 away from the substrate base 01 and patterned to form the second plate 62 of the capacitor 60 and the second barrier structure 40.

As shown in fig. 10, a second gate insulating layer 54 is formed on the second plate 62 and the second barrier structure 40 on the side away from the substrate 01, and the second gate insulating layer 54 covers the second plate 62 and the second barrier structure 40.

As shown in fig. 11, the first semiconductor layer 11 is formed on the side of the second gate insulating layer 54 away from the base substrate 01. As shown in fig. 12, a third gate insulating layer 55 is formed on a side of the first semiconductor layer 11 away from the base substrate 01, and the third gate insulating layer 55 covers the first semiconductor layer 11.

As shown in fig. 13, the second sub via 252 and the receiving cavity 320 receiving the second sub barrier structure 32 are simultaneously formed. It should be understood that the accommodating chamber 320 does not extend through the first semiconductor layer 11, and the third gate insulating layer 55 is spaced between the accommodating chamber 320 and the first semiconductor layer 11. After the second sub via 252 is formed, the second sub via 252 leaks out the source and drain regions of the second semiconductor layer 21, and the source and drain regions of the second semiconductor layer 21 may be subjected to hydrofluoric acid cleaning. Since the first via hole 15 is not formed yet, that is, the first semiconductor layer 11 is not exposed yet, the influence of the hydrofluoric acid cleaning on the first semiconductor layer 11 can be better avoided.

After the hydrofluoric acid cleaning is performed, as shown in fig. 14, a metal material may be deposited while forming the source connection layer 231, the drain connection layer 241, and the first barrier structure 30. Then, the second interlayer dielectric layer 56 of the array substrate may be formed again, and the first sub-via 251 and the first via 15 may be formed at the same time, and the first source electrode 13, the first drain electrode 14, the second source electrode 23, the second drain electrode 24, and the like may be formed at the same time. And will not be described in detail herein.

In some alternative embodiments, as shown in fig. 7 or fig. 8, the array substrate 100 may include a first flat layer 57, a second flat layer 58, and a metal routing layer 70. The first planarization layer 57 is located on a side of the first source electrode 13, the first drain electrode 14, the second source electrode 23, and the second drain electrode 24 facing away from the substrate base plate 01. The metal wiring layer 70 is located on a side of the first planar layer 57 facing away from the substrate base 01. The second planar layer 58 is located on the side of the metal wiring layer 70 facing away from the substrate base 01.

The signal lines of the array substrate 100 may be disposed on the metal wiring layer 70, such as scan signal lines, data signal lines, power signal lines, and the like.

The application also provides a display panel. Fig. 15 illustrates a schematic structural diagram of a display panel according to an embodiment of the present application. As shown in fig. 15, a display panel 1000 provided in an embodiment of the present invention may include an array substrate 100 and a counter substrate 200. The array substrate 100 is the array substrate according to any of the above embodiments. The counter substrate 200 may be a protective cover plate, for example a glass cover plate. The display panel shown in fig. 15 may be an Organic Light-Emitting Diode (OLED) display panel.

It should be understood by those skilled in the art that in other implementations of the present application, the display panel may also be a Micro light emitting diode (Micro LED) display panel, a quantum dot display panel, or the like.

The display panel provided in the embodiments of the present application has the advantages of the array substrate provided in the embodiments of the present application, and specific descriptions of the array substrate in the embodiments above may be specifically referred to, and the details of the embodiments are not repeated herein.

The application also provides a display device which comprises the display panel provided by the application. Referring to fig. 16, fig. 16 is a schematic structural diagram of a display device according to an embodiment of the present application. Fig. 16 provides a display device 2000 including a display panel 1000 according to any of the above embodiments of the present application. The embodiment in fig. 16 is only an example of a mobile phone, and the display device 2000 is described, it should be understood that the display device provided in the embodiment of the present application may be other display devices with a display function, such as a computer, a television, and a vehicle-mounted display device, and the present application is not limited thereto. The display device provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application, and specific reference may be specifically made to the specific description of the display panel in each of the above embodiments, which is not repeated herein.

In accordance with the embodiments of the present application as described above, these embodiments are not exhaustive and do not limit the application to the specific embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the application and its practical application, to thereby enable others skilled in the art to best utilize the application and its various modifications as are suited to the particular use contemplated. The application is limited only by the claims and their full scope and equivalents.

Claims

1. The array substrate is characterized by comprising a substrate base plate and a first transistor positioned on one side of the substrate base plate;

the first transistor comprises a first semiconductor layer, wherein the first semiconductor layer comprises a channel region and a source region and a drain region which are respectively positioned at two sides of the channel region in a first direction;

a first barrier structure comprising a first sub-barrier structure and a second sub-barrier structure;

the first sub-blocking structure is positioned on one side, away from the substrate, of the first semiconductor layer, and at least partially covers the channel region in a direction perpendicular to the plane of the substrate;

the second sub-barrier structure is positioned on at least one side of the channel region in a second direction, wherein the first direction is crossed with the second direction;

the first transistor comprises a first gate, and the first sub-blocking structure and the second sub-blocking structure are multiplexed into the first gate at the same time.

2. The array substrate of claim 1, wherein the first sub-barrier structure and the second sub-barrier structure are a unitary structure.

3. The array substrate of claim 1, wherein the length of the first sub-barrier structure and/or the second sub-barrier structure in the first direction is greater than or equal to the length of the channel region in the first direction.

4. The array substrate of claim 1, further comprising a second blocking structure located on a side of the first semiconductor layer facing away from the first sub-blocking structure, wherein an orthographic projection of the second blocking structure on the first semiconductor layer at least partially overlaps the channel region.

5. The array substrate of claim 4, wherein the second sub-barrier structure is in contact with the second barrier structure, and the first barrier structure and the second barrier structure together surround the channel region.

6. The array substrate of claim 1,

the first barrier structure comprises a non-metallic material, and the non-metallic material comprises at least one of graphite, carbon nano tubes, polypyrrole and polyaniline;

or, the first barrier structure comprises a metal material, and the metal material comprises at least one of titanium, aluminum and molybdenum.

7. The array substrate of claim 4, wherein the first semiconductor layer comprises a metal oxide.

8. The array substrate of claim 7, wherein the array substrate further comprises a second transistor;

the second transistor comprises a second semiconductor layer, the second semiconductor layer comprises silicon, and the second semiconductor layer is located on one side, close to the substrate, of the first semiconductor layer.

9. The array substrate of claim 8, wherein the array substrate comprises a capacitor, the second transistor comprises a second gate,

the second grid electrode is multiplexed as the first polar plate of the capacitor, the second polar plate of the capacitor and the second blocking structure are arranged on the same layer, and the second polar plate of the capacitor and the second blocking structure are made of the same material.

10. The array substrate of claim 9, wherein the first transistor comprises a first source and a first drain, and the second transistor comprises a second source and a second drain;

the array substrate further includes:

a buffer layer between the substrate base plate and the second semiconductor layer;

the first grid electrode insulating layer is positioned between the second semiconductor layer and the second grid electrode, and the first grid electrode insulating layer covers the second semiconductor layer;

the first interlayer dielectric layer is positioned on one side, away from the substrate, of the second grid electrode, and the first interlayer dielectric layer covers the second grid electrode;

the second grid electrode insulating layer is positioned on one side, away from the substrate, of the first interlayer dielectric layer, and the second semiconductor layer is positioned on one side, away from the substrate, of the second grid electrode insulating layer;

a third gate insulating layer located between the first semiconductor layer and the first sub-blocking structure, and covering the first semiconductor layer;

the second interlayer dielectric layer is positioned on one side of the first sub-barrier structure, which is far away from the substrate base plate, and covers the first sub-barrier structure;

the first source electrode, the first drain electrode, the second source electrode and the second drain electrode are all positioned on one side, away from the substrate, of the second interlayer dielectric layer, the first source electrode and the first drain electrode are respectively connected with a source region and a drain region of the first semiconductor layer through first via holes, and the second source electrode and the second drain electrode are respectively connected with a source region and a drain region of the second semiconductor layer through second via holes;

the second electrode plate of the capacitor and the second blocking structure are positioned between the first interlayer dielectric layer and the second grid electrode insulating layer.

11. The array substrate of claim 10, further comprising a source connection layer and a drain connection layer, wherein the source connection layer and the drain connection layer are located on a side of the third gate insulating layer facing away from the substrate, the second via hole comprises a first sub-via hole and a second sub-via hole, the second source and the second drain are respectively connected to the source connection layer and the drain connection layer through the first sub-via hole, and the source connection layer and the drain connection layer are respectively connected to the source region and the drain region of the second semiconductor layer through the second sub-via hole.

12. A display panel comprising the array substrate according to any one of claims 1 to 11.

13. A display device characterized by comprising the display panel according to claim 12.