CN112255455B

CN112255455B - Signal processing method, signal processor, device and storage medium

Info

Publication number: CN112255455B
Application number: CN202011232971.0A
Authority: CN
Inventors: 刘君
Original assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Current assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority date: 2020-11-06
Filing date: 2020-11-06
Publication date: 2024-09-27
Anticipated expiration: 2040-11-06
Also published as: CN112255455A

Abstract

The embodiment of the application discloses a signal processing method, a signal processor, equipment and a storage medium, belonging to the field of signal processing. The method comprises the following steps: acquiring an initial sampling signal; performing maximum signal-to-noise ratio processing on the initial sampling signal to obtain an input signal, wherein the data bit width corresponding to the input signal subjected to the maximum signal-to-noise ratio processing is lower than a data bit width threshold; and performing fast Fourier transform operation on the input signal, and performing maximum signal-to-noise ratio processing in the fast Fourier transform operation process to obtain an output signal, wherein the data bit width of the output signal subjected to the maximum signal-to-noise ratio processing is smaller than a data bit width threshold value. The overflow of the data bit width caused by the continuous increase of the data bit width along with the calculation of each stage can be avoided, so that the occupation of the continuous increase of the data bit width to the processing resource of the signal processor in the FFT realization process is avoided, and the FFT realization cost is further reduced.

Description

Signal processing method, signal processor, device and storage medium

Technical Field

The embodiment of the application relates to the field of signal processing, in particular to a signal processing method, a signal processor, equipment and a storage medium.

Background

The fast fourier transform (Fast Fourier Transformation, FFT) is a fast algorithm of the discrete fourier transform, and the application of the FFT to the field of signal processing can simplify the computation process in the signal processing process, such as fewer multiplication operations.

In the related art, in the FFT implementation process, a fixed bit width is adopted in the processing of each intermediate stage, and a fixed scaling factor is preset in each stage, and since the calculation process of each intermediate stage does not perform any processing, the data bit width can be correspondingly increased, and in order to avoid overflow, a larger data bit width needs to be set to accommodate the processed data, which obviously increases the implementation cost of the FFT.

Disclosure of Invention

The embodiment of the application provides a signal processing method, a signal processor, equipment and a storage medium. The technical scheme is as follows:

In one aspect, an embodiment of the present application provides a signal processing method, where the method includes:

Acquiring an initial sampling signal;

performing maximum signal-to-noise ratio processing on the initial sampling signal to obtain an input signal, wherein the data bit width corresponding to the input signal after the maximum signal-to-noise ratio processing is lower than a data bit width threshold;

And performing fast Fourier transform operation on the input signal, and performing maximum signal-to-noise ratio processing in the fast Fourier transform operation process to obtain an output signal, wherein the data bit width of the output signal subjected to the maximum signal-to-noise ratio processing is smaller than a data bit width threshold value.

On the other hand, the embodiment of the application provides a signal processor, which comprises a sampling unit, a fast Fourier transform operation unit, a first maximum signal-to-noise ratio processing unit and a second maximum signal-to-noise ratio processing unit;

the sampling unit is used for acquiring an initial sampling signal;

The first maximum signal-to-noise ratio processing unit is used for performing maximum signal-to-noise ratio processing on the initial sampling signal to obtain an input signal;

the fast Fourier transform operation unit and the second maximum signal-to-noise ratio processing unit are used for processing the input signal to obtain an output signal.

In another aspect, an embodiment of the present application provides a computer device, where the computer device includes a signal processor and a memory, where at least one instruction, at least one program, a code set, or an instruction set is stored, where the at least one instruction, the at least one program, the code set, or the instruction set is loaded and executed by the signal processor to implement the signal processing method according to the above aspect.

In another aspect, embodiments of the present application provide a computer readable storage medium having stored therein at least one instruction, at least one program, a set of codes, or a set of instructions, which are loaded and executed by a signal processor to implement the signal processing method as described in the above aspect.

In another aspect, according to one aspect of the present application, there is provided a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The signal processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions so that the computer device performs the signal processing methods provided in the various alternative implementations of the above aspects.

The technical scheme provided by the embodiment of the application has the beneficial effects that at least:

In the FFT implementation process, the maximum signal-to-noise ratio processing is carried out on the initial sampling signal, the fixed point loss in the FFT process is reduced, the data bit width is reduced through the maximum signal-to-noise ratio processing in the FFT process, and the overflow of the data bit width caused by the continuous increase of the data bit width along with the continuous increase of each level of calculation can be avoided, so that the occupation of the continuous increase of the data bit width on the processing resource of a signal processor in the FFT implementation process is avoided, and the implementation cost of the FFT is further reduced.

Drawings

FIG. 1 shows an expanded view of a 16-point IFFT transform;

FIG. 2 illustrates a block diagram of a signal processor according to an exemplary embodiment of the present application;

fig. 3 shows a flowchart of a signal processing method according to an exemplary embodiment of the present application;

fig. 4 shows a flow chart of a signal processing method according to another exemplary embodiment of the present application;

fig. 5 shows a flowchart of a signal processing method according to another exemplary embodiment of the present application;

FIG. 6 is a flow chart illustrating a method of maximum SNR processing during butterfly operations in accordance with an exemplary embodiment of the application;

FIG. 7 shows a schematic diagram of a radix operation shown in an exemplary embodiment of the application;

FIG. 8 illustrates a schematic diagram of a phase rotation operation shown in an exemplary embodiment of the present application;

fig. 9 is a block diagram showing a configuration of a signal processor according to an exemplary embodiment of the present application;

fig. 10 is a schematic diagram showing the structure of a computer device according to an exemplary embodiment of the present application.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail with reference to the accompanying drawings.

References herein to "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.

The FFT is a fast algorithm of discrete Fourier transform, and is obtained by improving the algorithm of discrete Fourier transform according to the characteristics of the discrete Fourier transform, such as odd, even, virtual, real and the like, and compared with the discrete Fourier transform, the FFT can save the operation times of complex sequences and the operation amount. In the field of signal processing, when a signal is processed using FFT, the signal may be transformed from the time domain to the frequency domain for further analysis of the characteristics of the signal in the frequency domain. Alternatively, the FFT algorithm includes a time-decimation-based FFT algorithm and a frequency-domain-decimation-based FFT algorithm. As shown in fig. 1, which shows an expanded view of a 16-point IFFT transformation, where, taking time-decimating, radix-2 as an example, X (0) -X (15) are 16 sample signals,And (3) representing the twiddle factors, and obtaining output signals by four-stage butterfly operation of 16 sampling signals, wherein each stage of butterfly operation consists of radix-2 operation and phase twiddle operation.

Because two complex additions and one complex multiplication are needed in each butterfly operation, if the operation data is not processed, the data bit width is gradually increased.

In order to solve the problem that the data bit width will be increased step by step in the related art, the embodiment of the present application provides a new signal processing method, which is applied to the signal processor shown in fig. 2, as shown in fig. 2, which shows a block diagram of the signal processor shown in an exemplary embodiment of the present application, the signal processor 200 includes: a sampling unit 201, a first maximum signal-to-noise ratio processing unit 202, an FFT operation unit 203, and a second maximum signal-to-noise ratio processing unit 204.

The sampling unit 201 is configured to perform analog-to-digital conversion on the analog signal, and sample the analog signal to obtain a plurality of discrete digital signals. In the embodiment of the present application, the sampling unit 201 is configured to obtain an initial sampling signal. Alternatively, the sampling unit 201 may be an Analog-to-Digital Converter (ADC).

The first maximum signal-to-noise ratio processing unit 202 is configured to perform maximum signal-to-noise ratio processing on an input signal. In this embodiment, the first maximum snr processing unit 202 may receive the initial sampling signal transmitted by the sampling unit 201, and perform the maximum snr processing on the initial sampling signal to obtain an input signal for performing the FFT process.

The FFT operation unit 203 is configured to perform a fast fourier transform operation on a plurality of discrete input signals. Wherein the FFT operation unit 203 may include a plurality of radix operators and a phase rotation unit.

The second maximum snr processing unit 204 is configured to perform maximum snr processing on the data during the FFT operation. In the embodiment of the application, in the FFT operation process, the maximum signal-to-noise ratio processing is carried out on each stage of operation, so that the gradual increase of the data bit width caused by complex addition operation and complex multiplication operation in the FFT process is avoided, and the data bit width is controlled within the data bit width threshold.

Optionally, the signal processor 200 further includes a buffer (buffer) for storing the scaling factor of each stage.

Compared with the prior art, only the input signal is subjected to the FFT operation, the first maximum snr processing unit 202 and the second maximum snr processing unit 204 are newly added in the signal processor 200, which can avoid overflow of the data bit width caused by increasing the data bit width with each stage of calculation, thereby avoiding occupation of processing resources of the signal processor caused by increasing the data bit width in the FFT implementation process, and further reducing the implementation cost of the FFT.

It should be noted that the signal processing method shown in the embodiment of the present application may be applied to a signal Processor (in a Processor chip), and the signal Processor may be a digital signal Processor (DIGITAL SIGNAL Processor, DSP) or an Application SPECIFIC INTEGRATED Circuit (ASIC), which is not limited in this embodiment of the present application.

Referring to fig. 3, a flowchart of a signal processing method according to an exemplary embodiment of the application is shown. The embodiment of the application is illustrated by taking the application of the method to a signal processor as an example, and the method comprises the following steps:

in step 301, an initial sampling signal is acquired.

In the field of signal processing, when an analog signal is processed, the analog signal needs to be converted into a digital signal and then processed, so in one possible implementation, the signal processor performs ADC sampling on the received analog signal to obtain the digital signal, that is, an initial sampling signal.

The analog signal may be a radio frequency signal or an electromagnetic wave signal, and the kind of the analog signal in the embodiment of the present application is not limited.

In order to facilitate FFT operation during FFT processing, when ADC sampling is performed on an analog signal, the number of samples obtained by sampling is generally an integer to the power of 2, for example, the number of samples is 16 and 2^4, so that 16 initial sampled signals can be obtained.

Step 302, performing maximum signal-to-noise ratio processing on the initial sampling signal to obtain an input signal, where the data bit width corresponding to the input signal after the maximum signal-to-noise ratio processing is lower than a data bit width threshold.

Defining an initial data bit width as W, wherein the initial data bit width is a sampling bit width corresponding to an initial sampling signal, for example, the initial data bit width (sampling bit width) is 16 bits, and each sampling point is used for collecting 2 bytes of data; the data bit width threshold is determined by the initial data bit width, and the data bit width of each level of operation data in the FFT implementation process is required to be smaller than the data bit width threshold, so that overflow phenomenon caused by the fact that the data bit width exceeds the data bit width threshold is avoided.

In one illustrative example, the relationship between the data bit width threshold and the initial data bit may be expressed as:

max_W＝2^W-1-1

where max_w represents the data bit width threshold and W represents the initial data bit width.

Since the data is processed by FFT localization during the implementation process, in order to avoid FFT localization loss, in one possible implementation, the initial sampling signal is first processed by maximum signal-to-noise ratio, so as to obtain the input signal for performing FFT.

Of course, due to the limitation of the data bit width threshold, the data bit width corresponding to the input signal after the maximum signal-to-noise ratio processing is performed on the initial sampling signal needs to be ensured to be lower than the maximum data bit width, so that overflow is avoided.

Step 303, performing a fast fourier transform operation on the input signal, and performing a maximum signal-to-noise ratio process during the fast fourier transform operation to obtain an output signal, where the data bit width of the output signal after the maximum signal-to-noise ratio process is smaller than the data bit width threshold.

Wherein the maximum signal-to-noise ratio process is used to narrow the data bit width of the signal during the fast fourier transform operation.

In the FFT implementation, the data bit width is increased in the processing of each stage, for example, complex multiplication or complex addition is performed on two signal values, which may result in an increase in the data bit width, so in order to avoid an increase in the data bit width, in the FFT implementation, the signal is processed in a manner of maximum signal-to-noise ratio, so as to avoid an increase in the data bit width of the signal in the FFT operation.

In one possible implementation, the increase in the bit width of the data after complex multiplication is avoided by performing a fast fourier transform on the input signal and performing a maximum signal-to-noise ratio process on the operation data during the FFT operation, e.g., performing a maximum signal-to-noise ratio process after complex multiplication.

In the embodiment of the application, the maximum signal-to-noise ratio processing is carried out on the initial sampling signal, the fixed point loss in the FFT process is reduced, the data bit width is reduced through the maximum signal-to-noise ratio processing in the FFT process, and the overflow of the data bit width caused by the continuous increase of the data bit width along with the calculation of each stage can be avoided, thereby avoiding the occupation of the processing resource of a signal processor caused by the continuous increase of the data bit width in the FFT implementation process, and further reducing the implementation cost of the FFT.

In order to further avoid the increase of the data bit width of each intermediate stage operation, in one possible implementation, the maximum signal-to-noise ratio processing is performed in each stage of butterfly operation, so as to further control the increase of the data bit width in the FFT process.

Referring to fig. 4, a flowchart of a signal processing method according to another exemplary embodiment of the present application is shown. The embodiment of the application is illustrated by taking the application of the method to a signal processor as an example, and the method comprises the following steps:

In step 401, an initial sampling signal is acquired.

The implementation of this step may refer to step 301, and this embodiment is not described herein.

Step 402, calculating an initial scaling factor corresponding to the input signal according to the initial real signal value, the initial imaginary signal value and the initial data bit width, wherein the initial data bit width is a sampling bit width corresponding to the initial sampling signal.

In the step of representing the initial sampling signal, the initial sampling signal is represented as complex number to participate in signal processing operation, for example, the initial signal may be represented as: r _si(n)＝X_si(n)+j·Y_si (n), where R _si (n) is an initial sampling signal, X _si (n) is a real signal value corresponding to the initial sampling signal, Y _si (n) is an imaginary signal value corresponding to the initial sampling signal, and j is an imaginary unit.

Alternatively, the initial sampling signal (I/Q) may share the same exponent, e.g., e, and the initial sampling signal may be expressed as: r _si(n)＝I*2^e+Q*2^e.

In one possible implementation, the principle when performing maximum signal-to-noise ratio processing for each data R _si (n) is: and (3) shifting each data R _si (n) to the left, ensuring that one of the highest bit of the input data (signal) I/Q is not 0, and correspondingly, in the processing process, firstly calculating to obtain an initial scaling factor corresponding to the input signal according to an initial real part signal value, an initial imaginary part signal value and an initial data bit width (sampling bit width) corresponding to the initial sampling signal, and then calculating to obtain the input signal after the maximum signal-to-noise ratio processing according to the initial scaling factor and the initial sampling signal value.

In one illustrative example, the relationship of the scaling factor to the initial sampled signal may be expressed as:

S(n)＝W-2-floor(log2(max(|X_si(n)|,|Y_si(n)|))) (1)

Wherein S (n) is an initial scaling factor corresponding to the initial sampling signal R _si (n), W is an initial data bit width, X _si (n) is an initial real signal value, Y _si (n) is an initial imaginary signal value, floor (X) represents a downward rounding function, that is, taking a maximum integer not greater than X, max (X) represents taking a maximum value, and |x| represents taking an absolute value.

In one possible implementation, the initial scaling factor corresponding to the input signal may be obtained by calculating the initial sampling signal represented in complex form in the manner shown in equation (1).

Because the fixed scaling factor is not adopted in the embodiment of the application, a buffer for storing the scaling factor is arranged, and the size of the buffer is the number of FFT points supported by the signal processor at maximum.

The number of FFT points is the number corresponding to the initial sampling signal, and in order to facilitate FFT operation, the initial sampling signal is usually an integer power of 2, for example, 16 points.

In one possible application scenario, after the initial sampling signal is processed with the maximum signal-to-noise ratio, an initial scaling factor needs to be stored in a buffer, and an input signal is sent to an FFT operation unit for FFT operation.

Step 403, calculating to obtain an input signal according to the initial sampling signal and the initial scaling factor.

In one possible implementation, after determining the initial scaling factor, the input signal after the maximum signal-to-noise ratio processing may be calculated according to the initial sampled signal and the initial scaling factor.

In one illustrative example, the relationship of the input signal, the initial scaling factor, and the initial sampled signal may be expressed as:

R_si′(n)＝R_si(n)·2^-s(n)

where R _si' (n) represents the input signal (i.e., the sampled signal after maximum signal-to-noise processing), R _si (n) represents the initial sampled signal, and s (n) represents the initial scaling factor.

Step 404, performing k-level butterfly operation on the input signal, and performing maximum signal-to-noise ratio processing in each level of butterfly operation process to obtain an output signal, where k is a positive integer and is related to the number of initial sampling signals.

The FFT operation is superposition of all levels of butterfly operations, according to the characteristics of the FFT, the FFT comprises a plurality of levels of butterfly operations related to the number of initial sampling signals and related to an algorithm adopted by the FFT, taking a time-decimated radix-2 algorithm as an example, if the number of the initial sampling signals is 16 (2^4), the FFT comprises 4 levels of butterfly operations, and if the time-decimated radix-4 is taken as an example, the FFT comprises two levels of butterfly operations (4^2).

Because each butterfly operation needs to undergo complex addition twice and complex multiplication once, and the data bit width corresponding to the signal value after the operation is increased in the complex addition process, the data bit width overflow or the situation of larger data bit width can occur, in order to avoid the phenomenon that each butterfly operation causes the data bit width increase, the maximum signal-to-noise ratio processing is performed for each butterfly operation result, the purpose of reducing the data bit width is achieved, and the processing resources allocated when the signal processor processes the signal can be saved on the basis that the data bit width is smaller than the data bit width threshold value (the overflow phenomenon does not occur).

In this embodiment, the loss of FFT localization can be avoided by performing maximum signal-to-noise ratio processing on the initial sampling signal, and in addition, by performing maximum signal-to-noise ratio processing in each stage of butterfly operation in the FFT, the phenomenon of data overflow in the butterfly operation process is avoided, and meanwhile, the increase of the data bit width after each stage of butterfly operation processing is avoided, so that the need of allocating more processing resources due to the increase of the data bit width is avoided, and the implementation cost of the FFT is reduced.

As can be seen from fig. 1, two operation steps of radix (radix) operation and phase rotation operation are required in each stage of butterfly operation, so that when the maximum snr processing is performed in the butterfly operation, the maximum snr processing in the two operation cases needs to be considered, i.e., the maximum snr processing needs to be performed after each operation.

On the basis of fig. 4, as shown in fig. 5, step 404 may include steps 404A to 404D.

In step 404A, radix operation is performed on the n-th input signal, so as to obtain a radix operation result of the n-th stage, where n is a positive integer, and the n-th input signal is an input signal of the n-th stage butterfly operation.

In the process of performing maximum signal-to-noise ratio processing on the butterfly operation, taking into consideration that the butterfly operation comprises radix operation and phase rotation operation, and each operation possibly brings about an increase in data bit width, so that after the radix operation is performed on an input signal, the radix operation result needs to be subjected to maximum signal-to-noise ratio processing, and then the output signal after the maximum signal-to-noise ratio processing is subjected to phase rotation operation; similarly, after the output signal is subjected to the phase rotation operation, the phase rotation operation result may need to be subjected to the maximum signal-to-noise ratio processing, so that the output signal can be used as the input signal of the next butterfly operation.

Since the FFT process includes k stages of butterfly operations, that is, iterative processes of k butterfly operations, in one possible implementation manner, after the signal processor acquires the nth stage input signal, that is, performs radix operation on the nth stage input signal, firstly, an nth stage radix operation result is obtained, and then, maximum signal-to-noise ratio processing is performed on the nth stage radix operation result.

In an exemplary example, taking radix-2, 8-point FFT as an example, the FFT includes 3 stages of butterfly operation, when n takes 1, the first stage input signal (i.e., the signal after the initial sampling signal is subjected to the maximum signal-to-noise ratio processing or the input signal of the first stage butterfly operation) is subjected to radix operation, so as to obtain a first stage radix operation result, and then the first stage radix operation result is subjected to the maximum signal-to-noise ratio processing. When n is 2, the second-stage input signal is the signal obtained by radix operation, maximum signal-to-noise ratio processing, phase rotation operation and maximum signal-to-noise ratio processing of the first-stage input signal, and so on.

And 404B, carrying out maximum signal-to-noise ratio processing on the nth stage radix operation result to obtain an nth stage output signal.

Unlike the related art in which the radix operation result is directly subjected to the phase rotation operation, in order to weaken or counteract the phenomenon of increasing the data bit width in the radix operation process of the signal value, the embodiment of the application firstly needs to perform maximum signal-to-noise ratio processing on the radix operation result after the radix operation result is obtained, reduces the data bit width of the radix operation result, avoids the increase of the data bit width, and can also ensure that the data bit width does not exceed the data bit width threshold value.

Corresponding to step 404A, in the implementation process, after the signal processor obtains the nth radix operation result, the maximum signal-to-noise ratio processing is performed on the nth radix operation result first, so as to obtain an output signal for performing the phase rotation operation, that is, an nth output signal.

In an exemplary example, when n is 1, the first stage input signal is subjected to radix operation, after a first stage radix operation result is obtained, the first stage radix operation result is subjected to maximum signal-to-noise processing, and an output signal obtained after the maximum signal-to-noise processing is used as a first stage output signal.

Step 404C, performing a phase rotation operation on the nth stage output signal to obtain an nth stage phase rotation operation result.

In each stage of butterfly operation, radix operation is performed first and then phase rotation operation is performed, so in one possible implementation manner, the signal processor inputs the nth stage output signal processed by butterfly operation and maximum signal to noise ratio into the phase rotation operation unit to perform phase rotation operation, firstly obtains the nth stage phase rotation operation result, and then performs maximum signal to noise ratio processing on the nth stage phase rotation operation result.

Step 404D, performing maximum signal-to-noise ratio processing on the nth stage phase rotation operation result to obtain an n+1th stage input signal, where the input signal obtained after performing maximum signal-to-noise ratio processing on the kth stage phase rotation operation result is determined as the output signal.

Similarly to the radix operation process described above, after performing radix operation and maximum snr processing on the input signal, the obtained output signal is input to the phase rotation operation unit, and the data bit width of the processed signal value may be increased due to complex multiplication in the phase rotation operation, so in one possible implementation, the maximum snr processing is required on the phase rotation operation result, and the subsequent butterfly operation can be performed after the data bit width is reduced.

In the FFT process, after the signal processor acquires the nth stage phase rotation operation result, the signal processor firstly needs to perform maximum signal-to-noise ratio processing to avoid the increase of the data bit width, and then performs the next stage butterfly operation after the maximum signal-to-noise ratio processing.

In one illustrative example, the operation of the nth stage butterfly operation includes: performing radix operation on the n-th input signal to obtain a radix operation result, performing maximum signal-to-noise ratio processing on the radix operation result to obtain an n-th output signal, performing phase rotation operation on the n-th output signal to obtain an n-th phase rotation operation result, and performing maximum signal-to-noise ratio processing on the n-th phase rotation operation result to obtain an n+1-th input signal, wherein the n+1-th input signal is used for performing an n+1-th butterfly operation, and the n+1-th butterfly operation process is similar to the n-th butterfly operation process, and the embodiment is not described herein.

When the nth value is equal to k, that is, the FFT is performed to the final stage (k stage) butterfly operation, the input signal obtained after radix operation-maximum signal-to-noise ratio processing-phase rotation operation-maximum signal-to-noise ratio processing is determined as the output signal of the FFT.

In this embodiment, since the radix operation and the phase rotation operation are included in each butterfly operation, and both operations may cause an increase in the data bit width, and a situation that the data bit width exceeds the data bit width threshold may also occur, in each butterfly operation, the maximum signal-to-noise ratio processing step is added after the radix operation and the phase rotation operation, so that the increase in the data bit width is prevented more accurately, and overflow of the data bit width is avoided.

The above embodiment describes the action position of the maximum snr processing in the FFT implementation process, that is, the maximum snr processing is required for each stage of butterfly operation, and the maximum snr processing is also required for the radix operation and the phase rotation operation included in each stage of butterfly operation, and the following embodiment focuses on the detailed process of performing the maximum snr processing in each operation process.

Referring to fig. 6, a flowchart of a method for performing maximum snr processing in a butterfly operation process according to an exemplary embodiment of the present application is shown, where the method is applied to a signal processor as an example, and the method includes:

step 601, performing radix operation on the first input signal and the second input signal to obtain a first radix operation result and a second radix operation result.

As can be seen from fig. 1, in each butterfly operation, the input of the butterfly operation includes two signals, namely, the first input signal and the second input signal, and the output is also two signals, namely, the first output signal and the second output signal, so in one possible implementation, when the radix operation is performed on the n-th input signal, the radix operation is performed on the first input signal and the second input signal corresponding to the n-th input signal, and correspondingly, after the radix operation, two radix operation results, namely, the first radix operation result and the second radix operation result, are also obtained.

Wherein, the process of performing radix operation on the first output signal and the second output signal can comprise the following steps:

1. a first scaling factor corresponding to the first input signal and a second scaling factor corresponding to the second input signal are obtained.

In one possible implementation manner, in the radix operation process, the scaling factor corresponding to each stage of input signal needs to be considered, because the scaling factor is dynamically changed and stored in the buffer, when the radix operation is performed on the n-th stage of input signal, the first scaling factor and the second scaling factor corresponding to the first input signal and the second input signal (the n-th stage of input signal) respectively need to be acquired from the buffer for performing the radix operation.

The scaling factor corresponding to the n-th level input signal is the updated scaling factor obtained after the maximum signal-to-noise ratio processing is performed after the n-1-th level butterfly operation is performed, and the updated scaling factor is stored in a buffer.

2. And calculating to obtain a first radix operation result and a second radix operation result according to the first input signal, the second input signal, the first scaling factor and the second scaling factor.

Compared with the prior art, each stage of butterfly operation adopts a fixed scaling factor, and the scaling factor is not involved in the corresponding radix operation process, but in the embodiment of the application, because each stage of scaling factor is updated, the scaling factor is used as an index in the radix operation process, and the radix operation is carried out together with the first input signal and the second input signal.

In an exemplary example, taking the first radix operation result as an example, the radix calculation formula may be expressed as:

r′_sj+1(m)＝r_sj(m)·2^s(m)+r_sj(n)·2^s(n)

Wherein r' _sj+1 (m) represents a first radix operation result, r _sj (m) represents a first input signal, r _sj (n) represents a second input signal, s (m) represents a first scaling factor corresponding to the first input signal, and s (n) represents a second scaling factor corresponding to the second input signal.

Because of the decreasing and decreasing features of the butterfly operation, the second radix operation result may be expressed as:

r′_sj+1(n)＝r_sj(m)·2^s(m)-r_sj(n)·2^s(n)

Wherein r' _sj+1 (n) represents the second radix operation result.

Step 602, performing maximum signal-to-noise ratio processing on the first radix operation result to obtain a first output signal.

Since two operation results, namely, the first radix operation result and the second radix operation result, can be obtained after radix operation, in the process of performing maximum signal-to-noise ratio processing on the radix operation result, the two radix operation results also need to be respectively subjected to maximum signal-to-noise ratio processing, and in a possible implementation manner, the signal processor performs maximum signal-to-noise ratio processing on the first radix operation result, so that a first output signal corresponding to the nth output signal can be obtained for performing phase rotation operation subsequently.

The process of performing maximum signal-to-noise ratio processing on the first radix operation result may include the following steps:

1. And acquiring a first real part signal value corresponding to the first radix operation result, a first imaginary part signal value and a data bit width corresponding to the first radix operation result.

Since the data bit width corresponding to the radix operation result needs to be paid attention to in real time in the process of performing the maximum signal-to-noise ratio processing, and the updated scaling factor is related to the radix operation result, in one possible implementation, when the maximum signal-to-noise ratio processing is performed on the first radix operation result, the first real part signal value and the first imaginary part signal value corresponding to the first radix operation result need to be acquired first, so as to be used for calculating the updated scaling factor.

Since the update scaling factor is related to the current data bit width of the first radix operation result, for example, if the data bit width of the first radix operation result is larger, the corresponding scaling factor is larger, and therefore, when calculating the scaling factor, the data bit width corresponding to the first radix operation result also needs to be obtained.

In one possible implementation, after the signal processor obtains the first radix operation result, the signal processor needs to obtain a first real part signal value, a second imaginary part signal value and a corresponding data bit width corresponding to the first radix operation result.

2. And calculating a scaling factor corresponding to the first output signal according to the first real part signal value, the first imaginary part signal value and the data bit width corresponding to the first radix operation result.

In one possible implementation manner, after the first real part signal value, the first imaginary part signal value and the data bit width (the first radix operation result) corresponding to the first radix operation result are obtained, the scaling factor corresponding to the first output signal can be calculated according to the scaling factor formula, so as to achieve the purpose of updating the scaling factor.

In an exemplary example, taking the first output signal as an example, the calculation formula of the scaling factor may be expressed as:

s′(m)＝W-2-floor(log2(max(|X_sj(m)|,|Y_sj(m)|))) (2)

Where s' (m) is a scaling factor corresponding to the first output signal (i.e., an updated scaling factor in the maximum signal-to-noise ratio processing), W is a data bit width corresponding to the first radix operation result, X _sj (m) represents a first real part signal value corresponding to the first radix operation result, and Y _sj (m) represents a first imaginary part signal value corresponding to the first radix operation result.

3. And calculating to obtain a first output signal according to a scaling factor corresponding to the first output signal and a first radix operation result.

In a possible implementation, the updated scaling factor is used as an exponent for calculating the first output signal according to the first radix operation result and the updated scaling factor.

In one illustrative example, the relationship between the first output signal and the first radix operation result may be expressed as:

r_sj+1(m)＝r′_sj+1(m)·2^-s′(m) (3)

where r _sj+1 (m) represents the first output signal, r '_sj+1 (m) represents the first radix operation result, and s' (m) represents the updated scaling factor (i.e., the scaling factor corresponding to the first output signal).

And 603, performing maximum signal-to-noise ratio processing on the second radix operation result to obtain a second output signal.

Similarly to the maximum signal-to-noise ratio processing of the radix operation result, after the signal processor obtains the second radix operation result, the signal processor does not directly perform the phase rotation operation on the second radix operation result, but performs the maximum signal-to-noise ratio processing on the second radix operation result first, so as to reduce the data bit width increased in the radix operation process, obtain the second output signal after the maximum signal-to-noise ratio processing, and further ensure that the data bit width of the second output signal is lower than the data bit width threshold.

The method for performing the maximum signal-to-noise ratio processing on the second radix operation result may include the following steps:

1. And acquiring a second real part signal value corresponding to the second radix operation result, a second imaginary part signal value and a data bit width corresponding to the second radix operation result.

Similarly to the above maximum signal-to-noise ratio processing of the first radix operation result, in the maximum signal-to-noise ratio processing of the second radix operation result, the second real part signal value, the second imaginary part signal value, and the corresponding data bit width corresponding to the second radix operation result need to be acquired for updating the scaling factor.

2. And calculating a scaling factor corresponding to the second output signal according to the second real part signal value, the second imaginary part signal value and the data bit width corresponding to the second radix operation result.

In one possible implementation manner, after the second real part signal value, the second imaginary part signal value and the data bit width corresponding to the second radix operation result are obtained, the scaling factor corresponding to the second output signal can be obtained by calculation according to the formula of the scaling factor, so as to achieve the purpose of updating the scaling factor.

In an exemplary example, the calculation formula of the scaling factor corresponding to the second output signal may be:

s′(n)＝W-2-floor(log2(max(|X_sj(n)|,|Y_sj(n)|)))

Where s' (n) represents a scaling factor corresponding to the second output signal (i.e., an updated scaling factor in the maximum signal-to-noise ratio processing), W represents a data bit width corresponding to the second radix operation result, X _sj (n) represents a second real part signal value corresponding to the second radix operation result, and Y _sj (n) represents a second imaginary part signal value corresponding to the second radix operation result.

3. And calculating to obtain a second output signal according to a scaling factor corresponding to the second output signal and a second radix operation result.

In a possible implementation manner, the updated scaling factor is used as an index to calculate the second output signal after the maximum signal-to-noise ratio processing according to the second radix operation result and the updated scaling factor.

In an illustrative example, the relationship between the second output signal and the second radix operation result may be expressed as:

r_sj+1(n)＝r′_sj+1(n)·2^-s′(n)

Where r _sj+1 (n) represents the second output signal, r '_sj+1 (n) represents the second radix operation result, and s' (n) represents the updated scaling factor (i.e., the scaling factor corresponding to the second output signal).

In one illustrative example, as shown in fig. 7, a schematic diagram of radix operation is shown in accordance with an exemplary embodiment of the present application. Let j denote the j-th butterfly operation, where r _sj (m) denotes the first input signal corresponding to the j-th input signal, r _sj (n) denotes the second input signal corresponding to the j-th input signal, s (m) denotes the first scaling factor corresponding to the first output signal, s (n) denotes the second scaling factor corresponding to the second output signal, r _sj+1 (m) denotes the first output signal corresponding to the j-th output signal, r _sj+1 (n) denotes the second output signal corresponding to the j-th output signal, s '(m) denotes the scaling factor corresponding to the first output signal (scaling factor updated during maximum signal-to-noise ratio processing), and s' (n) denotes the scaling factor corresponding to the second output signal (scaling factor updated during maximum signal-to-noise ratio processing). Wherein the process from r _sj(m)、r_sj (n) to r _sj+1(m)、r_sj+1 (n) can be referred to the above embodiments.

Step 604, performing a phase rotation operation on the first output signal to obtain a first phase rotation operation result.

The first output signal is a signal obtained by processing a first radix operation result through the maximum signal-to-noise ratio.

For the phase rotation operation process, there are two cases, one is that complex multiplication operation is not needed, and the other is that complex multiplication operation is needed, wherein the increase of the data bit width is possibly brought after the complex multiplication operation, so that the maximum signal-to-noise ratio processing is needed after the phase rotation operation unit, and in addition, the maximum signal-to-noise ratio processing is not needed for the case that complex multiplication operation is not needed, the maximum signal-to-noise ratio processing is also needed, and the data bit width can be further reduced.

In an exemplary example, for a phase rotation unit that needs to perform complex multiplication, a calculation formula of a phase rotation operation result may be expressed as:

Where r' _sj+1 (m) represents the first phase rotation operation result, r _sj (m) is the first output signal (i.e., the first radix operation result processed by the maximum signal-to-noise ratio), As a twiddle factor in the FFT,

Step 605, performing a phase rotation operation on the second output signal to obtain a second phase rotation operation result.

The second output signal is a signal obtained by performing maximum signal-to-noise ratio processing on the second radix operation result.

The calculation manner of the second phase rotation operation result may refer to the first phase rotation operation result, and this embodiment is not described herein.

Step 606, performing maximum signal-to-noise ratio processing on the first phase rotation operation result to obtain a first input signal corresponding to the n+1st input signal.

Similar to radix operation, unlike the related art, in which the phase rotation operation result is directly used as the input signal of the next butterfly operation, in order to avoid the increase of the data bit width, the embodiment of the application needs to perform maximum signal-to-noise ratio processing on the phase rotation operation result.

In one possible implementation manner, after the signal processor obtains the first phase rotation operation result, the first phase rotation operation result is subjected to maximum signal-to-noise ratio processing to obtain a first input signal of the next butterfly operation, i.e. a first input signal in the n+1st input signal.

In one possible implementation, the process of performing the maximum signal-to-noise ratio processing on the first phase rotation operation result may include the following steps:

1. And acquiring a third real part signal value, a third imaginary part signal value and a data bit width corresponding to the first phase rotation operation result.

Similarly to the maximum snr processing of the radix operation result, when the maximum snr processing of the phase rotation operation result is performed, the real part signal value and the imaginary part signal value corresponding to the first phase rotation operation result and the data bit width are also required to be obtained, so as to update the scaling factor, that is, obtain the third real part signal value, the third imaginary part signal value and the corresponding data bit width corresponding to the first phase rotation operation result.

2. And according to the third real part signal value, the third imaginary part signal value and the data bit width corresponding to the first phase rotation operation result, calculating to obtain a first scaling factor corresponding to the first input signal in the n+1 level input signal.

In the butterfly operation process, the data bit width of each stage is dynamically changed, and the data bit widths of different stages may be different, but the data bit widths of each stage need to be ensured to be lower than the data bit width threshold value.

In one possible implementation manner, the third real part signal value, the third imaginary part signal value and the data bit width corresponding to the first phase rotation operation result are input into a preset scaling factor calculation formula, and a scaling factor corresponding to the first input signal in the n+1th level input signal can be calculated, that is, the scaling factor updated after the maximum signal-to-noise ratio processing is performed on the first phase rotation operation result is obtained.

The formula (2) in the above embodiment may be referred to for the calculation formula of the scaling factor, which is not described herein.

3. And according to a first scaling factor and a first phase rotation operation result corresponding to the first input signal in the n+1th stage input signal, calculating to obtain the first input signal corresponding to the n+1th stage input signal.

In one possible implementation manner, when the maximum signal-to-noise ratio processing is performed on the first phase rotation operation result, the updated scaling factor is used as an index, and the scaling factor is operated with the first phase rotation operation result, so that a signal after the maximum signal-to-noise ratio processing, namely, a first input signal corresponding to the n+1st input signal is obtained.

The formula for calculating the first output signal according to the first phase rotation operation result may refer to the formula (3) in the above embodiment, which is not described herein.

In step 607, the maximum snr processing is performed on the second phase rotation result, so as to obtain a second input signal corresponding to the n+1st input signal.

Similar to the maximum snr processing performed on the first phase rotation operation result in the above embodiment, after the signal processor obtains the second phase rotation operation result, the maximum snr processing is further performed on the second phase rotation operation result, and then the second phase rotation operation result is used for the input of the subsequent n+1st butterfly operation.

The method for performing the maximum signal-to-noise ratio processing on the second phase rotation operation result may include the following steps:

1. and acquiring a fourth real part signal value, a fourth imaginary part signal value and a data bit width corresponding to the second phase rotation operation result.

Since the updating of the scaling factor is involved in the maximum snr processing of the second phase rotation result, and the updating of the scaling factor requires participation of the signal value and the data bit width, in one possible implementation, the fourth real part signal value, the fourth imaginary part signal value and the corresponding data bit width corresponding to the second phase rotation result need to be obtained in the maximum snr processing of the second phase rotation result and used for calculating the updated scaling factor.

2. And calculating a second scaling factor corresponding to a second input signal in the n+1th level input signal according to the fourth real part signal value, the fourth imaginary part signal value and the data bit width corresponding to the second phase rotation operation result.

In one possible implementation, after the signal processor obtains the fourth real part signal value, the fourth imaginary part signal value and the data bit width corresponding to the second phase rotation operation result, the three data may be brought into a preset scaling factor formula, so as to calculate an updated scaling factor, that is, a second scaling factor corresponding to the second input signal in the n+1th level input signal.

The formula of calculating the scaling factor according to the real signal value, the imaginary signal value and the data bit width can refer to the above embodiment, and the description of this embodiment is omitted here.

3. And according to a second scaling factor and a second phase rotation operation result corresponding to the second input signal in the n+1th stage input signal, calculating to obtain the second input signal corresponding to the n+1th stage input signal.

In one possible implementation manner, after the updated scaling factor is obtained, the second input signal corresponding to the n+1st stage input signal may be calculated according to the scaling factor and the second phase rotation operation result.

The formulas for calculating the signal values according to the phase rotation operation result and the scaling factor can refer to the above embodiments, and the description of the embodiments is omitted herein.

In one illustrative example, as shown in fig. 8, a schematic diagram of a phase rotation operation is shown in accordance with an exemplary embodiment of the present application. Wherein r _sj (m) represents a first output signal (i.e., a signal input to the phase rotation operation unit) in the j-th butterfly operation, s (m) represents a scaling factor corresponding to the first output signal, r _sj+1 (m) represents a first output signal obtained by performing phase rotation operation and maximum signal-to-noise ratio processing on r _sj (m), s' (m) represents a scaling factor corresponding to the first output signal,The rotation factor is represented, and the maximum signal-to-noise ratio processing is performed after the phase rotation operation, which involves updating the scaling factor, i.e., the scaling factor is updated from s (m) to s' (m).

In this embodiment, a process of performing maximum signal-to-noise ratio processing during radix operation and phase rotation operation is described, and compared with the related art, by performing maximum signal-to-noise ratio processing on a radix operation result, an increase in data bit width during radix operation can be avoided, and simultaneously performing maximum signal-to-noise ratio processing on a phase rotation operation result, an increase in data bit width during phase rotation operation can be avoided, so that occupation of processing resources of a signal processor by an increase in data bit width during FFT implementation is avoided, and further implementation cost of FFT is reduced.

It should be noted that, the embodiment of the present application is only exemplified by FFT, and in other possible implementations, various signal processing methods provided by the embodiment of the present application are also applicable in the IFFT process.

Referring to fig. 9, a block diagram of a signal processor according to an exemplary embodiment of the present application is shown. The signal processor 900 comprises a sampling unit 901, a first maximum signal-to-noise ratio processing unit 902, a fast fourier transform operation unit 903 and a second maximum signal-to-noise ratio processing unit 904.

The sampling unit 901 is used for obtaining an initial sampling signal;

the first maximum snr processing unit 902 is configured to perform maximum snr processing on the initial sampled signal, to obtain an input signal;

the fast fourier transform operation unit 903 and the second maximum signal-to-noise ratio processing unit 904 are configured to process the input signal to obtain an output signal.

Optionally, the fast fourier transform operation includes a k-stage butterfly operation, where k is a positive integer and is related to the number of the initial sampled signals;

the fast fourier transform operation unit 903 and the second maximum signal to noise ratio processing unit 904 are further configured to:

And carrying out k-level butterfly operation on the input signal, and carrying out maximum signal-to-noise ratio processing in the butterfly operation process of each level to obtain the output signal.

Optionally, the butterfly operation includes a radix operation and a phase rotation operation;

Performing radix operation on an nth stage input signal to obtain an nth stage radix operation result, wherein n is a positive integer, and the nth stage input signal is an nth stage butterfly operation input signal;

carrying out maximum signal-to-noise ratio processing on the nth stage radix operation result to obtain an nth stage output signal;

performing phase rotation operation on the nth stage output signal to obtain an nth stage phase rotation operation result;

And carrying out maximum signal-to-noise ratio processing on the nth stage phase rotation operation result to obtain an n+1th stage input signal, wherein the input signal obtained after carrying out maximum signal-to-noise ratio processing on the kth stage phase rotation operation result is determined to be the output signal.

Performing radix operation on the first input signal and the second input signal to obtain a first radix operation result and a second radix operation result;

performing maximum signal-to-noise ratio processing on the first radix operation result to obtain the first output signal;

Performing maximum signal-to-noise ratio processing on the second radix operation result to obtain the second output signal;

performing phase rotation operation on the first output signal to obtain a first phase rotation operation result;

Performing phase rotation operation on the second output signal to obtain a second phase rotation operation result;

Performing maximum signal-to-noise ratio processing on the first phase rotation operation result to obtain a first input signal corresponding to the n+1st input signal;

And carrying out maximum signal-to-noise ratio processing on the second phase rotation operation result to obtain a second input signal corresponding to the n+1st input signal.

Optionally, the fast fourier transform operation unit 903 is further configured to:

acquiring a first scaling factor corresponding to the first input signal and a second scaling factor corresponding to the second input signal;

And calculating to obtain the first radix operation result and the second radix operation result according to the first input signal, the second input signal, the first scaling factor and the second scaling factor.

Optionally, the second maximum signal to noise ratio processing unit 904 is further configured to:

Acquiring a first real part signal value, a first imaginary part signal value and a data bit width corresponding to the first radix operation result;

According to the first real part signal value, the first imaginary part signal value and the first radix operation result, calculating a scaling factor corresponding to the first output signal;

Calculating to obtain the first output signal according to a scaling factor corresponding to the first output signal and the first radix operation result;

acquiring a second real part signal value, a second imaginary part signal value and a data bit width corresponding to the second radix operation result;

Calculating a scaling factor corresponding to the second output signal according to the second real part signal value, the second imaginary part signal value and the data bit width corresponding to the second radix operation result;

And calculating to obtain the second output signal according to the scaling factor corresponding to the second output signal and the second radix operation result.

Acquiring a third real part signal value and a third imaginary part signal value corresponding to the first phase rotation operation result and a data bit width corresponding to the first phase rotation operation result;

According to the third real part signal value, the third imaginary part signal value and the data bit width corresponding to the first phase rotation operation result, calculating to obtain a first scaling factor corresponding to a first input signal in the n+1st-stage input signal;

And calculating the first input signal corresponding to the n+1th stage input signal according to a first scaling factor corresponding to the first input signal in the n+1th stage input signal and the first phase rotation operation result.

acquiring a fourth real part signal value, a fourth imaginary part signal value and a data bit width corresponding to the second phase rotation operation result;

According to the fourth real part signal value, the fourth imaginary part signal value and the data bit width corresponding to the second phase rotation operation result, calculating to obtain a second scaling factor corresponding to a second input signal in the n+1th level input signal;

And calculating the second input signal corresponding to the n+1th stage input signal according to a second scaling factor corresponding to the second input signal in the n+1th stage input signal and the second phase rotation operation result.

Optionally, the first maximum signal to noise ratio processing unit 902 is further configured to:

calculating an initial scaling factor corresponding to the input signal according to the initial real part signal value, the initial imaginary part signal value and an initial data bit width, wherein the initial data bit width is a sampling bit width corresponding to the initial sampling signal;

And calculating the input signal according to the initial sampling signal and the initial scaling factor.

In the embodiment of the application, in the FFT implementation process, the maximum signal-to-noise ratio processing is carried out on the initial sampling signal, the fixed point loss in the FFT process is reduced, the data bit width is reduced through the maximum signal-to-noise ratio processing in the FFT process, and the overflow of the data bit width caused by the continuous increase of the data bit width along with the continuous increase of each stage of calculation can be avoided, thereby avoiding the occupation of the continuous increase of the data bit width on the processing resources of a signal processor in the FFT implementation process, and further reducing the implementation cost of the FFT.

Referring to fig. 10, a schematic structural diagram of a computer device according to an exemplary embodiment of the present application is shown.

The computer device 1000 comprises a signal processor 1001 and a memory 1002. The signal processor 1001 may be a DSP or an ASIC, and the embodiment of the present application is not limited thereto, and may be used to implement the signal processing method as shown in the above embodiments when the signal processor 1001 is operated.

Embodiments of the present application also provide a computer readable storage medium storing at least one instruction that is loaded and executed by the processor to implement the signal processing method described in the above embodiments.

Embodiments of the present application also provide a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The signal processor of the computer device reads the computer instructions from the computer-readable storage medium, and the processor executes the computer instructions so that the computer device performs the signal processing methods provided in the various alternative implementations of the above aspects.

Those skilled in the art will appreciate that in one or more of the examples described above, the functions described in the embodiments of the present application may be implemented in hardware, software, firmware, or any combination thereof. When implemented in software, these functions may be stored on or transmitted over as one or more instructions or code on a computer-readable storage medium. Computer-readable storage media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.

The foregoing description of the preferred embodiments of the present application is not intended to limit the application, but rather, the application is to be construed as limited to the appended claims.

Claims

1. A method of signal processing, the method comprising:

Acquiring an initial sampling signal;

Performing radix operation on an nth stage input signal to obtain an nth stage radix operation result, wherein n is a positive integer, and the nth stage input signal is an nth stage butterfly operation input signal; carrying out maximum signal-to-noise ratio processing on the nth stage radix operation result to obtain an nth stage output signal; wherein the nth stage input signal comprises a first input signal and a second input signal, and the nth stage output signal comprises a first output signal and a second output signal;

performing phase rotation operation on the first output signal to obtain a first phase rotation operation result; performing phase rotation operation on the second output signal to obtain a second phase rotation operation result;

acquiring a third real part signal value, a third imaginary part signal value and a data bit width corresponding to the first phase rotation operation result; according to the third real part signal value, the third imaginary part signal value and the data bit width corresponding to the first phase rotation operation result, calculating to obtain a first scaling factor corresponding to a first input signal in the n+1st-stage input signal; according to a first scaling factor corresponding to a first input signal in the n+1th-stage input signal and the first phase rotation operation result, calculating to obtain the first input signal corresponding to the n+1th-stage input signal;

Acquiring a fourth real part signal value, a fourth imaginary part signal value and a data bit width corresponding to the second phase rotation operation result; according to the fourth real part signal value, the fourth imaginary part signal value and the data bit width corresponding to the second phase rotation operation result, calculating to obtain a second scaling factor corresponding to a second input signal in the n+1th level input signal; and calculating to obtain a second input signal corresponding to the n+1th level input signal according to a second scaling factor corresponding to the second input signal in the n+1th level input signal and the second phase rotation operation result, wherein n is more than 0 and less than or equal to k, k is a positive integer, the number of the initial sampling signals is related, an input signal obtained after the maximum signal-to-noise ratio processing of the k level phase rotation operation result is determined to be an output signal, and the data bit width of the output signal after the maximum signal-to-noise ratio processing is smaller than the data bit width threshold.

2. The method of claim 1, wherein the step of determining the position of the substrate comprises,

The radix operation is performed on the n-th input signal to obtain an n-th radix operation result, which comprises the following steps:

The maximum signal-to-noise ratio processing is carried out on the nth stage radix operation result to obtain an nth stage output signal, which comprises the following steps:

And carrying out maximum signal-to-noise ratio processing on the second radix operation result to obtain the second output signal.

3. The method according to claim 2, wherein performing radix operation on the first input signal and the second input signal to obtain a first radix operation result and a second radix operation result includes:

4. A method according to claim 3, wherein said performing maximum signal-to-noise ratio processing on said first radix operation result to obtain said first output signal comprises:

According to the first real part signal value, the first imaginary part signal value and the data bit width corresponding to the first radix operation result, calculating to obtain a scaling factor corresponding to the first output signal;

And performing maximum signal-to-noise ratio processing on the second radix operation result to obtain the second output signal, including:

5. The method according to any of claims 1 to 4, wherein the initial sampled signal consists of initial real signal values and initial imaginary signal values;

The maximum signal-to-noise ratio processing is performed on the initial sampling signal to obtain an input signal, which comprises the following steps:

6. The signal processor is characterized by comprising a sampling unit, a fast Fourier transform operation unit, a first maximum signal-to-noise ratio processing unit and a second maximum signal-to-noise ratio processing unit;

the sampling unit is used for acquiring an initial sampling signal;

The fast Fourier transform operation unit and the second maximum signal-to-noise ratio processing unit are used for carrying out radix operation on an nth stage input signal to obtain an nth stage radix operation result, n is a positive integer, and the nth stage input signal is an input signal of an nth stage butterfly operation; carrying out maximum signal-to-noise ratio processing on the nth stage radix operation result to obtain an nth stage output signal; wherein the nth stage input signal comprises a first input signal and a second input signal, and the nth stage output signal comprises a first output signal and a second output signal; performing phase rotation operation on the first output signal to obtain a first phase rotation operation result; performing phase rotation operation on the second output signal to obtain a second phase rotation operation result; acquiring a third real part signal value, a third imaginary part signal value and a data bit width corresponding to the first phase rotation operation result; according to the third real part signal value, the third imaginary part signal value and the data bit width corresponding to the first phase rotation operation result, calculating to obtain a first scaling factor corresponding to a first input signal in the n+1st-stage input signal; according to a first scaling factor corresponding to a first input signal in the n+1th-stage input signal and the first phase rotation operation result, calculating to obtain the first input signal corresponding to the n+1th-stage input signal; acquiring a fourth real part signal value, a fourth imaginary part signal value and a data bit width corresponding to the second phase rotation operation result; according to the fourth real part signal value, the fourth imaginary part signal value and the data bit width corresponding to the second phase rotation operation result, calculating to obtain a second scaling factor corresponding to a second input signal in the n+1th level input signal; and calculating to obtain a second input signal corresponding to the n+1th level input signal according to a second scaling factor corresponding to the second input signal in the n+1th level input signal and the second phase rotation operation result, wherein n is more than 0 and less than or equal to k, k is a positive integer, the number of the initial sampling signals is related, an input signal obtained after the maximum signal-to-noise ratio processing of the k level phase rotation operation result is determined to be an output signal, and the data bit width of the output signal after the maximum signal-to-noise ratio processing is smaller than the data bit width threshold.

7. A computer device, characterized in that it comprises a signal processor and a memory in which at least one instruction, at least one program, code set or instruction set is stored, said at least one instruction, said at least one program, said code set or instruction set being loaded and executed by said signal processor to implement the signal processing method according to any of claims 1 to 5.

8. A computer readable storage medium having stored therein at least one instruction, at least one program, a set of codes, or a set of instructions, the at least one instruction, the at least one program, the set of codes, or the set of instructions being loaded and executed by a signal processor to implement the signal processing method of any one of claims 1 to 5.