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CN112187229B - High-precision pulse width modulation system and method - Google Patents

High-precision pulse width modulation system and method Download PDF

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Publication number
CN112187229B
CN112187229B CN202011166022.7A CN202011166022A CN112187229B CN 112187229 B CN112187229 B CN 112187229B CN 202011166022 A CN202011166022 A CN 202011166022A CN 112187229 B CN112187229 B CN 112187229B
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signal
delay
phase
signals
pwm
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CN112187229A (en
Inventor
冯珅
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Sino Wealth Microelectronics Co ltd
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Sino Wealth Microelectronics Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K7/00—Modulating pulses with a continuously-variable modulating signal
    • H03K7/08—Duration or width modulation ; Duty cycle modulation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/083—Details of the phase-locked loop the reference signal being additionally directly applied to the generator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H03L7/0998—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator using phase interpolation

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  • Pulse Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

The invention provides a high-precision pulse width modulation system and a high-precision pulse width modulation method. The multi-phase delay locking loop system generates M main phase signals Q 0～QM－1 based on an input reference frequency signal, and generates N delay signals P 1～PN according to the M main phase signals, wherein N=M×S, and M, N, S is an integer greater than or equal to 1; a particular one of the N delay signals P 1～PN is selected to compare phase with a particular one of the M main phase signals, and the comparison result is converted into a digital error signal to calibrate an output phase error of the delay signal. The PWM signal post-processor modulates a time delay signal P n selected from N calibrated time delay signals to the modulation frequency F PWM of the PWM signal in a rising edge or falling edge modulation mode according to the modulation precision requirement to obtain a PWM modulation signal after high-precision modulation, wherein N is an integer from 1 to N.

Description

High-precision pulse width modulation system and method
Technical Field
The present invention relates to pulse width modulation systems, and more particularly to high resolution pulse width modulation systems with multi-phase delay.
Background
Pulse width modulation (PWM, pulse Width Modulation) is a very effective technique for controlling analog circuits using the digital output of a microprocessor, and is widely used in many fields from measurement, communication to power control and conversion. How to generate a high-precision PWM signal and fine-tune the pulse width of the PWM signal is a significant challenge in the art.
Some existing PWM systems use a delay locked loop (DLL-Delay Locked Loop) to control the PWM signal, as shown in fig. 1. The delay locked loop does not provide a multi-phase delay output signal and thus cannot be used in system applications requiring fine delay resolution.
In addition, it has been proposed in the prior art to implement 40 multi-phase delay signal outputs using 5x8 delay cells in a delay locked loop. But the generation of the multi-phase signal at its input uses analog circuit interpolation techniques, which tend to cause phase errors in the multi-phase input signal, and do not provide a high precision pwm implementation.
Disclosure of Invention
In order to realize high-precision modulation of pulse width signals, the invention provides a high-precision pulse width modulation system and a high-precision pulse width modulation method.
The high-precision pulse width modulation system comprises a multiphase delay locked loop system and a PWM signal post-processor.
The multi-phase delay locked loop system is configured to generate M main phase signals (digital main phase signals) Q 0～QM－1 based on an input reference frequency signal, and generate N delay signals P 1～PN according to the M main phase signals, where n=m×s, M, N, S is an integer greater than or equal to 1; a particular one of the N delay signals P 1～PN is selected to compare phase with a particular one of the M main phase signals, and the comparison result is converted into a digital error signal to calibrate an output phase error of the delay signal.
The PWM signal post-processor modulates a time delay signal P n selected from N calibrated time delay signals to the modulation frequency F PWM of the PWM signal in a rising edge or falling edge modulation mode according to the modulation precision requirement to obtain a PWM modulation signal after high-precision modulation, wherein N is an integer from 1 to N.
In one embodiment, the multi-phase delay locked loop system includes a main phase signal generator configured to generate the M main phase signals Q 0～QM－1 based on the input reference frequency signal, the M main phase signals having a frequency Fout, the M main phase signals having a phase difference of 360/M degrees in turn.
In one embodiment, the multi-phase delay locked loop system further comprises a phase locked loop. The phase locked loop includes a delay module, a charge pump phase detector, a loop filter, and an analog to digital converter.
The time delay module comprises M time delay lines, each time delay line correspondingly receives one main phase signal in M main phase signals, and each time delay line comprises S numerical control time delay units which are sequentially connected in series; under the condition that the delay module has no error, each delay line delays the corresponding main phase signal to output S delay signals with the same phase difference in sequence, so that delay delta T=1/(fout×M×S) is formed among the delay signals, and the phase shift difference is 360/(M×S).
The charge pump phase discriminator is configured to compare whether the phase of the delay signal P k output by the last delay unit in the j-th delay line is the same as the phase of the main phase signal Q j input to the next delay line, so as to obtain a comparison result in the form of an analog current, where P k is the specific delay signal, Q j is the specific main phase signal, j is an integer from 1 to M, k=j×s, and Q M is regarded as Q 0.
The loop filter converts the comparison result into an analog voltage value.
The analog-to-digital converter converts the analog voltage value into the digital error signal, the digital error signal carries phase error information between P k and Q j, and the digital error signal is fed back to the time delay module; when the digital error signal indicates that the phases of P k and Q j are the same, the delay line corresponding to P k has no error; when the digital error signal indicates that the phase error exists between the P k and the Q j, the delay line corresponding to the P k needs to be calibrated, the delay module adjusts the output phase error of the delay signal according to the digital error signal, outputs the phase-adjusted P k to the charge pump phase discriminator to compare with the Q j again until the digital error signal indicates that the phase of the P k is the same as the phase of the Q j, and the delay line error of the delay module is corrected.
In one embodiment, the multi-phase delay locked loop system further comprises a first gate, a second gate, and a digital state machine.
The first gate is configured to select P 0、Pn and P k from the output of the delay module under the control of the digital state machine, where P 0 represents a signal that is not delayed, P 0 is input to the PWM signal post-processor, P n is a delay signal calibrated to modulate the modulation frequency F PWM of the PWM signal, P n is input to the PWM signal post-processor, P k is a delay signal to correct phase error, and P k is input to the charge pump phase detector.
The second gate is configured to select Q j,Qj from the M digital master phase signals Q 0～QM－1 to be sent to the charge pump phase detector under control of the digital state machine.
The digital state machine is configured to perform signal gating control and system control of the first and second gates according to a state control signal from a main control unit and the digital error signal.
In one embodiment, the digital state machine selects, according to the state control signal, whether to perform phase error calibration on only the delay signal output by the delay line corresponding to one of the M digital main phase signals or perform phase error calibration on the delay signals output by the delay lines corresponding to all the M digital main phase signals.
In one embodiment, the digital state machine further selects either the rising edge or the falling edge modulation scheme based on the state control signal.
In one embodiment, where the digital state machine chooses to calibrate the output phase errors of all N delay signals P 1～PN, when the digital error signal indicates no phase error between P k and Q j, the digital state machine controls the first and second gates to gate the next set of P k and Q j for phase comparison by the phase locked loop, where the next set of P k and Q j refers to P k and Q j obtained after j=j+1.
In an embodiment, when the delay signal P n is modulated to the modulation frequency F PWM of the PWM signal by a rising edge modulation method, the rising edge delay is (N/N) ×Δt, Δt=1/(fout×n), and N is an integer from 1 to N/2.
In an embodiment, when the delay signal P n is modulated to the modulation frequency F PWM of the PWM signal by a falling edge modulation method, the falling edge delay is- (N-N/N) ×Δt, Δt=1/(fout×n), and N is an integer of N/2+1 to N.
In one embodiment, the PWM signal post-processor comprises a first D-type flip-flop, a second D-type flip-flop, and an or gate;
The D end input of the first D-type trigger is the modulation frequency F PWM of the PWM signal, and the C end input is P 0;
The D end input of the second D-type trigger is the modulation frequency F PWM of the PWM signal, and the C end input is P n;
The outputs of the first and second D-type flip-flops are used as inputs of an OR gate, and the outputs of the OR gate are the PWM modulation signals after high-precision modulation.
In one embodiment, the primary phase signal generator is a current-mode logic digital divider.
In one embodiment, the main phase signal generator is implemented by a multi-phase ring oscillator and a phase locked loop coupled to the multi-phase ring oscillator.
The high-precision pulse width modulation method comprises the following steps:
Providing a reference signal frequency and a modulation frequency Fpwm of the PWM signal;
Generating M digital main phase signals with frequency Fout based on the reference signal frequency, wherein the M main phase signals sequentially have a phase difference of 360/M degrees;
Providing a delay module with M delay lines, and carrying out delay on M digital main phase signals to obtain N delay signals P 1～PN, wherein N=M×S, and M, N, S is an integer greater than or equal to 1;
Selecting a specific time delay signal in N time delay signals P 1～PN to compare the phase with a specific main phase signal in M main phase signals, and converting the comparison result into a digital error signal to calibrate the output phase error of the time delay signals; and
According to the modulation precision requirement, modulating a time delay signal P n selected from the calibrated N time delay signals to the modulation frequency F PWM of the PWM signal by a rising edge or falling edge modulation mode to obtain a PWM modulation signal after high-precision modulation, wherein N is an integer from 1 to N.
In one embodiment, the step of providing the delay module with M delay lines delays each of the M digital main phase signals to obtain N delay signals P 1～PN includes:
Each delay line correspondingly receives one main phase signal in M main phase signals, wherein each delay line comprises S numerical control delay units which are sequentially connected in series;
Under the condition that the delay module has no error, each delay line delays the corresponding main phase signal to output S delay signals with a phase difference in sequence, so that delay delta T=1/(fout×M×S) is formed among the delay signals, and the phase shift difference is 360/(M×S).
In one embodiment, the step of selecting a particular one of the N delay signals P 1～PN to compare the phase with a particular one of the M main phase signals, converting the comparison result to a digital error signal to calibrate the output phase error of the delay signal includes:
only carrying out phase error calibration on a time delay signal output by a time delay line corresponding to one main phase signal in the M digital main phase signals; or (b)
And carrying out phase error calibration on the time delay signals output by the time delay lines corresponding to all M digital main phase signals.
In one embodiment, the step of selecting a specific one of the N delay signals P 1～PN to compare the phase with a specific one of the M main phase signals, and converting the comparison result into a digital error signal to calibrate the output phase error of the delay signal includes:
Selecting a delay signal P k output by a last delay unit in a j-th delay line and a main phase signal Q j input into a next delay line, and comparing whether phases are the same, wherein P k is the specific delay signal, Q j is the specific main phase signal, j is an integer from 1 to M, k=j is S, and Q M is regarded as Q 0;
converting the comparison result into an analog voltage value;
Converting the analog voltage value into the digital error signal with phase error information between P k and Q j, the digital error signal being fed back to the delay module; when the digital error signal indicates that the phases of P k and Q j are the same, then the delay line corresponding to P k has no error, the next group of P k and Q j is selected, for phase comparison, wherein the next set of P k and Q j refers to P k and Q j obtained after j=j+1; When the digital error signal indicates that the phase errors exist between the P k and the Q j, the delay line corresponding to the P k needs to be calibrated, the delay module adjusts the output phase error of the delay signal according to the digital error signal, And again comparing the phase adjusted P k with Q j until the digital error signal indicates that P k is the same phase as Q j, and the error correction of the delay line of the delay module is completed.
In one embodiment, when the delay signal P n is modulated to the modulation frequency F PWM of the PWM signal by a rising edge modulation method, the rising edge delay is (N/N) ×Δt, Δt=1/(fout×n), and N is an integer from 1 to N/2.
In one embodiment, when the delay signal P n is modulated to the modulation frequency F PWM of the PWM signal by a falling edge modulation method, the falling edge delay is- (N-N/N) ×Δt, Δt=1/(fout×n), and N is an integer of N/2+1 to N.
The high-precision pulse width modulation system and the method are applied to the multi-phase delay locked loop, and can realize high-precision modulation of pulse width signals.
Drawings
The foregoing summary of the invention, as well as the following detailed description of the invention, will be better understood when read in conjunction with the accompanying drawings. It is to be noted that the drawings are merely examples of the claimed invention. In the drawings, like reference numbers indicate identical or similar elements.
Fig. 1 illustrates a prior art delay locked loop;
fig. 2 shows a high resolution pulse width modulation system based on multi-phase delay according to an embodiment of the present invention;
FIG. 3 shows a logic circuit of a PWM post-processor according to an embodiment of the present invention;
FIG. 4 shows a timing diagram of input and output signals of a PWM post-processor according to an embodiment of the present invention;
FIG. 5 illustrates a system operation and control flow diagram according to an embodiment of the invention.
Detailed Description
The detailed features and advantages of the present invention will be set forth in the detailed description that follows, and in part will be readily apparent to those skilled in the art from that description or recognized by practicing the invention as described herein, and related objects and advantages thereof will be readily understood by those skilled in the art from the description, claims and drawings disclosed herein.
The pulse width modulation system of the present invention is a high resolution pulse width modulation (HR PWM) system based on a multi-phase delay (MP DLL). As shown in fig. 2, the system includes a multi-phase delay locked loop system and a PWM signal post-processor 210.
The multi-phase delay locked loop system includes a main phase signal generator 201, a first gate 202, a second gate 203, a phase locked loop 204, and a digital state machine 205. The phase locked loop 204 includes a delay block 206, a charge pump phase detector 207, a loop filter 208, and an analog to digital converter (ADC) 209.
The main phase signal generator 201 generates M digital main phase signals Q 0～QM－1 (having a frequency Fout) based on the input reference frequency signal Fref, where M is an integer of 1 or more. The M main phase signals have a phase difference of 360/M degrees in turn. For example, when M is 8, the phase difference between the 8 main phase signals Q 0-Q7 in turn is 45 degrees, and is 0, 45, 90, 135, 180, 225, 270, 315 degrees, respectively.
In one embodiment, the main phase signal generator 201 may be implemented by a current-mode logic digital divider (CML DIVIDER, current Mode Logic Divider). In one embodiment, the current-mode digital divider converts a single-ended input reference frequency signal Fref from a current-mode logic circuit to a fully differential signal, and then generates 8 main phase signals Q 0-Q7 from a divide-by-4 divider, where fout=fref/4. For example, the frequency of the input reference frequency signal Fref may be 400M, and the frequency of the output signal Fout of the main phase signal generator is 100M at this time.
In one embodiment, the main phase signal generator 201 may be implemented by a multi-phase ring oscillator (RO, ringOscillator) and a Phase Locked Loop (PLL). For example, the multi-phase ring oscillator may be an 8-phase ring oscillator, thereby generating 8 main phase signals Q 0-Q7. In one embodiment, the input reference frequency signal Fref may be a lower frequency, such as 24MHz or 40MHz. A Phase Locked Loop (PLL) multiplies the input reference frequency signal Fref to a high frequency, e.g. in the 100MHz range, while 8 main phase signals with a phase difference of 45 degrees are generated by an 8-phase output ring oscillator (8-phase RO). The ring oscillator can be generally composed of a CMOS inverter, the oscillation frequency and phase of which are controlled by current or voltage, and the final output frequency and phase are locked by a phase locking loop.
The Delay module 206 includes M Delay lines Delay [ M-1, …,0], each of which includes S identical digitally controlled Delay cells, i.e., each of which can provide S phase shift or Delay signal outputs. Each delay line correspondingly receives a main phase signal, and under the condition that the delay line has no error (or the condition that the error is calibrated), the delay line outputs S phase shift or delay signals with the same phase difference in sequence, and the phase difference is 360/(M) S degrees, so that the phase shift or delay signal output by the last delay unit in each delay line is the same as the phase of the main phase signal input into the next delay line.
The M delay lines together provide m×s phase shifted or delayed output signals, i.e., P 1,P2,...,PM*S, plus the original phase signal P 0 that has not been phase shifted, and the delay module 202 together outputs (m×s) +1 phase shifted or delayed signals, where P 0 is identical to P M*S (corresponding to a 360 degree phase shift) and Q 0 are identical in phase. The phase difference between the phase-shifted signals is 360/(m×s) degrees, and if converted into a time delay, the phase difference between the time-delayed signals is Δt=1/(fout×m×s). The delay time of the P n th delay signal (n E [1, M S ]) is n/(Fout M S).
It should be noted that the term "phase shift" and the term "delay" are understood by those skilled in the art to have substantially the same meaning, and thus, reference herein to "phase shifted signal" and "delay signal" refers to the same signal, and "phase error" and "delay error" have substantially the same meaning.
In one embodiment, it is assumed that m= 8,S =8, i.e. the main phase signal generator generates 8 main phase signals Q 0～Q7, which in turn are phase shifted by 45 degrees, Q 0 by 0 degrees, Q 1 by 45 degrees, Q 2 is 90 degrees out of phase, Q 3 is 135 degrees out of phase, Q 4 is 180 degrees out of phase, Q 5 is 225 degrees out of phase, Q 6 is phase shifted 270 degrees and Q 7 is phase shifted 315 degrees. After Q 0 is input to the first delay line, the delay line outputs 8 phase-shifted or delayed signals P 1～P8, the phase difference between the 8 phase-shifted or delayed signals in turn is 45/8 degrees, the phase difference of the 8 th phase-shifted or delayed signal P 8 is 45 degrees, Exactly the same phase difference (45 degrees) as the next main phase signal Q 1. And so on, Q 7 (with a phase difference of 315 degrees) is input to the eighth delay line, which outputs 8 phase-shifted or delayed signals P 57～P64, the phase difference between the 8 phase-shifted or delayed signals in turn is 45/8 degrees, at which time the phase difference of the 8 th phase-shifted or delayed signal P 64 of the delay line is exactly 360 degrees, The same phase difference (0 degrees) as Q 0.
Ideally, i.e. if the delay module itself has no error, the phase shift or delay signal output P k from the last delay unit in each delay line should be the same as the phase of the main phase signal Q j input to the next delay line, where j represents the j-th delay line, j is an integer from 1 to M, k=j×s, and Q M is regarded as Q 0. That is, in the case of m= 8,S =8, when j=1, the phase of P 8 should be the same as Q 1. The phase of P 16 should be the same … … as Q 2 and so on when j=2, and the phase of P 64 should be the same as Q 0 when j=8. However, in practical applications, errors are generated in the delay module or delay line, so that the phase difference between the obtained 65-path phase-shifted or delayed signals is not equal, that is, the phase of P 8 and the phase of Q 1 will have errors, the phase of P 16 and the phase of Q 2 will have errors … … and so on, There is an error in the phase of P 64 and the phase of Q 0. if the pulse width of the PWM signal is adjusted by using 65-way phase shifted or delayed output signals with phase errors, the adjustment accuracy is greatly reduced. Therefore, in order to solve this problem, the present invention controls and adjusts the output delay error or output phase error generated by the delay module by comparing whether the phase shift or delay signal output P k output by the last delay unit in each delay line is the same as the phase of the main phase signal Q j input to the next delay line.
The first gate 202 receives the outputs from the delay modules and selectively outputs three signals from these output signals via control of the digital state machine 205, the three signals being:
-P 0, output to a PWM signal Post Processor (Post Processor) 210 for phase synchronization processing functions in the Post Processor;
-P n as a selected delay signal to the post-processor 210, the delay time of which can be calculated from (n/(m×s)) × (1/Fout); wherein n=1, 2,..m.s;
-P k, selected as one input reference signal for a charge pump phase detector (PD/CP) 207 in a phase locked loop, where k=j×s, j e 1, m.
The second gate 203 receives the M main phase signals, and selects a signal Q j from the main phase signals to output to the charge pump phase detector 207 under the control of the digital state machine 205.
The charge pump phase detector 207 compares whether P k and Q j are in phase, where the choice of P k and Q j is not arbitrary, To satisfy k=j×s, Q M is regarded as Q 0. That is, assuming that m= 8,S =8, it is necessary to select P 8 to Q 1, P 16 to Q 2, P 24 compared to Q 3, P 32 compared to Q 4, P 40 compared to Q 5, P 48 compared to Q 6, P 56 compared to Q 7, P 64 compared to Q 0.
The charge pump type phase detector 207 outputs the comparison result to the Loop Filter (LF) 208 in the form of an analog current, obtains an analog voltage value, and then outputs a digital quantity (i.e., a digital error signal) as a control signal after being converted by the analog-to-digital converter (ADC) 209, and one path of the control signal is fed back to the delay module 206 to adjust the phase shift or the delay error of the delay module, and the other path of the control signal is output to the digital state machine 205 to control the state switching of the state machine, i.e., the gating of the first gate and the second gate. The control signal carries the phase error information of P k and Q j.
Ideally, the phases of P k and Q j are identical, so if the charge pump phase detector 207 compares to find that the phases are identical, then this indicates that there is no phase error between P k and Q j, and the delay line corresponding to P k does not need to be error-adjusted, and the digital state machine 205 selects whether the phases of the next set of comparison objects are identical, where the next set of comparison objects refer to P k and Q j obtained after j=j+1.
If the charge pump phase detector 207 finds that there is an error in the phases of P k and Q j, the comparison result is converted to a digital quantity (digital error signal) by the analog-to-digital converter and fed back to the delay module 206. The digital quantity represents the magnitude of the error. The delay module 206 adjusts the error according to the digital quantity, the adjusted output P k is compared with Q j by the charge pump type phase discriminator and feeds back the digital quantity to the delay module 206, and the process is repeated until the comparison result indicates that the phases of P k and Q j are the same, which indicates that the delay line corresponding to P k is calibrated at this time, the digital state machine 205 controls the charge pump type phase discriminator 207 to jump to the next group of comparison objects, i.e. let j=j+1 (i.e. start the calibration of the next delay line), and continuously compares whether the phases of P k and Q j are the same, so as to repeat until the whole delay module is calibrated.
In one embodiment, the resolution required for the analog-to-digital converter (ADC) 209 of the present invention is low, typically 4 bits.
In one embodiment, a Digital State Machine (DSM) 205 is used for system control, correction control, and delay selection of the post-processor. A Digital State Machine (DSM) 205 receives two signal inputs, one digital error signal with phase error information, output by an analog-to-digital converter (ADC) 209 in the phase locked loop 204; the other is a status control signal from a main control unit (SOC), such as an on-chip Microprocessor (MCU), e.g. a power-up, calibration end, calibration start, etc. control signal. The digital state machine 205 outputs digital control signals for signal selection control of the first and second gates and control of the entire system according to two input signals.
In one embodiment, the digital state machine 205 may selectively calibrate the phase error of only the delay signal output by the delay line corresponding to one of the M digital main phase signals according to the state control signal, or may selectively calibrate the phase error of the delay signals output by the delay lines corresponding to all of the M digital main phase signals. The control may be performed by controlling signal selection of the first and second gates.
In one embodiment, the digital state machine 205 also selects either the rising edge or the falling edge modulation scheme based on the state control signal.
In one embodiment, where the digital state machine 205 chooses to calibrate the output phase errors of all N delay signals P 1～PN, the digital state machine 205 controls the first and second gates to gate the next set of P k and Q j for phase-locked loop phase comparison when the digital error signal indicates no phase error between P k and Q j, where the next set of P k and Q j refer to P k and Q j that result after j=j+1.
The input signals of the PWM post-processor 210 are P 0, P n and F PWM, where F PWM is the modulation frequency of the PWM signal, and the output signal is the PWM modulated signal after high-precision modulation. The PWM post-processor 210 may modulate either the rising edge of the F PWM frequency signal or the falling edge of the F PWM frequency signal. The PWM post-processor 210 modulates a delay signal P n selected from the calibrated N delay signals to the modulation frequency F PWM of the PWM signal by a rising edge or falling edge modulation mode according to the modulation precision requirement, so as to obtain a PWM modulation signal after high precision modulation, where N is an integer from 1 to N, and different P n represent different modulation precision.
The PWM post-processor 210 in the present invention may be implemented by a simple logic circuit. Fig. 3 shows a logic implementation of a PWM post-processor according to an embodiment of the present invention. As shown in fig. 3, the PWM signal post-processor includes a first D-type flip-flop, a second D-type flip-flop, and an or gate. The D end input of the first D-type trigger is the modulation frequency F PWM of the PWM signal, and the C end input is P 0. The D end input of the second D-type trigger is the modulation frequency F PWM of the PWM signal, and the C end input is P n. The outputs of the first and second D-type flip-flops are input to an or gate whose output is the PWM modulated signal after the high precision modulation, represented by PWMn in the figure.
In one embodiment, when the delay signal P n is modulated to the modulation frequency F PWM of the PWM signal by the rising edge modulation method, the rising edge delay is (N/N) ×Δt, Δt=1/(fout×n), and N is an integer from 1 to N/2.
In one embodiment, when the delay signal P n is modulated to the modulation frequency F PWM of the PWM signal by a falling edge modulation method, the falling edge delay is- (N-N/N) ×Δt, Δt=1/(fout×n), and N is an integer of N/2+1 to N.
The timing relationship of the input and output signals of the post-processor 210 is given by fig. 4. For simplicity and clarity, the timing relationship in fig. 4 is given only in terms of a delay module of 8-phase output, i.e., the delay module outputs P 1～P8 in total.
The system of the present invention may modulate the falling edge of a pulse with a time delay, e.g., n=1/2/3, or modulate the rising edge of a pulse with a time delay, e.g., n=4/5/6/7.
It should be noted that the PWM post-processor 210 of the present invention is not limited to implementation with the logic circuit shown in fig. 3. Those skilled in the art will appreciate that the PWM post-processor 210 may also be implemented using other modules or circuits.
In addition, the values of M and S of the present invention are not limited to the values mentioned in the above embodiments, and may be selected according to actual requirements (e.g., accuracy requirements). In addition, the high-precision pulse width modulation system of the invention can select only the output phase of the delay signal corresponding to one main phase signal in the M main phase signals for calibration, and the multi-phase delay locked loop system becomes a single phase locked loop substantially.
The invention also discloses a high-precision pulse width modulation method, which comprises the following steps:
Providing a reference signal frequency and a modulation frequency Fpwm of the PWM signal;
Generating M digital main phase signals with frequency Fout based on the reference signal frequency, wherein the M main phase signals sequentially have a phase difference of 360/M degrees;
Providing a time delay module with M time delay lines, and performing time delay on M digital main phase signals to obtain N time delay signals P 1～PN, wherein N=M×S, and M, N, S is an integer greater than or equal to 1;
Selecting a specific time delay signal in N time delay signals P 1～PN to compare the phase with a specific main phase signal in M main phase signals, and converting the comparison result into a digital error signal to calibrate the output phase error of the time delay signals; and
According to the modulation precision requirement, modulating a time delay signal P n selected from the calibrated N time delay signals to the modulation frequency F PWM of the PWM signal by a rising edge or falling edge modulation mode to obtain a PWM modulation signal after high-precision modulation, wherein N is an integer from 1 to N.
In one embodiment, the step of providing the delay module with M delay lines delays each of the M digital main phase signals to obtain N delay signals P 1～PN includes:
Each delay line correspondingly receives one main phase signal in M main phase signals, wherein each delay line comprises S numerical control delay units which are sequentially connected in series;
Under the condition that the delay module has no error, each delay line delays the corresponding main phase signal to output S delay signals with a phase difference in sequence, so that delay delta T=1/(fout×M×S) is formed among the delay signals, and the phase shift difference is 360/(M×S).
In one embodiment, the step of selecting a particular one of the N delay signals P 1～PN to compare the phase with a particular one of the M main phase signals, converting the comparison result to a digital error signal to calibrate the output phase error of the delay signal includes:
only carrying out phase error calibration on a time delay signal output by a time delay line corresponding to one main phase signal in the M digital main phase signals; or (b)
And carrying out phase error calibration on the time delay signals output by the time delay lines corresponding to all M digital main phase signals.
In one embodiment, the step of selecting a particular one of the N delay signals P 1～PN to compare the phase with a particular one of the M main phase signals, converting the comparison result to a digital error signal to calibrate the output phase error of the delay signal includes:
Selecting a delay signal P k output by a last delay unit in a j-th delay line and a main phase signal Q j input into a next delay line, and comparing whether phases are the same, wherein P k is the specific delay signal, Q j is the specific main phase signal, j is an integer from 1 to M, k=j is S, and Q M is regarded as Q 0;
converting the comparison result into an analog voltage value;
Converting the analog voltage value into the digital error signal with phase error information between P k and Q j, the digital error signal being fed back to the delay module; when the digital error signal indicates that the phases of P k and Q j are the same, then the delay line corresponding to P k has no error, the next group of P k and Q j is selected, for phase comparison, wherein the next set of P k and Q j refers to P k and Q j obtained after j=j+1; When the digital error signal indicates that the phase errors exist between the P k and the Q j, the delay line corresponding to the P k needs to be calibrated, the delay module adjusts the output phase error of the delay signal according to the digital error signal, And again comparing the phase adjusted P k with Q j until the digital error signal indicates that P k is the same phase as Q j, and the error correction of the delay line of the delay module is completed.
In one embodiment, when the delay signal P n is modulated to the modulation frequency F PWM of the PWM signal by a rising edge modulation method, the rising edge delay is (N/N) ×Δt, Δt=1/(fout×n), and N is an integer from 1 to N/2.
In one embodiment, when the delay signal P n is modulated to the modulation frequency F PWM of the PWM signal by a falling edge modulation method, the falling edge delay is- (N-N/N) ×Δt, Δt=1/(fout×n), and N is an integer of N/2+1 to N.
FIG. 5 illustrates a system operation and control flow diagram according to an embodiment of the invention. After Power up (Power On) and Reset (Reset), the reference signal frequency Fref and PWM modulated signal frequency F PWM are ready (step 501), the master phase generator generates M master phase signals Q 0～QM-1 (step 502). Depending on the system accuracy requirements, the present invention may perform calibration flow control (Calibration Control) of a Single-Phase or multiple-phases (Multi-Phase) on a Multi-Phase Delay line, such as Delay [ M-1:0], and gate control on the first and second gates by a digital state machine (step 503). The output phase of the phase-locked loop is compared with the main phase, and the error signal is converted into a digital signal to control and adjust the time delay of the time delay line, so that the phase lock of the phase-locked loop eliminates the phase error, and a high-precision multiphase time delay line system is realized. After the calibration procedure is completed (Cal End)
The digital state machine and gates (e.g., mux 65-to-3 and Mux 8-to-1) select a phase shift signal or delay signal P k of a fixed delay line and the corresponding main phase signal Q j, where k=j×s, j being an integer from 1 to M, and the phase locked loop locks the two phase signals (steps 505 and 506). At this time, the multi-phase delay line will output a phase shifted or delayed signal after calibration and phase locking. The PWM signal post-processor will be turned on and the digital state machine will control the post-processor according to the system requirements, select the delay (FALLING EDGE DELAY) to generate the rising edge delay (RISE EDGE DELAY) or the falling edge, and modulate onto the modulation frequency F PWM of the PWM. Finally, the PWM modulation signal with high precision delay is Output (PWM Output) by an Output driving circuit (Driver). Calculation of rising edge delay can be calculated by a formula: (N/N) ×Δt= (1/Fout), such as n=64, n=0, 1, …,31, and the delay of the falling edge can be calculated according to the formula, - (N-N/N) ×Δt= (1/Fout), such as n=64, n=32, 33, …,63, Δt= (1/Fout)/64
(Step 507).
For ease of illustration, the above described workflow uses a delay line and PWM system with 8 main phases and 64 delay units, but the present invention is applicable to various corresponding multi-main phase and multi-delay unit systems.
The terms and expressions which have been employed herein are used as terms of description and not of limitation. The use of these terms and expressions is not meant to exclude any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible and are intended to be included within the scope of the claims. Other modifications, variations, and alternatives are also possible. Accordingly, the claims should be looked to in order to cover all such equivalents.
Also, it should be noted that while the present application has been described with reference to the particular embodiments presently, it will be appreciated by those skilled in the art that the above embodiments are provided for illustration only and that various equivalent changes or substitutions may be made without departing from the spirit of the application, and therefore, the changes and modifications to the above embodiments shall fall within the scope of the claims of the present application as long as they are within the true spirit of the application.

Claims (16)

1. A high precision pulse width modulation system comprising:
A multi-phase delay locked loop system configured to generate M main phase signals Q 0～QM－1 based on an input reference frequency signal, and generate N delay signals P 1～PN according to the M main phase signals, where n=m×s, M, N, S is an integer greater than or equal to 1; selecting a designated delay signal of the N delay signals P 1～PN to compare the phase with a designated main phase signal of the M main phase signals, and converting the comparison result into a digital error signal to calibrate the output phase error of the delay signals; and
The PWM signal post-processor modulates a time delay signal P n selected from N calibrated time delay signals to the modulation frequency F PWM of the PWM signal in a rising edge or falling edge modulation mode according to the modulation precision requirement to obtain a PWM modulation signal after high-precision modulation, wherein N is an integer from 1 to N.
2. The high precision pulse width modulation system of claim 1, wherein the multi-phase delay locked loop system comprises:
A main phase signal generator configured to generate the M main phase signals Q 0～QM－1 based on the input reference frequency signal, the M main phase signals having a frequency Fout, the M main phase signals having a phase difference of 360/M degrees in turn.
3. The high precision pulse width modulation system of claim 2, wherein the multi-phase delay locked loop system further comprises:
a phase locked loop, comprising:
The time delay module comprises M time delay lines, each time delay line correspondingly receives one main phase signal in M main phase signals, and each time delay line comprises S numerical control time delay units which are sequentially connected in series; under the condition that the delay module has no error, each delay line delays the corresponding main phase signal to output S delay signals with the same phase difference in sequence, so that delay delta T=1/(Fout M S) is formed among the delay signals, and the phase shift difference is 360/(M S);
The charge pump type phase discriminator is configured to compare whether a time delay signal P k output by a last time delay unit in a j-th time delay line is the same as a main phase signal Q j input into a next time delay line or not to obtain a comparison result in an analog current form, wherein P k is the appointed time delay signal, Q j is the appointed main phase signal, j is an integer from 1 to M, k=j is S, and Q M is regarded as Q 0;
A loop filter converting the comparison result into an analog voltage value;
An analog-to-digital converter for converting the analog voltage value into the digital error signal with phase error information between P k and Q j, the digital error signal being fed back to the delay module; when the digital error signal indicates that the phases of P k and Q j are the same, the delay line corresponding to P k has no error; when the digital error signal indicates that the phase errors exist between the P k and the Q j, the delay line corresponding to the P k needs to be calibrated, the delay module adjusts the output phase error of the delay signal according to the digital error signal, outputs the phase-adjusted P k to the charge pump phase discriminator to compare with the Q j again until the digital error signal indicates that the phases of the P k and the Q j are the same, and the delay line error corresponding to the P k is corrected.
4. The high precision pwm system of claim 3, wherein the multi-phase delay locked loop system further comprises:
A first gate, a second gate, and a digital state machine;
The first gate is configured to select P 0、Pn and P k from the output of the delay module under the control of the digital state machine, wherein P 0 represents a signal which is not delayed, P 0 is input to the PWM signal post-processor, P n is a delay signal which is calibrated and used for modulating the modulation frequency F PWM of the PWM signal, P n is input to the PWM signal post-processor, P k is a delay signal used for correcting a phase error, and P k is input to the charge pump type phase detector;
the second gate is configured to select Q j,Qj from M main phase signals Q 0～QM－1 to be sent to the charge pump phase detector under the control of the digital state machine;
the digital state machine is configured to perform signal gating control and system control of the first gating device and the second gating device according to a state control signal from a main control unit and the digital error signal, wherein:
The digital state machine selects to calibrate the phase error of the delay signal output by the delay line corresponding to one of the M main phase signals according to the state control signal, or to calibrate the phase error of the delay signal output by the delay line corresponding to all the M main phase signals, and the digital state machine also selects the rising edge or the falling edge modulation mode according to the state control signal.
5. The high precision pwm system of claim 4, wherein in the case where the digital state machine chooses to calibrate the output phase errors of all N delay signals P 1～PN, when the digital error signal indicates no phase error between P k and Q j, the digital state machine controls the first and second gates to gate the next set of P k and Q j for phase comparison by the phase locked loop, wherein the next set of P k and Q j refer to P k and Q j after j = j + 1.
6. The high-precision PWM system of claim 1, wherein when the delay signal P n is modulated to the modulation frequency F PWM of the PWM signal by rising edge modulation, the rising edge delay is (N/N) ×Δt, Δt=1/(fout×n), and N is an integer from 1 to N/2.
7. The high-precision PWM system of claim 1, wherein when the delay signal P n is modulated to the modulation frequency F PWM of the PWM signal by a falling-edge modulation, the falling-edge delay is- (N-N/N) ×Δt, Δt=1/(fout×n), and N is an integer from N/2+1 to N.
8. The high precision pulse width modulation system of claim 1, wherein the PWM signal post-processor comprises a first D-type flip-flop, a second D-type flip-flop, and an or gate;
The D end input of the first D-type trigger is the modulation frequency F PWM of the PWM signal, and the C end input is P 0;
The D end input of the second D-type trigger is the modulation frequency F PWM of the PWM signal, and the C end input is P n;
The outputs of the first and second D-type flip-flops are used as inputs of an OR gate, and the outputs of the OR gate are the PWM modulation signals after high-precision modulation.
9. The high precision pulse width modulation system of claim 2, wherein the primary phase signal generator is a current-mode logic digital divider.
10. The high precision pulse width modulation system of claim 2, wherein the main phase signal generator is implemented by a multi-phase ring oscillator and a phase locked loop coupled to the multi-phase ring oscillator.
11. A method of high precision pulse width modulation, the method comprising:
Providing a reference signal frequency and a modulation frequency Fpwm of the PWM signal;
Generating M main phase signals with frequency Fout based on the reference signal frequency, wherein the M main phase signals sequentially have a phase difference of 360/M degrees;
Providing a time delay module with M time delay lines, and performing time delay on M main phase signals to obtain N time delay signals P 1～PN, wherein N=M×S, and M, N, S is an integer greater than or equal to 1;
Selecting a designated delay signal of the N delay signals P 1～PN to compare the phase with a designated main phase signal of the M main phase signals, and converting the comparison result into a digital error signal to calibrate the output phase error of the delay signals; and
According to the modulation precision requirement, modulating a time delay signal P n selected from the calibrated N time delay signals to the modulation frequency F PWM of the PWM signal by a rising edge or falling edge modulation mode to obtain a PWM modulation signal after high-precision modulation, wherein N is an integer from 1 to N.
12. The method of claim 11, wherein providing a delay module having M delay lines to delay each of the M main phase signals to obtain N delay signals P 1～PN comprises:
Each delay line correspondingly receives one main phase signal in M main phase signals, wherein each delay line comprises S numerical control delay units which are sequentially connected in series;
Under the condition that the delay module has no error, each delay line delays the corresponding main phase signal to output S delay signals with the same phase difference in sequence, so that delay delta T=1/(fout×M×S) is formed among the delay signals, and the phase shift difference is 360/(M×S).
13. The method of claim 12, wherein selecting a specified one of the N delay signals P 1～PN to compare phases with a specified one of the M main phase signals, converting the comparison result to a digital error signal to calibrate an output phase error of the delay signal comprises:
only carrying out phase error calibration on a time delay signal output by a time delay line corresponding to one of the M main phase signals; or (b)
And carrying out phase error calibration on the time delay signals output by the time delay lines corresponding to all M main phase signals.
14. The method of claim 12, wherein selecting a specified one of the N delay signals P 1～PN to compare phases with a specified one of the M main phase signals, converting the comparison result to a digital error signal to calibrate an output phase error of the delay signal comprises:
Selecting a delay signal P k output by a last delay unit in a j-th delay line and a main phase signal Q j input into a next delay line, and comparing whether phases are the same, wherein P k is the specified delay signal, Q j is the specified main phase signal, j is an integer from 1 to M, k=j is S, and Q M is regarded as Q 0;
converting the comparison result into an analog voltage value;
Converting the analog voltage value into the digital error signal with phase error information between P k and Q j, the digital error signal being fed back to the delay module; when the digital error signal indicates that the phases of P k and Q j are the same, then the delay line corresponding to P k has no error, the next group of P k and Q j is selected, for phase comparison, wherein the next set of P k and Q j refers to P k and Q j obtained after j=j+1; When the digital error signal indicates that the phase errors exist between the P k and the Q j, the delay line corresponding to the P k needs to be calibrated, the delay module adjusts the output phase error of the delay signal according to the digital error signal, And again comparing the phase adjusted P k with Q j until the digital error signal indicates that P k is the same phase as Q j, and the error correction of the delay line of the delay module is completed.
15. The method of claim 11, wherein when the delay signal P n is modulated to the modulation frequency F PWM of the PWM signal by rising edge modulation, the rising edge delay is (N/N) ×Δt, Δt=1/(fout×n), and N is an integer from 1 to N/2.
16. The method of claim 11, wherein when the delay signal P n is modulated to the modulation frequency F PWM of the PWM signal by a falling-edge modulation, the falling-edge delay is- (N-N/N) ×Δt, Δt=1/(fout×n), and N is an integer of N/2+1 to N.
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