CN112165315A - Linear phase interpolator, linear phase interpolation chip and data clock recovery circuit - Google Patents
Linear phase interpolator, linear phase interpolation chip and data clock recovery circuit Download PDFInfo
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Abstract
The embodiment of the invention relates to the field of phase interpolation, in particular to a linear phase interpolator, which comprises: n parallel phase interpolation units, each phase interpolation unit is used for selecting a corresponding differential clock signal from the multi-path differential clock signals according to the carrier modulation signal as an output signal of the phase interpolation unit; and the accumulation unit is used for superposing the output signals of the N paths of phase interpolation units to be used as the output signals of the interpolator. Meanwhile, a corresponding linear phase interpolation chip and a data clock recovery circuit are also provided. The implementation method provided by the invention can improve the accuracy and the linearity of the linear phase interpolation.
Description
Technical Field
The present invention relates to the field of phase interpolation, and in particular, to a linear phase interpolator, a linear phase interpolation chip, and a data clock recovery circuit.
Background
PI (phase interpolator) is widely used in integrated circuits to enable the output clock signal to have high precision and phase controllability. The input of the conventional phase interpolator generally receives 2 sets of differential clock signals, i.e. 2 sets of signals with phases completely opposite to each other, which are I, I-Q, Q-, respectively, and generates a specific output phase by adjusting the weight values of I, I-Q, Q-. In the existing phase interpolator, the interval step of each clock signal phase is longer, and the increment of the clock phase is larger.
Specifically, the phase interpolation technique utilizes a trigonometric function induction formula to sum two monophonic sine or cosine signals with the same frequency and different phases, so as to obtain a signal with the same frequency and the other phase. The weighted summation can be realized by changing the weighted values (amplitudes A1 and A2) of the two single-tone signals, so that the phase of the output signal is changed for a phase interpolator with P digits, P digital control codes are input, the corresponding output phase is changed from 0 degrees to 360 degrees, the step length is that in an actual circuit, the weighted values can be generated by controlling the current, the resistor, the capacitor array and other modes through the digital control codes, and the phase output is changed.
The disadvantages of the prior art phase modulators are as follows: 1. the output signal amplitude is not stable enough; 2. the phase precision of the synthesized signal is not ideal enough; 3. the linearity of the synthesized signal is not ideal.
Disclosure of Invention
The present invention is directed to a linear phase interpolator, a chip and a data clock recovery circuit, which at least partially solve the above problems.
To achieve the above object, according to a first aspect of the present invention, there is provided a linear phase interpolator comprising:
n parallel phase interpolation units, each phase interpolation unit is used for selecting a corresponding differential clock signal from the multi-path differential clock signals according to the carrier modulation signal as an output signal of the phase interpolation unit; and the accumulation unit is used for superposing the output signals of the N paths of phase interpolation units to be used as the output signals of the linear phase interpolator.
Preferably, the clock signals are orthogonal first differential clock signals, second differential clock signals, third differential clock signals and fourth differential clock signals; the carrier modulation signal is a four-way differential carrier modulation signal; each phase interpolation unit comprises: two identical load resistances: the first ends of the first load resistor and the second load resistor are respectively connected with a power supply, and the second ends of the first load resistor and the second load resistor are respectively used as a first output end and a second output end of the phase interpolation unit; eight identical amplifier tubes: the drain electrodes of the first amplifying tube, the third amplifying tube, the fifth amplifying tube and the seventh amplifying tube are all connected with the second end of the first load resistor; the drain electrodes of the second amplifying tube, the fourth amplifying tube, the sixth amplifying tube and the eighth amplifying tube are all connected with the second end of the second load resistor; the gates of the first amplifying tube and the fourth amplifying tube share the first differential clock signal, the gates of the second amplifying tube and the third amplifying tube share the second differential clock signal, the gates of the fifth amplifying tube and the eighth amplifying tube share the third differential clock signal, and the gates of the sixth amplifying tube and the seventh amplifying tube share the fourth differential clock signal; four identical switching tubes: the source electrodes of the first amplifying tube and the second amplifying tube are connected with the drain electrode of the first switching tube, the source electrodes of the third amplifying tube and the fourth amplifying tube are connected with the drain electrode of the second switching tube, the source electrodes of the fifth amplifying tube and the sixth amplifying tube are connected with the drain electrode of the third switching tube, and the source electrodes of the seventh amplifying tube and the eighth amplifying tube are connected with the drain electrode of the fourth switching tube; the grid electrodes of the first switching tube, the second switching tube, the third switching tube and the fourth switching tube are respectively connected to the four paths of differential carrier modulation signals; and two identical equal current sources: the source electrodes of the first switch tube and the second switch tube are connected with the first equi-value current source, and the source electrodes of the third switch tube and the fourth switch tube are connected with the second equi-value current source.
Preferably, the linear phase interpolator further comprises: a clock circuit for generating the quadrature four-way differential clock signals, the clock circuit comprising: a clock source for generating a clock signal; the frequency division sub-circuit is used for generating two paths of orthogonal clock sub-signals from the clock signals; and the phase shifting sub-circuit is used for converting each path of clock sub-signal into two paths of differential clock signals.
Preferably, each of the equivalent current sources comprises: the grid electrode of the amplifying triode is connected with a bias voltage source, the source electrode of the amplifying triode is grounded, and the drain electrode of the amplifying triode is used for providing current for the connected devices; the bias voltage source is used for providing bias voltage.
Preferably, the value of N is 127.
Preferably, the four paths of differential carrier modulation signals are binary signals with K bits, where K and N have the following relationship: n is 2K-1。
Preferably, the linear phase interpolator further comprises a decoding circuit for encoding the K-bit binary signal into an N-bit thermometer code.
In a second aspect of the present invention, there is also provided a linear phase interpolation chip configured to include the aforementioned linear phase interpolator.
Preferably, the chip includes: k input pins for receiving carrier modulation signal input; a differential clock signal input pin for receiving a differential clock signal input; and an output pin for outputting an output signal of the chip.
In a third aspect of the present invention, there is also provided a data clock recovery circuit, which includes the aforementioned linear phase interpolator or the aforementioned linear phase interpolation chip.
The linear phase interpolator, the chip and the data clock recovery circuit have the following beneficial effects:
1) triangular wave approximation is not needed, so that the amplitude of the output signal of the phase interpolator is constant;
2) the direct-current static working point of the output node is not influenced by the modulation signal;
3) meanwhile, the linearity of the open-loop modulator is ideal, and modulation modes with higher requirements on the linearity, such as BPSK, QPSK, 16QAM and the like, can be simultaneously supported.
Additional features and advantages of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate an embodiment of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:
FIG. 1 is a schematic diagram of a linear phase interpolator according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a linear phase interpolator according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of a linear phase interpolation chip according to an embodiment of the present invention.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating embodiments of the invention, are given by way of illustration and explanation only, not limitation.
Fig. 1 is a schematic structural diagram of a linear phase interpolator according to an embodiment of the present invention, and as shown in fig. 1, the linear phase interpolator includes:
and each phase interpolation unit is used for selecting a corresponding differential clock signal from the multi-path differential clock signals according to the carrier modulation signal as an output signal of the phase interpolation unit. Most of the existing phase modulation signals are realized by changing the weight of a plurality of paths of differential clock signals, and the embodiment is realized by changing the number of the phase interpolation units in a conducting working state in N phase interpolation units. The output after the phase interpolation units are superposed can ensure that the output power of each phase interpolation unit is smaller under the condition of meeting the output signal power, so that the output power is kept in a low-power linear state, and the linearity of the phase interpolation is realized. In this embodiment, the plurality of differential clock signals may be output by using a multi-modulus divider, or may be output by using a divider circuit plus a phase shifter circuit.
And the accumulation unit is used for superposing the output signals of the N paths of phase interpolation units to be used as the output signals of the interpolator. Vout (i) is the output of the i-th phase interpolation unit, VoutFor the output signal of the interpolator, the calculation formula is:
the accumulation of the output value of the phase interpolation unit with the state of being opened is realized by the synthesis of the output signals of the phase interpolation unit.
Fig. 2 is a schematic circuit diagram of a linear phase interpolator according to an embodiment of the present invention, and as shown in fig. 2, each phase interpolation unit includes the following structure: two identical load resistors, a first load resistor RL1And a second load resistor RL2Wherein the first load resistance RL1And a second load resistor RL2Are respectively connected with a power supply, and the first load resistor RL1And the second load resistor RL2As a first output terminal and a second output terminal of the phase interpolation unit, respectively; the function of the load resistor is to convert the interpolated current into corresponding interpolated voltage to form voltage waveform output.
Eight identical amplifier tubes, wherein: the drains of the first amplifying tube M1, the third amplifying tube M3, the fifth amplifying tube M5 and the seventh amplifying tube M7 are all connected with the first load resistor RL1Are connected with each other; the drains of the second amplifying tube M2, the fourth amplifying tube M4, the sixth amplifying tube M6 and the eighth amplifying tube M8 are all connected with the second load resistor RL2Are connected with each other; the gates of the first amplifying tube M1 and the fourth amplifying tube M4 share a first differential clock signal; the gates of the second amplifying tube M2 and the third amplifying tube M3 share a second differential clock signal; the gates of the fifth amplifying tube M5 and the eighth amplifying tube M8 share a third differential clock signal; the gates of the sixth amplifying tube M6 and the seventh amplifying tube M7 share a fourth differential clock signal; the first differential clock signal, the second differential clock signal, the third differential clock signal, and the fourth differential clock signal are orthogonal four paths of differential clock signals, i.e. X in fig. 2P(i)、XN(i)、YP(i)、YN(i) And i represents the differential clock signal corresponding to the ith phase interpolation unit. In a phase interpolator with 2 sets of differential clock signals input, the 2 sets of differential clock signals are in quadrature, each adjacent clock beingThe phase difference of the signals is 90 °. The phases of the four orthogonal differential clock signals are generally the signals of the same clock signal at phases of 0 °, 90 °, 180 °, and 270 °, wherein the phase difference between the first differential clock signal and the second differential clock signal is 180 °, and the phase difference between the third differential clock signal and the fourth differential clock signal is 180 °.
Four identical switching tubes, wherein: the sources of the first amplifying tube M1 and the second amplifying tube M2 are both connected with the drain of the first switching tube M9; the sources of the third amplifying tube M3 and the fourth amplifying tube M4 are both connected with the drain of the second switching tube M10; the sources of the fifth amplifying tube M5 and the sixth amplifying tube M6 are both connected with the drain of a third switching tube M11; the sources of the seventh amplifying tube M7 and the eighth amplifying tube M8 are both connected with the drain of the fourth switching tube M12; the gates of the first switch tube M9, the second switch tube M10, the third switch tube M11 and the fourth switch tube M12 are respectively connected to four paths of differential carrier modulation signals. The carrier modulation signal determines the phase value of the output signal, and the carrier modulation signal determines the current flowing through the switching tube, so that the amplitude of the input differential clock signal is changed, and the difference of the phases of the synthesized signals is realized. Namely, the weight proportion of the differential clock signal is changed, and the phase output is changed, so that the whole process of weighted interpolation is completed. Each phase interpolation unit in this embodiment only accesses one of the bits in the carrier modulated signal, and depending on whether the control bit is "1" or "0", one of two states, on or off, is achieved.
The source electrodes of the first switch tube and the second switch tube are connected with a first equal current source, and the source electrodes of the third switch tube and the fourth switch tube are connected with a second equal current source; the equivalent current source is used for providing current, the magnitude of the current is controlled by the switch tube and is reflected to the output signal.
In one embodiment, the interpolator further comprises: a clock circuit for generating the quadrature four-way differential clock signals, the clock circuit comprising: a clock source for generating a clock signal; the frequency division sub-circuit is used for generating two paths of orthogonal clock sub-signals from the clock signals; and the phase shifting sub-circuit is used for converting each path of clock sub-signal into two paths of differential clock signals. Through the circuits, four paths of differential clock signals are generated, the phases of the four paths of differential clock signals are respectively 0 degrees, 90 degrees, 180 degrees and 270 degrees, wherein the phase difference between the first differential clock signal and the second differential clock signal is 180 degrees, and the phase difference between the third differential clock signal and the fourth differential clock signal is 180 degrees. By accumulating the outputs of the above clock signals, an output signal of a desired phase is realized.
In one embodiment, each of the equivalent current sources comprises: the grid electrode of the amplifying triode is connected with a bias voltage source, the source electrode of the amplifying triode is grounded, and the drain electrode of the amplifying triode is used for providing current for the connected devices; the bias voltage source is used for providing a bias voltage Vbias. The equivalent current source is used to provide current, and as can be seen from fig. 2, the current flowing through the amplifying transistors (M13 and M14) is related to the current of the first switch tube, the second switch tube, the third switch tube and the fourth switch tube, i.e. controlled by the gate voltage of the above switch tubes. The equivalent current source in the embodiment can ensure that the current values of the switching tube and the amplifying tube are kept in a linear working interval.
In one embodiment, the output signal of the interpolator is a superposition of the output signals of the N phase interpolation units, and includes:
wherein VoutVout (i) is the output of the ith phase interpolation unit, which is the output signal of the interpolator. The output vout (i) of the aforementioned single phase interpolation unit depends on whether the bit corresponding to the carrier modulation signal is "1" or "0", and the differential clock signal of the gate of the amplifier tube.
In one embodiment, the value of N is 127. When the value of N is too small, the interpolation accuracy may be insufficient. And if the value of N is too large, the complexity of interpolation current is obviously increased. The embodiment preferably has 127 bits, and can cover the precision requirement under most use scenes.
In one embodiment of the present invention, the substrate is,the four paths of differential carrier modulation signals are binary signals with K bits, wherein the K and the N have the following relations: n is 2K-1. The phase value of the phase interpolated output signal is controlled by the carrier modulated signal. When a binary signal of K bits is selected, 2 can be generatedKA carrier modulation code corresponding to 2KA phase value.
In one embodiment, the interpolator further comprises a decoding circuit for encoding the K-bit binary signal into an N-bit thermometer code. As previously described, the output Vout (i) of a single phase interpolation unit depends on whether the bit corresponding to the carrier modulated signal is a "1" or a "0", and when the carrier modulated signal determines the phase to be generated by the interpolator circuit, the binary signal is encoded into an N-bit thermometer code, the number of open phase interpolation units N is determined by the number of "1" s in the thermometer code, and further by
Obtaining the output signal V of the interpolatorout。
The following is a description of the operating state of the aforementioned interpolator to further understand the embodiments by those skilled in the art. The specific input and output signals are described as follows:
1) after passing through a 1/2 frequency divider, a local clock signal outputs I, Q two-path orthogonal four-path differential clock signal VIP、VIN、VQP、VQNThe amplifying tubes M1, M2, M3, M4, M5, M6, M7 and M8 are driven respectively. And M1-M2-M3-M4-M5-M6-M7-M8.
2) Differential carrier modulated digital signal XP(i)、XN(i)、YP(i)、YN(i) And respectively controlling the on and off of M9, M10, M11 and M12. And M9-M10-M11-M12.
3)VbiasM13 and M14 are connected to realize a medium current source I0 in the phase interpolator. And M13 ═ M14.
4) Vout (i) is a differential carrier modulated digital signal XP(i)、XN(i)、YP(i)、YN(i) Through the scheme, the phase is insertedThe valuator phase modulates the signal. Load resistance RL1＝RL2。
5) i takes the value of N, so the final modulation signal
Therefore, this embodiment designs an N-way parallel phase interpolator circuit array, and implements carrier modulation digital signal X by a thermometer encoderP(i)、XN(i)、YP(i)、YN(i) Thereby finally achieving phase modulation of the carrier signal.
The mathematical principle derivation formula is as follows:
from fig. 1, N parallel output voltages can be obtained:
Vout＝AvI*VIP+AvQ*VQP (7)
the following can be obtained by a half-circuit method:
AvI＝gmI*RL1 (8)
AvQ＝gmQ*RL2 (9)
in FIG. 2, gmTo amplify the gate-to-output increased transconductance of the tube:
wherein:
Coxis a unit area oxidized into a capacitor;
μ0is the electron mobility;
I+and I-Flow through quiet passages in M9 and M10, respectivelyThe current of state.
1. When X is presentP<i>And XN<i>When the middle and the middle are high level, M9 and M10 are turned on simultaneously, wherein the current flowing through the M9 and the M10 are the same, and I is the same+And I-Are all I0And/2, when:
gmi＝0 (11)
2. when X is presentP<i>Is at a high level, XN<i>At low level, I+Is I0, I-Is 0, at this time:
3. when XP<i>At a low level, XN<i>At a high level, I+Is 0, I-I0, at this time:
because M3 is M1
In the scheme, a thermometer code mode is adopted, and if i is taken as N, N unit modules (phase interpolation units) in the figure 2 are required. The total output gain of all cells in the X array is:
by encoding, digital signals XPi and XNi can only be 0 or 1.
The same can get:
because: rL2＝RL1R, obtained from formulas (8) and (9):
according to equation (7), again because of VIPAnd VQPIs a quadrature signal generated by the local clock, so the output of the phase interpolator is as in equation (19)
The encoding mode of the thermometer encoder is that:
since the modulation signal X/Y for controlling the local oscillator in the scheme is obtained by the digital phase signal through the CORDIC algorithm, the phase is originally associated with
In sine and cosine correspondence, substituting equations (20) and (2) into (19) can result in:
comparing equation (21) with equation (3), it can be found that Vout (t) is the phase modulation signal, and the weight control signal satisfies a1 2+a2 2＝1。
Meanwhile, according to the formula (7), substituting the formulas (17) and (18) can obtain the phase of the output circuit:
therefore, it is not only easy to use
Therefore, as shown in equation (23), the present embodiment realizes that the phase of the output circuit is controlled by the control signal X inputted into N pathsP(i)、XN(i)、YP(i)、YN(i) The purpose of linear phase modulation is achieved.
Through the embodiment, the phase modulator with good linearity can be realized, the direct-current static working point is not influenced by the modulation signal, and the amplitude of the output signal of the phase interpolator is constant.
Fig. 3 is a schematic structural diagram of a linear phase interpolation chip according to an embodiment of the present invention, as shown in fig. 3. In the present embodiment, there is also provided a linear phase interpolation chip configured to include the aforementioned linear phase interpolator. The circuit structure of the linear phase interpolator is usually packaged in a linear phase interpolation chip, so that the linear phase interpolator has the advantages of integration, simplicity and easiness in use. And the external signal is accessed and the phase modulation signal is output by externally providing a pin form. Further, the chip provides pins comprising: k input pins for receiving carrier modulation signal input; that is, receiving phase information to be generated, when its input is K input pins in parallel, it is possible to realize 2 between phases of input differential clock signalsKAnd (4) interpolating. A differential clock signal input pin for receiving a differential clock signal input, specifically the input of the differential clock signal, to provide a clock reference for the interpolator; and the output pin is used for outputting an output signal of the chip, and the output signal is the output of the interpolator.
In an embodiment, a data clock recovery circuit is further provided, where the data clock recovery circuit includes the aforementioned linear phase interpolator or the aforementioned linear phase interpolation chip. Specifically, the phase interpolator may generate a weight setting signal based on the carrier modulation signal, and the signal generator of the phase interpolator may generate the phase interpolation clock signal based on the weight setting signal. The data clock recovery circuit adopting the linear phase interpolator or the linear phase interpolation chip has the advantages of high precision and simple circuit structure.
The embodiment of the invention does not need triangular wave approximation, so the amplitude of the output signal of the phase interpolator is constant; the implementation mode also ensures that the direct current static working point of the output node is not influenced by the modulation signal, simultaneously leads the linearity of the open-loop modulator to be more ideal, and can simultaneously support the modulation modes with higher requirements on the linearity, such as BPSK, QPSK, 16QAM and the like.
Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, the embodiments of the present invention are not limited to the details of the above embodiments, and various simple modifications can be made to the technical solutions of the embodiments of the present invention within the technical idea of the embodiments of the present invention, and the simple modifications all belong to the protection scope of the embodiments of the present invention.
It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, the embodiments of the present invention do not describe every possible combination.
Those skilled in the art will understand that all or part of the steps in the method according to the above embodiments may be implemented by a program, which is stored in a storage medium and includes several instructions to enable a single chip, a chip, or a processor (processor) to execute all or part of the steps in the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
In addition, any combination of different implementation manners of the embodiments of the present invention can be performed, and the embodiments of the present invention should be considered as disclosed in the embodiments of the present invention as long as the combination does not depart from the idea of the embodiments of the present invention.
Claims (10)
1. A linear phase interpolator, characterized in that the linear phase interpolator comprises:
n parallel phase interpolation units, each phase interpolation unit is used for selecting a corresponding differential clock signal from the multi-path differential clock signals according to the carrier modulation signal as an output signal of the phase interpolation unit;
and the accumulation unit is used for superposing the output signals of the N paths of phase interpolation units to be used as the output signals of the linear phase interpolator.
2. The linear phase interpolator of claim 1, wherein the plurality of differential clock signals are orthogonal first, second, third, and fourth differential clock signals; the carrier modulation signal is a four-way differential carrier modulation signal;
each phase interpolation unit comprises:
two identical load resistances: the first ends of the first load resistor and the second load resistor are respectively connected with a power supply, and the second ends of the first load resistor and the second load resistor are respectively used as a first output end and a second output end of the phase interpolation unit;
eight identical amplifier tubes: the drain electrodes of the first amplifying tube, the third amplifying tube, the fifth amplifying tube and the seventh amplifying tube are all connected with the second end of the first load resistor; the drain electrodes of the second amplifying tube, the fourth amplifying tube, the sixth amplifying tube and the eighth amplifying tube are all connected with the second end of the second load resistor; the gates of the first amplifying tube and the fourth amplifying tube share the first differential clock signal, the gates of the second amplifying tube and the third amplifying tube share the second differential clock signal, the gates of the fifth amplifying tube and the eighth amplifying tube share the third differential clock signal, and the gates of the sixth amplifying tube and the seventh amplifying tube share the fourth differential clock signal;
four identical switching tubes: the source electrodes of the first amplifying tube and the second amplifying tube are connected with the drain electrode of the first switching tube, the source electrodes of the third amplifying tube and the fourth amplifying tube are connected with the drain electrode of the second switching tube, the source electrodes of the fifth amplifying tube and the sixth amplifying tube are connected with the drain electrode of the third switching tube, and the source electrodes of the seventh amplifying tube and the eighth amplifying tube are connected with the drain electrode of the fourth switching tube; the grid electrodes of the first switching tube, the second switching tube, the third switching tube and the fourth switching tube are respectively connected to the four paths of differential carrier modulation signals; and
two identical equal current sources: the source electrodes of the first switch tube and the second switch tube are connected with the first equi-value current source, and the source electrodes of the third switch tube and the fourth switch tube are connected with the second equi-value current source.
3. The linear phase interpolator of claim 2, further comprising: a clock circuit for generating the quadrature four-way differential clock signals, the clock circuit comprising:
a clock source for generating a clock signal;
the frequency division sub-circuit is used for generating two paths of orthogonal clock sub-signals from the clock signals; and
and the phase shifting sub-circuit is used for converting each path of clock sub-signal into two paths of differential clock signals.
4. The linear phase interpolator of claim 2, wherein each of the equivalent current sources comprises:
the grid electrode of the amplifying triode is connected with a bias voltage source, the source electrode of the amplifying triode is grounded, and the drain electrode of the amplifying triode is used for providing current for the connected devices;
the bias voltage source is used for providing bias voltage.
5. The linear phase interpolator of any of claims 1-4, wherein N is 127.
6. The linear phase interpolator of claim 2, wherein said four differential carrier modulated signals are each K-bit binary signals, wherein K and N have the following relationship:
N＝2K-1。
7. the linear phase interpolator of claim 6 further comprising a decoding circuit for encoding said K-bit binary signal as an N-bit thermometer code.
8. A linear phase interpolation chip, characterized in that the linear phase interpolation chip is configured to comprise the linear phase interpolator of any of claims 1 to 7.
9. The linear phase interpolation chip of claim 8, wherein the linear phase interpolation chip comprises:
k input pins for receiving carrier modulation signal input;
a differential clock signal input pin for receiving a differential clock signal input; and
and the output pin is used for outputting the output signal of the linear phase interpolation chip.
10. A data clock recovery circuit comprising the linear phase interpolator of any of claims 1 to 7 or the linear phase interpolation chip of any of claims 8 to 9.
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| CN113098453A (en) * | 2021-04-06 | 2021-07-09 | 无锡中微亿芯有限公司 | High-linearity phase interpolation circuit |
| TWI763411B (en) * | 2021-03-31 | 2022-05-01 | 瑞昱半導體股份有限公司 | Linearity test method and system for chip, and linearity signal providing device |
| CN115333513A (en) * | 2022-07-28 | 2022-11-11 | 灿芯半导体(苏州)有限公司 | Phase interpolation circuit with good linearity |
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| TWI763411B (en) * | 2021-03-31 | 2022-05-01 | 瑞昱半導體股份有限公司 | Linearity test method and system for chip, and linearity signal providing device |
| CN113098453A (en) * | 2021-04-06 | 2021-07-09 | 无锡中微亿芯有限公司 | High-linearity phase interpolation circuit |
| CN113098453B (en) * | 2021-04-06 | 2022-02-18 | 无锡中微亿芯有限公司 | Phase interpolation circuit |
| US11791827B2 (en) | 2021-04-06 | 2023-10-17 | Wuxi Esiontech Co., Ltd. | Phase interpolation circuit with high linearity |
| CN115333513A (en) * | 2022-07-28 | 2022-11-11 | 灿芯半导体(苏州)有限公司 | Phase interpolation circuit with good linearity |
| CN115333513B (en) * | 2022-07-28 | 2023-09-01 | 灿芯半导体(苏州)有限公司 | Phase interpolation circuit with good linearity |
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