CN112164678B - Semiconductor package and manufacturing method thereof - Google Patents
Semiconductor package and manufacturing method thereof Download PDFInfo
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- CN112164678B CN112164678B CN202011034805.XA CN202011034805A CN112164678B CN 112164678 B CN112164678 B CN 112164678B CN 202011034805 A CN202011034805 A CN 202011034805A CN 112164678 B CN112164678 B CN 112164678B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 258
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 81
- 238000000034 method Methods 0.000 claims description 43
- 229910000679 solder Inorganic materials 0.000 claims description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 238000004806 packaging method and process Methods 0.000 claims description 3
- 229910000831 Steel Inorganic materials 0.000 claims description 2
- 239000011521 glass Substances 0.000 claims description 2
- 239000010959 steel Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 13
- 230000007423 decrease Effects 0.000 description 4
- 238000012536 packaging technology Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
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- 238000006243 chemical reaction Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000013473 artificial intelligence Methods 0.000 description 1
- 229920006336 epoxy molding compound Polymers 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15172—Fan-out arrangement of the internal vias
- H01L2924/15174—Fan-out arrangement of the internal vias in different layers of the multilayer substrate
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The invention discloses a semiconductor package and a manufacturing method thereof. The manufacturing method of the semiconductor package comprises the following steps: providing a first substrate; providing a first wiring structure on the first substrate; the first wiring structure includes at least two first wiring layers; providing at least one second wiring structure; electrically connecting a plurality of the second wiring structures with a side of the first wiring structure facing away from the first substrate; each second wiring structure comprises at least two second wiring layers; providing at least one semiconductor element; each semiconductor element comprises a plurality of pins; and arranging one side of the semiconductor element, on which the pins are arranged, on one side of the second wiring structure, which is away from the first substrate. The embodiment of the invention can improve the utilization rate of the wafer and reduce the cost.
Description
Technical Field
The invention relates to the technical field of display, in particular to a semiconductor package and a manufacturing method thereof.
Background
Among the semiconductor technologies, the semiconductor packaging technology plays an important role in the development of the semiconductor industry. With the development of artificial intelligence, 5G technology, smart phone, and other technologies, the requirements for semiconductor packaging technology are also increasing, and the semiconductor packaging needs to achieve smaller overall dimensions, lighter weight, thinner, more pins, high reliability, and lower cost.
In the prior art, a wafer level packaging technology is mostly adopted, and a wafer is used as a substrate for carrying out a chip packaging process, but the wafer level packaging technology has higher cost, the utilization rate of the wafer is lower, and the cost is increased.
Disclosure of Invention
The invention provides a semiconductor package and a manufacturing method thereof, which can improve the utilization rate of a wafer and reduce the cost.
In a first aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor package, including:
providing a first substrate;
providing a first wiring structure on the first substrate; the first wiring structure comprises at least two first wiring layers, and a first insulating layer is arranged between every two adjacent first wiring layers; the first insulating layer comprises a plurality of first through holes, and two adjacent first wiring layers are electrically connected through the first through holes;
providing at least one second wiring structure; each second wiring structure comprises at least two second wiring layers; a second insulating layer is arranged between two adjacent second wiring layers of the same second wiring structure, the second insulating layer comprises a plurality of second through holes, and the two adjacent second wiring layers are electrically connected through the second through holes;
electrically connecting a plurality of the second wiring structures with a side of the first wiring structure facing away from the first substrate;
providing at least one semiconductor element; each semiconductor element comprises a plurality of pins;
and arranging one side of the semiconductor element, on which the pins are arranged, on one side of the second wiring structure, which is away from the first substrate.
In a second aspect, an embodiment of the present invention provides a semiconductor package formed by any one of the methods for manufacturing a semiconductor package provided in the first aspect. The semiconductor package includes:
a first wiring structure; the first wiring structure comprises at least two first wiring layers, and a first insulating layer is arranged between every two adjacent first wiring layers; the first insulating layer comprises a plurality of first through holes, and two adjacent first wiring layers are electrically connected through the first through holes;
at least one second wiring structure; each second wiring structure comprises at least two second wiring layers, and a second insulating layer is arranged between every two adjacent second wiring layers; the second insulating layer comprises a plurality of second through holes, and two adjacent layers of second wiring layers are electrically connected through the second through holes; a plurality of the second wiring structures are located on one side of the first wiring structure; each of the second wiring structures is electrically connected with the first wiring structure;
at least one semiconductor element, each semiconductor element including a plurality of pins; the semiconductor element is positioned on one side of the second wiring structure, which is away from the first wiring structure, and is electrically connected with the first wiring structure.
According to the technical scheme provided by the embodiment of the invention, at least one manufactured second wiring structure is arranged on one side of the first wiring structure, which is away from the first substrate, and is electrically connected with the first wiring structure, and at least one manufactured semiconductor element is arranged on one side of the second wiring structure, which is away from the first substrate, and is electrically connected with the first wiring structure through the second wiring structure. Since the second wiring structures are independent of each other, when designing the second wiring structure mother board, the distance between the adjacent second wiring structures does not need to be considered, and only the distance between the adjacent second wiring structures needs to be adjusted after the second wiring structure mother board is cut to form a plurality of independent second wiring structures. If the second wiring structure is formed by adopting the wafer-level process, when designing the second wiring structure mother board, the spacing limitation between the adjacent second wiring structures can be ignored, and the spacing between the adjacent second wiring structures in the second wiring structure mother board is smaller, so that the number of the second wiring structures in the second wiring structure mother board on a single wafer is increased, the utilization rate of the wafer is further increased, and the production cost is reduced.
Drawings
In order to more clearly illustrate the technical solution of the exemplary embodiments of the present invention, a brief description is given below of the drawings required for describing the embodiments. It is obvious that the drawings presented are only drawings of some of the embodiments of the invention to be described, and not all the drawings, and that other drawings can be made according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic top view of a wafer according to the prior art;
FIG. 2 is a schematic cross-sectional view of a semiconductor package formed by steps of a conventional method for fabricating a semiconductor package;
fig. 3 is a flow chart of a method for manufacturing a semiconductor package according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a semiconductor package formed by steps of a method for manufacturing a semiconductor package according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a semiconductor package formed by steps of a method for manufacturing a semiconductor package according to another embodiment of the present invention;
fig. 6 is a flowchart illustrating a method for manufacturing a semiconductor package according to another embodiment of the present invention;
fig. 7 is a schematic structural diagram of a semiconductor package formed by steps of a method for manufacturing a semiconductor package according to another embodiment of the present invention;
fig. 8 is a schematic flow chart of a method for manufacturing a second wiring structure according to an embodiment of the present invention;
fig. 9 is a schematic structural diagram of a second wiring structure formed by steps of a method for manufacturing a second wiring structure according to an embodiment of the present invention;
fig. 10 is a schematic structural diagram of a semiconductor package formed by steps of a method for manufacturing a semiconductor package according to another embodiment of the present invention;
fig. 11 is a schematic structural diagram of a semiconductor package according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram of another semiconductor package according to an embodiment of the present invention.
Detailed Description
The present application is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the application and not limiting thereof. It should be further noted that, for convenience of description, only some, but not all of the structures related to the present application are shown in the drawings.
Fig. 1 is a schematic top view of a wafer in the prior art, fig. 2 is a schematic cross-sectional structure of a semiconductor package formed by steps of a method for manufacturing a semiconductor package, and fig. 2 is a cross-sectional structure of the semiconductor package along AA' in fig. 1. Referring to fig. 1 and 2, the conventional method for manufacturing a semiconductor package includes:
s11, a plurality of semiconductor elements 11 are placed on the wafer 12.
S12, molding the semiconductor element 11 to form a first plastic layer 13; the first molding layer 13 is polished to expose the leads of the semiconductor device 11.
S13, a plurality of wiring layers 14 having high accuracy are sequentially formed on the semiconductor element 11.
Specifically, in the prior art, the multilayer wiring layers 14 are required to be directly fabricated on the wafer 12 in sequence by adopting a wafer-level process, the precision of the side, close to the semiconductor element 11, of the multilayer wiring layers 14 is higher, a certain distance exists between the high-precision multilayer wiring layers 14 electrically connected with the adjacent semiconductor element 11, the wafer 12 is wasted, and the utilization rate of the wafer 12 is lower.
In view of this, the method for manufacturing a semiconductor package according to the embodiment of the present invention may be applicable to manufacturing a package including a plurality of semiconductor elements. Fig. 3 is a schematic flow chart of a method for manufacturing a semiconductor package according to an embodiment of the present invention, and fig. 4 is a schematic structural diagram of a semiconductor package formed by steps of the method for manufacturing a semiconductor package according to the embodiment of the present invention, where, as shown in fig. 3, the method for manufacturing a semiconductor package includes:
s110, providing a first substrate.
Illustratively, as depicted in fig. 4, a first substrate 110 is provided, which may optionally be used under a panel-level process, such as: the first substrate may be glass, copper plate or steel plate, and compared with the substrate under the wafer level process, the substrate under the panel level process has larger size, and the panel level process is beneficial to realizing the manufacture of more semiconductor packages on the basis of the larger substrate, thereby being beneficial to the mass production of the semiconductor packages.
S120, a first wiring structure is provided on the first substrate.
The first wiring structure comprises at least two first wiring layers, and a first insulating layer is arranged between every two adjacent first wiring layers; the first insulating layer comprises a plurality of first through holes, and two adjacent first wiring layers are electrically connected through the first through holes.
As illustrated in fig. 4, the first wiring structure 120 is disposed on the first substrate 110, the first wiring structure 120 includes three first wiring layers 121, and a first insulating layer 122 is disposed between two adjacent first wiring layers 121; the first insulating layer 122 includes a plurality of first via holes 123, and two adjacent first wiring layers 121 are electrically connected through the first via holes 123. The accuracy of the first wiring layer 121 gradually increases and the line width gradually decreases along the direction perpendicular to the first substrate 110 and along the direction in which the first substrate 110 points to the first wiring structure 120, which is advantageous for continuing the arrangement of the second wiring structure 130 with higher accuracy on the first wiring structure 120. Fig. 4 exemplarily shows that the first wiring structure 120 includes three first wiring layers 121, and in practical applications, the number of layers of the first wiring layers 121 may be determined according to the size of the semiconductor package, the size of the semiconductor element 140, and the process accuracy.
S130, at least one second wiring structure is provided.
Wherein each of the second wiring structures includes at least two second wiring layers; a second insulating layer is arranged between two adjacent second wiring layers of the same second wiring structure, the second insulating layer comprises a plurality of second through holes, and the two adjacent second wiring layers are electrically connected through the second through holes.
Illustratively, as shown in fig. 4, two second wiring structures 130 are provided, wherein each second wiring structure 130 includes three layers of second wiring layers 131; a second insulating layer 132 is disposed between two adjacent second wiring layers 131 of the same second wiring structure 130, and the second insulating layer 132 includes a plurality of second through holes 133, and the two adjacent second wiring layers 131 are electrically connected through the second through holes 133. The accuracy of the second wiring layer 131 gradually increases and the line width gradually decreases along the direction perpendicular to the first substrate 110 and along the direction in which the first wiring structure 120 points to the second wiring structure 130, which is advantageous for continuing the arrangement of the semiconductor element 140 on the second wiring structure 130. Fig. 4 exemplarily provides two second wiring structures 130, and each second wiring structure 130 includes three layers of second wiring layers 131, and in practical applications, the number of second wiring structures 130 may be flexibly set according to the number of semiconductor elements 140, and the number of layers of the second wiring layers 131 may be determined according to the size of the semiconductor package, the size of the semiconductor elements 140, and the process accuracy.
Specifically, the spacing between adjacent connection points on the side of the first wiring structure 120 adjacent to the second wiring structure 130 may limit the spacing between adjacent second wiring structures 130. As shown in fig. 4, the spacing between adjacent connection points of the first wiring layer 121 closest to the second wiring structure 130 is S1, and the spacing between adjacent second wiring structures 130 is determined to be S2, and since the second wiring structures 130 in the embodiment of the present invention are independent of each other, when designing the second wiring structure master, the spacing between adjacent second wiring structures need not be considered, and only after cutting the second wiring structure master to form a plurality of independent second wiring structures 130, the spacing between adjacent second wiring structures 130 is set to S2. If the second wiring structure 130 is formed by adopting the wafer-level process, when designing the second wiring structure mother board, the spacing limitation between the adjacent second wiring structures can be ignored, the spacing between the adjacent second wiring structures in the second wiring structure mother board is smaller, and the spacing between the adjacent second wiring structures on the second wiring structure mother board can be reduced, so that the number of the second wiring structures in the second wiring structure mother board on a single wafer is increased, the utilization rate of the wafer is further increased, and the production cost is reduced.
And S140, electrically connecting a plurality of second wiring structures with one side of the first wiring structure, which is away from the first substrate.
Illustratively, as shown in fig. 4, a plurality of second wiring structures 130 are electrically connected to a side of the first wiring structure 120 facing away from the first substrate 110, and the second wiring structures 130 are electrically connected to one semiconductor element 140 in a one-to-one correspondence. In other embodiments, two or more semiconductor elements 140 may be electrically connected to one second wiring structure 130, which is not particularly limited in comparison.
S150, providing at least one semiconductor element; each semiconductor element includes a plurality of pins.
Illustratively, as shown in fig. 4, at least one semiconductor element 140 is provided, each semiconductor element 140 comprising two pins 141, the pins 141 being for electrical connection with the second wiring structure 130. The semiconductor device 140 may be a bare die fabricated on a wafer using wafer level processing. In other embodiments, each semiconductor element 140 may include three or more pins 141, which is not particularly limited in this application.
And S160, arranging one side of the semiconductor element provided with the pins on one side of the second wiring structure away from the first substrate.
As illustrated in fig. 4, an exemplary side of the semiconductor element 140 on which the pins 141 are disposed is disposed on a side of the second wiring structure 130 facing away from the first substrate 110. The second wiring structure 130 has the smallest line width and highest accuracy of the second wiring layer 131 closest to the semiconductor element 140, and the larger line width and smaller accuracy of the second wiring layer 131 farther from the semiconductor element 140, so that the size of the second wiring structure 130 is larger than the size of the semiconductor element 140. The first wiring structure 120 is located at a side of the second wiring structure 130 facing away from the semiconductor element 140, and the first wiring layer 121 of the first wiring structure 120 closest to the first substrate 110 has a maximum line width and a minimum precision, and the line width of the first wiring layer 121 farther from the semiconductor element 140 is larger and the precision is smaller, so that the size of the first wiring structure 120 is larger than the size of all the second wiring structures 130 electrically connected to the first wiring structure 120, that is, the size of the semiconductor element 140 is smaller than the size of the semiconductor package.
According to the technical scheme provided by the embodiment of the invention, at least one manufactured second wiring structure is arranged on one side of the first wiring structure, which is away from the first substrate, and is electrically connected with the first wiring structure, and at least one manufactured semiconductor element is arranged on one side of the second wiring structure, which is away from the first substrate, and is electrically connected with the first wiring structure through the second wiring structure. Since the second wiring structures are independent of each other, when designing the second wiring structure mother board, the distance between the adjacent second wiring structures does not need to be considered, and only the distance between the adjacent second wiring structures needs to be adjusted after the second wiring structure mother board is cut to form a plurality of independent second wiring structures. If the second wiring structure is formed by adopting the wafer-level process, when designing the second wiring structure mother board, the spacing limitation between the adjacent second wiring structures can be ignored, and the spacing between the adjacent second wiring structures in the second wiring structure mother board is smaller, so that the number of the second wiring structures in the second wiring structure mother board on a single wafer is increased, the utilization rate of the wafer is further increased, and the production cost is reduced.
It should be noted that fig. 3 and fig. 4 only show that one semiconductor package includes a plurality of semiconductor elements 140, and when the semiconductor package needs to perform a plurality of functions, for example, the semiconductor package performs the functions of analog-to-digital conversion and digital signal processing, the semiconductor elements that perform the analog-to-digital conversion and the semiconductor elements that perform the digital signal processing may be packaged together, thereby saving space. In practical applications, the semiconductor package may only perform a single function, so the semiconductor package may include one semiconductor element, and the semiconductor package is prepared as shown in fig. 5, where fig. 5 illustrates two semiconductor packages, and adjacent packages are insulated from each other.
Optionally, with continued reference to fig. 4, the line width of the second wiring layer 131 is smaller than the line width of the first wiring layer 121.
Illustratively, as shown in fig. 4, the distance between the pins 141 within the semiconductor element 140 is small and the distance between the connection points of the semiconductor package is large to enable the semiconductor package to be electrically connected to an external circuit. The pitch of the connection points on the first wiring layer 121 closest to the first substrate 110 is the distance between the connection points of the semiconductor package, the pitch of the connection points on the second wiring layer 131 closest to the semiconductor element 140 is the distance between the pins 141, and in order to achieve that the distance between the connection points of the semiconductor package is greater than the distance between the pins 141 in the semiconductor element 140, the line width of the wiring layer gradually increases and the accuracy gradually decreases along the direction in which the semiconductor element 140 points to the first substrate 110 along the direction perpendicular to the first substrate 110, i.e., the line width of the second wiring layer 131 is smaller than the line width of the first wiring layer 121.
Optionally, the semiconductor element includes a first semiconductor element and a second semiconductor element; the vertical projection of the first semiconductor element on the first substrate is larger than the vertical projection of the second semiconductor element on the first substrate. Fig. 6 is a flow chart of a method for manufacturing a semiconductor package according to an embodiment of the present invention, and fig. 7 is a schematic structural diagram of a semiconductor package formed by steps of the method for manufacturing a semiconductor package according to the embodiment of the present invention, where the method for manufacturing a semiconductor package includes:
s110, providing a first substrate.
S120, a first wiring structure is provided on the first substrate.
S130, at least one second wiring structure is provided.
And S140, electrically connecting a plurality of second wiring structures with one side of the first wiring structure, which is away from the first substrate.
S150, providing at least one semiconductor element; each semiconductor element includes a plurality of pins.
As illustrated in fig. 7, the semiconductor element 140 includes a first semiconductor element 140a and a second semiconductor element 140b, and one first semiconductor element 140a and one second semiconductor element 140b are provided, and a vertical projection of the first semiconductor element 140a on the first substrate 110 is greater than a vertical projection of the second semiconductor element 140b on the first substrate 110, that is, a distance between the inner leads 141 of the first semiconductor element 140a is greater than a distance between the inner leads 141 of the second semiconductor element 140 b. Fig. 6 illustrates that the semiconductor element 140 includes one first semiconductor element 140a and one second semiconductor element 140b, and in practical applications, the number of the first semiconductor element 140a and the second semiconductor element 140b is not limited.
S161, disposing a side of the first semiconductor element, on which the pins are disposed, on a side of the first wiring structure, which is away from the first substrate; and arranging one side of the second semiconductor element, on which the pins are arranged, on one side of the second wiring structure, which is away from the first substrate.
Illustratively, as shown in fig. 7, the distance between the inner pins 141 of the first semiconductor element 140a is large enough to match the line width of the first wiring layer 121 closest to the second semiconductor element 140b, and therefore, the side of the first semiconductor element 140a on which the pins are disposed is disposed on the side of the first wiring structure 120 facing away from the first substrate 110, and the first semiconductor element 140a is directly electrically connected to the first wiring structure 120. However, the distance between the inner leads 141 of the second semiconductor element 140b is small and cannot be matched with the line width of the first wiring layer 121, and since the line width of the second wiring layer 131 is smaller than the line width of the first wiring layer 121, the distance between the inner leads 141 of the second semiconductor element 140b can be matched with the line width of the second wiring layer 131, and the side of the second semiconductor element 140b on which the leads are provided is disposed on the side of the second wiring structure 130 facing away from the first substrate 110, and the second semiconductor element 140b is electrically connected to the first wiring structure 120 through the second wiring structure 130.
In the embodiment of the invention, the small-sized semiconductor element is arranged on the side of the second wiring structure 130 away from the first substrate 110, and the large-sized semiconductor element is arranged on the side of the first wiring structure 120 away from the first substrate 110, so that the wiring structures for the semiconductor elements with different sizes can be respectively arranged, and the wiring structure of the large-sized semiconductor element can be simplified.
Optionally, in executing step S140, specific steps include:
and S141, detecting whether each second wiring structure is qualified.
And S142, electrically connecting the qualified second wiring structure with one side of the first wiring structure, which is away from the first substrate.
Specifically, after the second wiring structures are manufactured, detecting whether each second wiring structure is qualified or not, rejecting unqualified second wiring structures, and arranging the qualified second wiring structures on one side of the first wiring structure, which is away from the first substrate, so that the second wiring structures and the first wiring structures are electrically connected. Because the second wiring structures are mutually independent, the damage of a single second wiring structure does not affect other second wiring structures, and decorrelation among the second wiring structures is realized, so that the utilization rate of the second wiring structures is improved.
Alternatively, when step S160 is performed, the setting position of the semiconductor element may also be adjusted according to the position of the second wiring structure.
Specifically, due to the fact that the second wiring structure is manufactured and the positions with offset and errors exist in the process of aligning and electrically connecting the second wiring structures with the first wiring structure, the position of the semiconductor element is adjusted, accuracy of alignment between pins of the semiconductor element and connection points of the second wiring structures can be improved, and accordingly yield of the semiconductor package is improved.
Optionally, fig. 8 is a schematic flow chart of a method for manufacturing a second wiring structure according to an embodiment of the present invention, and fig. 9 is a schematic structural diagram of a second wiring structure formed by steps of the method for manufacturing a second wiring structure according to an embodiment of the present invention, where, as shown in fig. 8, the method for manufacturing a second wiring structure includes:
s131, providing a second substrate.
Illustratively, as shown in fig. 9, a second substrate 134 is provided, and the second substrate 134 may be a wafer used in a wafer level process. The wafer-level process has a smaller line width and higher accuracy than the panel-level process, and thus the second wiring structure 130 having a higher accuracy and a smaller line width can be formed.
S132, arranging at least two second wiring layers on the second substrate, wherein a second insulating layer is arranged between two adjacent second wiring layers; the second insulating layer comprises a plurality of second through holes, and two adjacent layers of second wiring layers are electrically connected through the second through holes so as to form a second wiring structure mother board.
As illustrated in fig. 9, three second wiring layers 131 are provided on the second substrate 134, and a second insulating layer 132 is provided between two adjacent second wiring layers 131; the second insulating layer 132 includes a plurality of second through holes 133, and adjacent two second wiring layers 131 are electrically connected through the second through holes 133 to form the second wiring structure master 130a. Optionally, the second wiring layers 131 formed on the second substrate 134 are sequentially stacked from low to high to match the line width of the first wiring structure 120 and the pitch of the leads 141 in the semiconductor device 140. Fig. 9 illustrates only an exemplary case where three second wiring layers 131 are provided on the second substrate 134, and in practical applications, they are determined according to the size of the semiconductor package, the size of the semiconductor element 140, and the process accuracy.
S133, cutting the second wiring structure mother board, and stripping the second substrate to form a plurality of second wiring structures.
Illustratively, as shown in fig. 9, the second wiring structure master 130a is cut, and the second substrate 134 is peeled off, forming a plurality of second wiring structures 130. After the second wiring structure mother board 130a is cut, a plurality of independent second wiring structures 130 are formed, offset and errors exist in the process of manufacturing the first wiring structure, and the position of the second wiring structure 130 can be flexibly adjusted according to the offset and the errors of the first wiring structure, so that the alignment accuracy between the second wiring structure 130 and the first wiring structure is improved, and the yield of semiconductor packages is improved.
Optionally, after performing as step S160, the method for manufacturing a semiconductor package further includes:
s170, plastic packaging the semiconductor element.
For example, fig. 10 is a schematic structural diagram of a semiconductor package formed by steps of a method for manufacturing a semiconductor package according to another embodiment of the present invention, and after a side of the semiconductor element 140 with the pins 141 is disposed on a side of the second wiring structure 130 facing away from the first substrate 110, the semiconductor element 140 is encapsulated to form an encapsulated structure 150, as shown in fig. 10. The material of the plastic package structure 150 includes an epoxy molding compound, for example, an injection molding process is used to form the plastic package structure 150. Optionally, a plastic package structure 150 is formed on a side of the first wiring structure 120 and the second wiring structure 130 away from the first substrate 110 and around the semiconductor element 140, that is, the plastic package structure 150 encapsulates the semiconductor element 140, and the plastic package structure 150 can protect the semiconductor element 140 and provide a heat dissipation path for the semiconductor element 140.
S180, stripping the first substrate.
And S190, implanting balls on one side of the first wiring structure, which is away from the semiconductor element, to form solder balls.
As shown in fig. 10, the first substrate 110 is peeled off to expose the first wiring layer 121 with the lowest precision, and balls are planted on the side of the first wiring structure 120 away from the semiconductor element 140 to form solder balls 160, so that the solder balls 160 are electrically connected with the first wiring layer 121 with the lowest precision, and the solder balls 160 are electrically connected with the pins 141 of the semiconductor element 140. The solder balls 160 are connection points of the semiconductor package for realizing wire connection of the leads 141 of the semiconductor element 140 with an external circuit. Alternatively, the solder balls 160 may be formed of tin, lead, copper, silver, gold, or the like, or an alloy thereof.
Optionally, after performing step S160, the following steps are further performed:
s1100, cutting the first wiring structure to form a plurality of semiconductor packages; each of the semiconductor packages includes at least one of the semiconductor elements.
Illustratively, dicing the first wiring structure to form a plurality of semiconductor packages, each semiconductor package including two semiconductor elements, if the semiconductor elements are bare, a multi-chip package is formed; if the semiconductor elements are different in size, packages of chips of different sizes can be formed.
Based on the same inventive concept, the embodiment of the invention also provides a semiconductor package formed by adopting the manufacturing method of any semiconductor package provided in the embodiment of the application.
Fig. 11 is a schematic structural diagram of a semiconductor package according to an embodiment of the present invention. As shown in fig. 11, the semiconductor package 100 includes:
the first wiring structure 120, wherein the first wiring structure 120 includes at least two first wiring layers 121, a first insulating layer 122 is disposed between two adjacent first wiring layers 121, the first insulating layer 122 includes a plurality of first through holes 123, and the two adjacent first wiring layers 121 are electrically connected through the first through holes 123.
At least one second wiring structure 130, wherein each second wiring structure 130 includes at least two second wiring layers 131, a second insulating layer 132 is disposed between two adjacent second wiring layers 131, the second insulating layer 132 includes a plurality of second through holes 133, and the two adjacent second wiring layers 131 are electrically connected through the second through holes 133. A plurality of second wiring structures 130 are located at one side of the first wiring structure 120, and each of the second wiring structures 130 is electrically connected to the first wiring structure 120.
At least one semiconductor element 140, each semiconductor element 140 including a plurality of pins 141; the semiconductor element 140 is located on a side of the second wiring structure 130 facing away from the first wiring structure 120, and the semiconductor element 140 is electrically connected to the first wiring structure 120.
Illustratively, as shown in fig. 11, the first wiring structure 120 includes three first wiring layers 121, and each of the second wiring structures 130 includes three second wiring layers 131. The spacing between adjacent connection points of the first wiring structure 120 on the side near the second wiring structure 130 may limit the spacing between adjacent second wiring structures 130. Illustratively, the spacing between adjacent connections on the first wiring layer 121 closest to the second wiring structure 130 is S1, which determines the spacing between adjacent second wiring structures 130 to be S2, and since the second wiring structures 130 in the embodiment of the present invention are independent of each other, when designing the second wiring structure master, the spacing between adjacent second wiring structures need not be considered, and only after cutting the second wiring structure master to form a plurality of independent second wiring structures 130, the spacing between adjacent second wiring structures 130 need be set to S2. If the second wiring structure 130 is formed by adopting the wafer-level process, when designing the second wiring structure mother board, the spacing limitation between the adjacent second wiring structures can be ignored, the spacing between the adjacent second wiring structures in the second wiring structure mother board is smaller, and the spacing between the adjacent second wiring structures on the second wiring structure mother board can be reduced, so that the number of the second wiring structures in the second wiring structure mother board on a single wafer is increased, the utilization rate of the wafer is further increased, and the production cost is reduced.
It should be noted that fig. 11 illustrates that the first wiring structure 120 includes three first wiring layers 121, and each second wiring structure 130 includes three second wiring layers 131, and in practical applications, the number of layers of the first wiring layers 121 and the second wiring layers 131 is not particularly limited.
Alternatively, with continued reference to fig. 11, the line width of the second wiring layer 131 is smaller than the line width of the first wiring layer 121.
Illustratively, as shown in fig. 11, the distance between the pins 141 within the semiconductor element 140 is small and the distance between the connection points of the semiconductor package 100 is large, so that the semiconductor package 100 can be electrically connected to an external circuit. The pitch of the connection points on the first wiring layer 121 most away from the second wiring structure 130 is the distance between the connection points of the semiconductor package 100, the pitch of the connection points on the second wiring layer 131 closest to the semiconductor element 140 is the distance between the pins 141, and in order to achieve that the distance between the connection points of the semiconductor package is greater than the distance between the pins 141 in the semiconductor element 140, the line width of the wiring layer gradually increases and the accuracy gradually decreases along the direction in which the semiconductor element 140 points to the first wiring structure 120 along the direction perpendicular to the plane in which the first wiring structure 120 is located, i.e., the line width of the second wiring layer 131 is smaller than the line width of the first wiring layer 121.
Optionally, fig. 12 is a schematic structural diagram of still another semiconductor package according to an embodiment of the present invention. As shown in fig. 11, the semiconductor element 140 includes a first semiconductor element 140a and a second semiconductor element 140b, and the vertical projection of the first semiconductor element 140a on the plane of the first wiring structure 120 is larger than the vertical projection of the second semiconductor element 140b on the plane of the first wiring structure 120.
Wherein, the side of the first semiconductor element 140a where the pin 141 is disposed is located on the side of the first wiring structure 120 close to the second wiring structure 130, and the first semiconductor element 140a is electrically connected to the first wiring structure 120. The side of the second semiconductor element 140b on which the pins 141 are provided is located on the side of the second wiring structure 130 facing away from the first wiring structure 120, and the second semiconductor element 140b is electrically connected to the first wiring structure 120 through the second wiring structure 130.
As shown in fig. 12, the semiconductor element 140 includes a first semiconductor element 140a and a second semiconductor element 140b, and the vertical projection of the first semiconductor element 140a on the plane of the first wiring structure 120 is greater than the vertical projection of the second semiconductor element 140b on the plane of the first wiring structure 120, that is, the distance between the inner leads 141 of the first semiconductor element 140a is greater than the distance between the inner leads 141 of the second semiconductor element 140 b. The distance between the inner leads 141 of the first semiconductor element 140a is large enough to match the line width of the first wiring layer 121 closest to the second semiconductor element 140b, and thus the first semiconductor element 140a is directly electrically connected to the first wiring structure 120. However, the distance between the inner leads 141 of the second semiconductor element 140b is small and cannot be matched with the line width of the first wiring layer 121, and since the line width of the second wiring layer 131 is smaller than the line width of the first wiring layer 121, the distance between the inner leads 141 of the second semiconductor element 140b can be matched with the line width of the second wiring layer 131, and the second semiconductor element 140b is electrically connected to the first wiring structure 120 through the second wiring structure 130.
In the embodiment of the invention, by disposing the small-sized semiconductor element on the side of the second wiring structure 130 away from the first wiring structure 120 and disposing the large-sized semiconductor element on the side of the first wiring structure 120 away from the first substrate 110, it is possible to dispose the wiring structures for the semiconductor elements of different sizes, respectively, and thus it is possible to simplify the wiring structure of the large-sized semiconductor element.
It should be noted that fig. 12 only illustrates that the semiconductor element 140 includes one first semiconductor element 140a and one second semiconductor element 140b, and in practical applications, the number of the first semiconductor element 140a and the second semiconductor element 140b is not particularly limited.
Alternatively, with continued reference to fig. 11, the line width of the first wiring layer 121 on the side of the first wiring structure 120 close to the second wiring structure 130 is smaller than the line width of the first wiring layer 121 on the side of the first wiring structure 120 far from the second wiring structure 130.
The line width of the second wiring layer 131 of the second wiring structure 130 on the side far from the first wiring structure 120 is smaller than the line width of the second wiring layer 131 of the second wiring structure 130 on the side near the first wiring structure 120.
As shown in fig. 11, the line width of the first wiring layer 121 in the first wiring structure 120 is gradually reduced and the accuracy is gradually increased along the direction perpendicular to the plane of the first wiring structure 120 and along the direction of the first wiring structure 120 toward the wiring structure 130, so that the pitch between the connection points of the semiconductor package 100 can be shortened through the first wiring structure 120, and the connection points of the semiconductor package 100 can be electrically connected with the pins 141 of the semiconductor element 140. Along the direction perpendicular to the plane of the first wiring structure 120 and pointing to the wiring structure 130 along the first wiring structure 120, the line width of the second wiring layer 131 in the second wiring structure 130 is gradually reduced, the precision is gradually increased, the space between the connection points of the semiconductor package 100 is further reduced through the second wiring structure 130, and it is ensured that the connection points of the semiconductor package 100 can be electrically connected with the semiconductor element 140 with a smaller size.
Optionally, with continued reference to fig. 11 and 12, the semiconductor package 100 further includes:
the solder balls 160 are located on the side of the first wiring structure 120 away from the second wiring structure 130, and the solder balls 160 are electrically connected with the first wiring structure 120.
The plastic package structure 150 surrounds at least the semiconductor element 140 and the second wiring structure 130.
As shown in fig. 11 and 12, the first wiring layer 121 on the side of the first wiring structure 120 facing away from the second wiring structure 130 is electrically connected to the solder ball 160, and the solder ball 160 is electrically connected to the first wiring layer 121 with the lowest accuracy, so that the solder ball 160 is electrically connected to the pin 141 of the semiconductor element 140. The solder balls 160 are connection points of the semiconductor package 100 for connecting the leads 141 of the semiconductor element 140 to wires of an external circuit. The plastic package structure 150 surrounds the semiconductor element 140 and the second wiring structure 130, and is capable of protecting the semiconductor element 140 and the second wiring structure 130 and providing a heat dissipation path for the semiconductor element 140. Optionally, the plastic package structure 150 may further surround the first wiring structure 120 to protect the first wiring structure 120.
The foregoing description is only of the preferred embodiments of the invention and the technical principles employed. The present invention is not limited to the specific embodiments described herein, but is capable of numerous modifications, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the invention has been described in connection with the above embodiments, the invention is not limited to the embodiments, but may be embodied in many other equivalent forms without departing from the spirit of the invention, the scope of which is set forth in the following claims.
Claims (9)
1. A method of fabricating a semiconductor package, comprising:
providing a first substrate;
providing a first wiring structure on the first substrate; the first wiring structure comprises at least two first wiring layers, and a first insulating layer is arranged between every two adjacent first wiring layers; the first insulating layer comprises a plurality of first through holes, and two adjacent first wiring layers are electrically connected through the first through holes;
providing a plurality of second wiring structures formed in advance; each second wiring structure comprises at least two second wiring layers; a second insulating layer is arranged between two adjacent second wiring layers of the same second wiring structure, the second insulating layer comprises a plurality of second through holes, and the two adjacent second wiring layers are electrically connected through the second through holes;
wherein a plurality of the second wiring structures are formed by cutting a second wiring structure motherboard and are mutually independent;
electrically connecting a plurality of the second wiring structures with a side of the first wiring structure facing away from the first substrate;
providing at least one semiconductor element; each semiconductor element comprises a plurality of pins;
and arranging one side of the semiconductor element, on which the pins are arranged, on one side of the second wiring structure, which is away from the first substrate.
2. The method of manufacturing a semiconductor package according to claim 1, wherein a line width of the second wiring layer is smaller than a line width of the first wiring layer.
3. The method of manufacturing a semiconductor package according to claim 2, wherein the semiconductor element includes a first semiconductor element and a second semiconductor element; the vertical projection of the first semiconductor element on the first substrate is larger than the vertical projection of the second semiconductor element on the first substrate;
the step of disposing the side of the semiconductor element provided with the pins on the side of the second wiring structure facing away from the first substrate includes:
arranging one side of the first semiconductor element, on which the pins are arranged, on one side of the first wiring structure, which is away from the first substrate; and arranging one side of the second semiconductor element, on which the pins are arranged, on one side of the second wiring structure, which is away from the first substrate.
4. The method of manufacturing a semiconductor package according to claim 1, wherein the electrically connecting the plurality of second wiring structures and the side of the first wiring structure facing away from the first substrate further comprises:
detecting whether each second wiring structure is qualified;
and electrically connecting the qualified second wiring structure with one side of the first wiring structure, which is away from the first substrate.
5. The method according to claim 1, wherein when the side of the semiconductor element on which the leads are provided is disposed on the side of the second wiring structure away from the first substrate, further comprising:
and adjusting the setting position of the semiconductor element according to the position of the second wiring structure.
6. The method of manufacturing a semiconductor package according to claim 1, wherein said providing at least one second wiring structure comprises:
providing a second substrate;
at least two layers of second wiring layers are arranged on the second substrate, and a second insulating layer is arranged between two adjacent layers of second wiring layers; the second insulating layer comprises a plurality of second through holes, and two adjacent layers of second wiring layers are electrically connected through the second through holes so as to form a second wiring structure mother board;
cutting the second wiring structure mother plate, and stripping the second substrate to form a plurality of second wiring structures.
7. The method of manufacturing a semiconductor package according to claim 6, wherein,
the first substrate comprises glass, steel plate or copper plate;
the second substrate includes a wafer.
8. The method according to claim 1, wherein the step of disposing the side of the semiconductor element on which the leads are disposed on the side of the second wiring structure away from the first substrate, further comprises:
plastic packaging the semiconductor element;
stripping the first substrate;
and implanting balls at one side of the first wiring structure, which is away from the semiconductor element, to form solder balls.
9. The method according to claim 1, wherein the step of disposing the side of the semiconductor element on which the leads are disposed on the side of the second wiring structure away from the first substrate, further comprises:
dicing the first wiring structure to form a plurality of the semiconductor packages; each of the semiconductor packages includes at least one of the semiconductor elements.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104600064A (en) * | 2013-10-30 | 2015-05-06 | 台湾积体电路制造股份有限公司 | Chip on Package Structure and Method |
| CN107275240A (en) * | 2017-07-03 | 2017-10-20 | 京东方科技集团股份有限公司 | A kind of chip packaging method and chip-packaging structure |
| CN109216304A (en) * | 2017-06-30 | 2019-01-15 | 台湾积体电路制造股份有限公司 | Semiconductor packages and its manufacturing method |
| CN110120373A (en) * | 2018-02-05 | 2019-08-13 | 日月光半导体制造股份有限公司 | Semiconductor package and its manufacturing method |
| CN111430313A (en) * | 2020-05-11 | 2020-07-17 | 上海天马微电子有限公司 | Semiconductor package and method of manufacturing the same |
| CN111554641A (en) * | 2020-05-11 | 2020-08-18 | 上海天马微电子有限公司 | Semiconductor package and manufacturing method thereof |
| US10756054B1 (en) * | 2019-07-24 | 2020-08-25 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and method for manufacturing the same |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10700008B2 (en) * | 2018-05-30 | 2020-06-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structure having redistribution layer structures |
-
2020
- 2020-09-27 CN CN202011034805.XA patent/CN112164678B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104600064A (en) * | 2013-10-30 | 2015-05-06 | 台湾积体电路制造股份有限公司 | Chip on Package Structure and Method |
| CN109216304A (en) * | 2017-06-30 | 2019-01-15 | 台湾积体电路制造股份有限公司 | Semiconductor packages and its manufacturing method |
| CN107275240A (en) * | 2017-07-03 | 2017-10-20 | 京东方科技集团股份有限公司 | A kind of chip packaging method and chip-packaging structure |
| CN110120373A (en) * | 2018-02-05 | 2019-08-13 | 日月光半导体制造股份有限公司 | Semiconductor package and its manufacturing method |
| US10756054B1 (en) * | 2019-07-24 | 2020-08-25 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and method for manufacturing the same |
| CN111430313A (en) * | 2020-05-11 | 2020-07-17 | 上海天马微电子有限公司 | Semiconductor package and method of manufacturing the same |
| CN111554641A (en) * | 2020-05-11 | 2020-08-18 | 上海天马微电子有限公司 | Semiconductor package and manufacturing method thereof |
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