CN112151594A - Semiconductor structure and forming method thereof - Google Patents
Semiconductor structure and forming method thereof Download PDFInfo
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- CN112151594A CN112151594A CN201910577014.2A CN201910577014A CN112151594A CN 112151594 A CN112151594 A CN 112151594A CN 201910577014 A CN201910577014 A CN 201910577014A CN 112151594 A CN112151594 A CN 112151594A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Abstract
A semiconductor structure and a forming method thereof are provided, wherein the forming method comprises the following steps: providing a substrate, wherein the substrate comprises a substrate and a fin part protruding out of the substrate, a well region is formed in the substrate, and first type ions are arranged in the well region; forming an inversion doping region and a threshold voltage adjusting region in the fin portion, wherein the threshold voltage adjusting region is located on one side of the top of the fin portion, the inversion doping region is located below the threshold voltage adjusting region, a first type of ions are arranged in the threshold voltage adjusting region, and a second type of ions are arranged in the inversion doping region; and forming an isolation structure on the substrate with the exposed fin part, wherein the isolation structure exposes the inversion doping region and the threshold voltage adjusting region. The threshold voltage adjusting region is formed on one side of the top of the fin portion, so that the current density of the top of the fin portion is reduced, the channel of the device is far away from the surface of the fin portion through the inversion doping region, the problem of flicker noise is solved, and the starting voltage of the device meets the performance requirement; in conclusion, the performance of the device is improved through the inversion doping region and the threshold voltage adjusting region.
Description
Technical Field
Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a method for forming the same.
Background
In semiconductor manufacturing, integrated circuit feature sizes continue to decrease with the trend toward very large scale integrated circuits. To accommodate the reduction in feature size, the channel length of MOSFETs has also been correspondingly shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the controllability of the gate to the channel is deteriorated, the difficulty of the gate voltage to pinch off the channel is increased, and the sub-threshold leakage (SCE), which is a so-called short-channel effect, is more likely to occur.
Therefore, in order to better accommodate the reduction of feature sizes, semiconductor processing is gradually beginning to transition from planar MOSFETs to three-dimensional transistors with higher power efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) at least from two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit a short-channel effect; and finfets have better compatibility with existing integrated circuit fabrication relative to other devices.
Disclosure of Invention
Embodiments of the present invention provide a semiconductor structure and a method for forming the same, which improve the performance of a device.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a substrate and a fin part protruding out of the substrate, a well region is formed in the substrate, and first type ions are arranged in the well region; forming an inversion doping region and a threshold voltage adjusting region in the fin portion, wherein the threshold voltage adjusting region is located on one side of the top of the fin portion, the inversion doping region is located below the threshold voltage adjusting region, the threshold voltage adjusting region is provided with first type ions, the inversion doping region is provided with second type ions, and the second type ions are different from the first type ions in conductive types; and forming an isolation structure on the substrate with the exposed fin part, wherein the isolation structure exposes the inversion doping region and the threshold voltage adjusting region.
Optionally, after forming the inversion-type doped region, forming the threshold voltage adjusting region.
Optionally, before forming the inversion doping region, the method further includes: forming an isolation material layer on the substrate exposed out of the fin portion, wherein the isolation material layer covers the side wall of the fin portion; the step of forming the inversion doping region comprises the following steps: and performing inverse ion implantation on the isolation material layer and the top of the fin part.
Optionally, after forming the inversion doping region and before forming the threshold voltage adjusting region, the method further includes: removing the isolation material layer with partial thickness to form an initial isolation layer exposing partial side walls of the fin parts; the step of forming the threshold voltage adjustment region includes: and performing threshold voltage injection on the fin part side wall exposed by the initial isolation layer.
Optionally, the step of forming the isolation structure includes: and after the threshold voltage adjusting region is formed, removing part of the initial isolation layer, and reserving the residual initial isolation layer as the isolation structure.
Optionally, before forming the inversion doping region, the method further includes: performing channel stop injection on the isolation material layer and the top of the fin portion, and forming a penetration prevention area in the fin portion, wherein the penetration prevention area is provided with first type ions; in the step of forming the inversion-type doped region, the inversion-type doped region is positioned above the anti-punch-through region; in the step of forming the isolation structure, the isolation structure covers the side wall of the penetration preventing region.
Optionally, an ion implantation process is used to perform inverse ion implantation on the fin portion to form the inverse doped region.
Optionally, an ion implantation process is used to perform threshold voltage implantation on the fin portion, so as to form the threshold voltage adjusting region.
Optionally, an ion implantation process is used to perform channel stop implantation on the fin portion, so as to form the penetration preventing region.
Optionally, an implantation angle of the ion implantation process is 0 to 7 degrees.
Optionally, the implantation angle of the ion implantation process is 15 to 20 degrees.
Optionally, the process parameters of the inversion ion implantation include: the second type of ions comprise one or more of boron, gallium and indium, the implantation energy is 6KeV to 30KeV, and the implantation dosage is 2E13atom/cm2To 1E15atom/cm2(ii) a Alternatively, the second type of ions comprises one or more of phosphorus, arsenic and antimony, the implantation energy is 15KeV to 50KeV, and the implantation dose is 2E13atom/cm2To 1E15atom/cm2。
Optionally, the process parameters of the threshold voltage implantation include: the first type of ions comprise one or more of phosphorus, arsenic and antimony, the implantation energy is 7KeV to 25KeV, and the implantation dosage is 1E13atom/cm2To 5E14atom/cm2(ii) a Or, the first type ions comprise one or more of boron, gallium and indium, the implantation energy is 3KeV to 15KeV, and the implantation dosage is 1E13atom/cm2To 5E14atom/cm2。
Optionally, in the step of forming the threshold voltage adjusting region, the threshold voltage adjusting region has a preset thickness; in the step of forming the isolation structure, the height of the fin part exposed out of the isolation structure is a preset height; the preset thickness is 1/5-1/3 of the preset height.
Optionally, after the isolation structure is formed, a distance from the top surface of the isolation structure to the bottom surface of the inversion doping region is 0nm to 30 nm.
Optionally, in the step of providing the substrate, a fin mask layer is formed on the top of the fin; in the step of forming the isolation material layer, the isolation material layer exposes the top of the fin portion mask layer; after the threshold voltage adjusting region is formed, the method further comprises the following steps: and removing the fin mask layer.
Correspondingly, an embodiment of the present invention further provides a semiconductor structure, including: the ion implantation device comprises a substrate, wherein a well region is formed in the substrate, and first type ions are arranged in the well region; the fin part protrudes out of the substrate; a threshold voltage adjustment region in the fin, the threshold voltage adjustment region being on a top side of the fin, the threshold voltage adjustment region having the first type of ions therein; an inversion doped region in the fin portion, the inversion doped region being located below the threshold voltage adjustment region, the inversion doped region having a second type of ions therein, the second type of ions being of a different conductivity type than the first type of ions; and the isolation structure is positioned on the substrate with the exposed fin part, and the inversion doping area and the threshold voltage adjusting area are exposed out of the isolation structure.
Optionally, the semiconductor structure further includes: the anti-punch-through area is positioned in the fin part below the anti-punch-through area, and first type ions are arranged in the anti-punch-through area; the isolation structure covers the side wall of the penetration preventing area.
Optionally, the threshold voltage adjusting region has a preset thickness, the height of the fin exposed by the isolation structure is a preset height, and the preset thickness is 1/5 to 1/3 of the preset height.
Optionally, the distance from the top surface of the isolation structure to the bottom surface of the inversion doping region is 0nm to 30 nm.
Optionally, the first type of ions include one or more of phosphorus, arsenic and antimony, and the doping concentration of the threshold voltage adjusting region is 1E18atom/cm3To 3E19atom/cm3(ii) a Or, the first type ions comprise one or more of boron, gallium and indium, and the doping concentration of the threshold voltage adjusting region is 1E18atom/cm3To 3E19atom/cm3。
Optionally, the second type of ions include one or more of phosphorus, arsenic and antimony, and the doping concentration of the inversion doping region is 2E18atom/cm3To 5E19atom/cm3(ii) a Or, the second type ions comprise one or more of boron, gallium and indium, and the doping concentration of the inversion doping region is 2E18atom/cm3To 5E19atom/cm3。
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
according to the embodiment of the invention, the inverted doping region and the threshold voltage adjusting region are formed in the fin part, the threshold voltage adjusting region is positioned on one side of the top of the fin part, the inverted doping region is positioned below the threshold voltage adjusting region, and the threshold voltage adjusting region is formed on one side of the top of the fin part to increase the starting voltage of the top of the low fin part, so that the current density of the top of the fin part is reduced, and the reliability of the device is improved; moreover, by forming the inversion doping region, the channel of the device is far away from the surface of the fin part, so that the problem of flicker noise (noise) is solved, the starting voltage at the position corresponding to the inversion doping region is reduced, and the starting voltage of the device meets the performance requirement; in conclusion, the reliability of the device and the low-frequency noise performance of flicker noise are improved through the inversion doping region and the threshold voltage adjusting region, namely the performance of the device is improved.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure;
fig. 2 to 8 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Detailed Description
Device performance currently remains to be improved. The device performance has yet to be improved in conjunction with a semiconductor structure analysis.
Referring to fig. 1, a schematic diagram of a semiconductor structure is shown.
The semiconductor structure includes: a substrate 10; a fin portion 11 protruding from the substrate 10; a threshold voltage adjusting region 22 located in the fin portion 11; a punch-through prevention region 21 located in the fin 11 below the threshold voltage adjustment region 22; and an isolation structure 12 located on the substrate 10 with the exposed fin portion 11, wherein the isolation structure 12 exposes the threshold voltage adjustment region 22.
The exposed fin 11 of the isolation structure 12 serves as an effective fin for providing a channel of the formed finfet, and the threshold voltage adjusting region 22 is mainly located at a middle position of the effective fin, so that the doping concentration of the threshold voltage adjusting region 22 is lower at a position (shown by a dotted line a in fig. 1) near the top of the fin 11. However, near the top of the fin 11, the electric field strength in the channel is large, and accordingly, the turn-on current at the position is large, and especially, the turn-on current at the top corner of the fin 11 is large, which easily causes the reliability of the device to be degraded, and also causes low-frequency noise to be degraded.
Moreover, since the fin 11 is liable to have a problem of surface defects, a reaction occurs between the device channel and the surface of the fin 11, thereby generating flicker noise.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a substrate and a fin part protruding out of the substrate, a well region is formed in the substrate, and first type ions are arranged in the well region; forming an inversion doping region and a threshold voltage adjusting region in the fin portion, wherein the threshold voltage adjusting region is located on one side of the top of the fin portion, the inversion doping region is located below the threshold voltage adjusting region, the threshold voltage adjusting region is provided with first type ions, the inversion doping region is provided with second type ions, and the second type ions are different from the first type ions in conductive types; and forming an isolation structure on the substrate with the exposed fin part, wherein the isolation structure exposes the inversion doping region and the threshold voltage adjusting region.
According to the embodiment of the invention, the inverted doping region and the threshold voltage adjusting region are formed in the fin part, the threshold voltage adjusting region is positioned on one side of the top of the fin part, the inverted doping region is positioned below the threshold voltage adjusting region, and the threshold voltage adjusting region is formed on one side of the top of the fin part to increase the starting voltage of the top of the fin part, so that the current density of the top of the fin part is reduced, and the reliability of the device is improved; moreover, by forming the inversion doping region, the device channel is far away from the surface of the fin part so as to improve the problem of flicker noise, and the starting voltage at the position corresponding to the inversion doping region is reduced so that the starting voltage of the device meets the performance requirement; in summary, the reliability and the flicker noise performance of the device are improved through the inversion doping region and the threshold voltage adjusting region, that is, the performance of the device is improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 2 to 8 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure according to the present invention.
Referring to fig. 2, a substrate is provided, which includes a substrate 100 and a fin 110 protruding from the substrate 100, wherein a well 105 is formed in the substrate 100, and the well 105 has a first type of ions therein.
The substrate 100 is used to provide a process platform for subsequent formation of finfet devices.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration.
The fin 110 is used to provide a channel for the finfet formed.
In this embodiment, the fin 110 and the substrate 100 are an integral structure. In other embodiments, the fin may also be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of precisely controlling the height of the fin.
For this reason, in this embodiment, the material of the fin portion 110 is the same as the material of the substrate 100, and the material of the fin portion 110 is silicon. In other embodiments, the material of the fin may also be a semiconductor material suitable for forming a fin, such as germanium, silicon carbide, gallium arsenide, or indium gallium, and the material of the fin may also be different from that of the substrate.
In this embodiment, a well region 105 is formed in the fin portion 110 and the substrate 100, and the well region 105 has a first type of ions therein.
Wherein, when the formed semiconductor structure is a PMOS transistor, the first type ions are N type ions, and the N type ions comprise one or more of phosphorus, arsenic and antimony; when the formed semiconductor structure is an NMOS transistor, the first type ions are P-type ions including one or more of boron, gallium, and indium.
In this embodiment, taking the formed semiconductor structure as an NMOS transistor as an example, the first type ions are P-type ions.
It should be noted that a fin mask layer 150 is further formed on the top of the fin 110, and the fin mask layer 150 is used as an etching mask for forming the substrate 100 and the fin 110.
In this embodiment, the fin mask layer 150 is made of silicon nitride.
With reference to fig. 3 to 7, an inversion-type doped region 320 (shown in fig. 5) and a threshold voltage adjusting region 330 (shown in fig. 5) are formed in the fin 110, the threshold voltage adjusting region 330 is located on one side of the top of the fin 110, the inversion-type doped region 320 is located below the threshold voltage adjusting region 330, the threshold voltage adjusting region 330 has the first type of ions therein, the inversion-type doped region 320 has a second type of ions therein, and the second type of ions has a different conductivity type from the first type of ions.
The subsequent process further comprises: an isolation structure is formed on the substrate, the isolation structure exposes the inversion doping region 320 and the threshold voltage adjusting region 330, and the fin 110 exposed by the isolation structure is used as an effective fin. In this embodiment, the inversion-type doped region 320 and the threshold voltage adjusting region 330 are formed in the effective fin portion, and the threshold voltage adjusting region 330 is formed on one side of the top of the fin portion 110 to increase the turn-on voltage at the top of the fin portion 110, thereby reducing the current density at the top of the fin portion 110 and further improving the reliability of the device; moreover, by forming the inversion doping region 320, the device channel is far away from the surface of the fin portion 110, so as to improve the problem of flicker noise, and at the same time, the turn-on voltage at the position corresponding to the inversion doping region 320 is reduced, so that the turn-on voltage of the device meets the performance requirement; for this reason, the reliability and the flicker noise performance of the device, i.e., the performance of the device, are improved by the inversion doping region 320 and the threshold voltage adjusting region 330.
In this embodiment, the threshold voltage adjusting region 330 is formed after the inversion doping region 320 is formed. The inversion doping region 320 is located below the threshold voltage adjusting region 330, and the inversion doping region 320 is formed first, which is beneficial to simplifying the process complexity and improving the forming quality of the inversion doping region 320 and the threshold voltage adjusting region 330.
As shown in fig. 3, before forming the inversion doping region 320, the method further includes: an isolation material layer 200 is formed on the substrate 100 exposed by the fin 110, and the isolation material layer 200 covers the sidewalls of the fin 110.
The isolation material layer 200 can protect the substrate 100, and is beneficial to reducing the probability of doping ions into the substrate 100 in the process of forming the inversion doping region 320, so that the influence on the normal performance of the device is reduced.
Furthermore, the isolation material layer 200 is used to prepare for the subsequent formation of isolation structures.
Therefore, by using the isolation material layer 200, an additional step of forming a protection layer for protecting the substrate 100 is omitted, the existing process is less modified, the process compatibility is high, and the process cost and the process time are saved.
Correspondingly, the material of the isolation material layer 200 is a dielectric material.
In this embodiment, the material of the isolation material layer 200 is silicon oxide. In other embodiments, the material of the isolation layer may also be other dielectric materials such as silicon nitride or silicon oxynitride.
Specifically, the step of forming the barrier material layer 200 includes: forming an initial isolation material layer (not shown) on the substrate 100 exposed by the fin 110 by a deposition process, wherein the initial isolation material layer covers the top of the fin mask layer 150; and performing planarization treatment on the initial isolation material layer, removing the initial isolation material layer higher than the top of the fin portion mask layer 150, and taking the remaining initial isolation material layer as the isolation material layer 200. That is, after the isolation material layer 200 is formed, the isolation material layer 200 exposes the top of the fin mask layer 150.
In this embodiment, the deposition step adopts a FCVD (flowable chemical vapor deposition) process. The FCVD process has good filling capacity, is beneficial to reducing the probability of defects such as cavities and the like formed in the isolation material layer 200, and is correspondingly beneficial to improving the isolation effect of the isolation material layer 200.
In this embodiment, the planarization process is performed by a chemical mechanical polishing process. In the chemical mechanical polishing process, the top surface of the fin mask layer 150 is used as a stop position, so that the isolation material layer 200 has a higher top surface flatness.
As shown in fig. 4, in this embodiment, after forming the isolation material layer 200 and before forming the inversion doped region 320, the method further includes: a channel stop implant (channel stop implant)315 is performed on the isolation material layer 200 and the top of the fin 110, and a punch-through prevention region 310 is formed in the fin 110, wherein the punch-through prevention region 310 has a first type of ions therein.
The subsequent process further comprises: forming a gate structure crossing the fin 110; and forming source and drain doped regions on two sides of the gate structure. The anti-punch-through region 310 is used to prevent punch-through between the source region and the drain region in the source and drain doped regions.
Therefore, the type of the doping ions of the anti-punch-through region 310 is different from the type of the doping ions of the source and drain doping regions, that is, the type of the doping ions of the anti-punch-through region 310 is the same as the type of the doping ions of the well region 105, and the first type of ions are in the anti-punch-through region 310.
In this embodiment, taking the formed semiconductor structure as an NMOS transistor as an example, the first type ions are P-type ions, that is, the type of the doped ions of the anti-punch-through region 310 is P-type ions.
In this embodiment, an ion implantation process is performed to perform a channel stop implantation 315 on the isolation material layer 200 and the top of the fin 110, so as to form the anti-punch-through region 310.
Because the width of the fin 210 is small, the isolation material layer 200 is also doped during the channel stop implantation 315, and after the channel stop implantation 315 is performed, the dopant ions in the isolation material layer 200 can diffuse into the fin 110 along the direction perpendicular to the sidewall of the fin 110, which is beneficial to improving the uniformity of the doping concentration of the punch-through prevention region 310 in the width direction of the fin 210.
Moreover, the ion implantation process is simple, and the doping concentration of the anti-punch-through region 310 can easily meet the process requirement by adjusting the implantation dose.
The implantation angle of the ion implantation process is not too large. If the implantation angle is too large, the implantation depth of the channel stop implantation 315 is likely to be too small, so that the anti-punch-through region 310 is difficult to form at the target position, which not only reduces the effect of the anti-punch-through region 310 for preventing punch-through between the source region and the drain region in the source-drain doped region, but also easily causes the anti-punch-through region 310 to occupy the position of other doped regions in the fin 110, and further easily causes the distance between the anti-punch-through region 310 and the channel of the transistor to be too close, and the doped ions of the anti-punch-through region 310 may affect the mobility of carriers in the channel, thereby affecting the normal performance of the transistor. For this reason, in the present embodiment, the implantation angle of the ion implantation process is 0 to 7 degrees during the channel stop implantation 315. Wherein the implantation angle is an included angle between an implantation direction and a surface normal of the substrate 100. For example: the implantation angle of the ion implantation process is 0 degree.
The implantation energy of the ion implantation process is not too small or too large. If the implantation energy is too small, the implantation depth of the channel stop implant 315 is easily made too small, that is, the anti-punch-through region 310 is easily made to be difficult to form at the target position, which not only reduces the effect of the anti-punch-through region 310 for preventing punch-through between the source region and the drain region in the source-drain doped region, but also easily causes the anti-punch-through region 310 to occupy the position of other doped regions in the fin 110, and furthermore, easily causes the distance between the anti-punch-through region 310 and the transistor channel to be too close, and the doped ions of the anti-punch-through region 310 may affect the mobility of carriers in the channel, thereby affecting the performance of the device; if the implantation energy is too large, it is easy to cause the implantation depth of the channel stop implant 315 to be too large, which also easily causes the anti-punch-through region 310 not to be formed at the target position, thereby affecting the function of the anti-punch-through region 310 and the performance of the device. For this reason, in the present embodiment, when the type of the doped ions in the anti-punch-through region 310 is P-type ions, the implantation energy is 12KeV to 45 KeV.
The implantation dosage of the ion implantation process is not required to be too small or too large. If the implantation dosage is too small, the doping concentration of the anti-punch-through region 310 is too low, so that the effect of the anti-punch-through region 310 for preventing punch-through between the source region and the drain region in the source and drain doped regions is easily reduced; if the implantation dose is too large, the dopant ions in the anti-punch-through region 310 are likely to diffuse toward the top of the fin 110, and thus the normal performance of the device is likely to be affected. For this reason, in the present embodiment, when the type of the doping ions in the anti-punch-through region 310 is P-type ions, the implantation dose is 1E14atom/cm2To 1E15atom/cm2。
In other embodiments, when the semiconductor structure is a PMOS transistor, the first type ions are N-type ions, and the process parameters of the channel stop implantation correspondingly include: the first type of ions comprise one or more of phosphorus, arsenic and antimony, the implantation energy is 25KeV to 65KeV, and the implantation dosage is 5E13atom/cm2To 1E15atom/cm2。
It should be noted that, in the process of performing the channel stop implantation 315 by using the ion implantation process, a fin mask layer 150 is formed on the top of the fin 110, and the fin mask layer 150 can protect the top of the fin 110, so that the damage of the ion implantation process to the top of the fin 110 is reduced.
Referring to fig. 5, an inversion ion implantation 325 is performed on the isolation material layer 200 and the top of the fin 110 to form an inversion doped region 320, wherein the inversion doped region 320 is located above the anti-punch through region 310.
The inversion doping region 320 has a second type of ions therein, and the type of the doped ions in the inversion doping region 320 is different from the type of the doped ions in the well 105. By the inversion doping region 320, when the device operates, the channel of the device is far away from the surface of the fin 110, so that the problem of flicker noise is solved, and the turn-on voltage at the position of the inversion doping region 320 is reduced.
In this embodiment, since the doped ions are diffused in the fin 110 in the direction perpendicular to the surface of the substrate 100, the bottom surface of the anti-punch through region 320 is flush with the top surface of the anti-punch through region 310. In other embodiments, the top surface of the inversion doping region may also be higher than the top surface of the anti-punch through region.
In this embodiment, after the anti-punch through region 310 is formed, the inverse type doped region 320 is formed, so as to prevent the process of forming the anti-punch through region 310 from affecting the doping concentration and the distribution of the doping ions of the inverse type doped region 320.
The inversion doping region 320 has a second type of ions therein, and the type of the doped ions in the inversion doping region 320 is different from the type of the doped ions in the well 105.
In this embodiment, taking the formed semiconductor structure as an NMOS transistor as an example, the type of the doped ions in the counter doped region 320 is correspondingly N-type ions, and the second type of ions includes one or more of phosphorus, arsenic and antimony.
In this embodiment, an ion implantation process is performed to perform an inverse ion implantation 325 on the isolation material layer 200 and the top of the fin 110, so as to form the inverse doped region 320.
The implantation angle of the ion implantation process is not too large. If the implantation angle is too large, the implantation depth of the channel stop implant 315 is too small, which affects the formation position and thickness of the inversion-type doped region 320, and also easily causes the inversion-type doped region 320 to occupy the position of the other doped region in the fin 110, which is not favorable for improving the performance of the device. For this reason, in the present embodiment, during the inversion ion implantation 325, the implantation angle of the ion implantation process is 0 to 7 degrees. Wherein the implantation angle is an included angle between an implantation direction and a surface normal of the substrate 100. For example: the implantation angle of the ion implantation process is 0 degree.
The implantation energy of the ion implantation process is not too small or too large. If the implantation energy is too small, the depth of the bottom surface of the inversion doping region 320 in the fin 110 is easily too small, so that the forming position and the thickness of the inversion doping region 320 are affected, and the inversion doping region 320 occupies the positions of other doping regions in the fin 110, which is not favorable for improving the problem of flicker noise and improving the overall performance of the device; if the implantation energy is too large, the inversion-type doped region 320 cannot be formed at the target position, thereby affecting the function of the inversion-type doped region 3200 and the performance of the device. For this reason, in the present embodiment, when the type of the doped ions in the inversion type doped region 320 is N-type ions, the implantation energy is 15KeV to 50 KeV.
The implantation dosage of the ion implantation process is not required to be too small or too large. If the implantation dosage is too small, the doping concentration of the inversion doping region 320 is too low, so that the effect of the inversion doping region 320 for improving the flicker noise problem is reduced; if the implantation dose is too large, it is easy to cause the doped ions in the inversion doping region 320 to diffuse into the channel, thereby causing the turn-on voltage of the device to be too high. For this reason, in the present embodiment, when the doping ion type of the inversion doping region 320 is N-type, the implantation dose is 2E13atom/cm2To 1E15atom/cm2。
In other embodiments, when the semiconductor structure is a PMOS transistor, the second type ions are P-type ions, and the process parameters of the inversion ion implantation include: the second type of ions comprise one or more of boron, gallium and indium, the implantation energy is 6KeV to 30KeV, and the implantation dosage is 2E13atom/cm2To 1E15atom/cm2。
Referring to fig. 6 and 7 in combination, a threshold voltage adjustment region 330 (as shown in fig. 7) is formed in the fin 110, wherein the threshold voltage adjustment region 330 is located above the inversion-type doped region 320.
The threshold voltage adjustment region 330 is used to adjust the threshold voltage of the transistor.
The current density at the top corner of the fin 110 is higher, which tends to degrade the reliability of the device and also degrades the flicker noise performance. Accordingly, by forming the threshold voltage adjustment region 330 on the top side of the fin 110, the turn-on voltage at the top of the fin 110 is increased, thereby reducing the current density at the top of the fin 110 and improving the reliability of the device.
The turn-on voltage at the position of the inversion doping region 320 is reduced by the inversion doping region 320, so that the turn-on voltage of the device can meet the performance requirement.
In this embodiment, the threshold voltage adjusting region 330 is located above the inverse doping region 320, and therefore, after the inverse doping region 320 is formed, the threshold voltage adjusting region 330 is formed, thereby preventing the processes of forming the inverse doping region 320 and the punch-through preventing region 310 from affecting the doping concentration and the distribution of the doping ions of the threshold voltage adjusting region 330.
The threshold voltage adjusting region 330 has the first type of ions therein, and the type of the doped ions in the threshold voltage adjusting region 330 is the same as the type of the doped ions in the well 105.
In this embodiment, taking the formed semiconductor structure as an NMOS transistor as an example, the doped ion type of the threshold voltage adjusting region 330 is correspondingly P-type ions.
In this embodiment, an ion implantation process is performed to implant 335 a threshold voltage into the fin 110, so as to form the threshold voltage adjusting region 330.
As shown in fig. 6, since the isolation material layer 200 is formed on the substrate 100 (as shown in fig. 5), after the forming of the inversion doping region 320 and before the forming of the threshold voltage adjusting region 330, the method further includes: a portion of the thickness of the isolation material layer 200 is removed to form an initial isolation layer 210 exposing a portion of the sidewalls of the fins 110.
The initial isolation layer 210 exposes portions of the sidewalls of the fin 110 for defining the region of the fin 110 for forming the threshold voltage adjustment region 330, thereby providing for the subsequent formation of the threshold voltage adjustment region 330.
In this embodiment, a dry etching process is adopted to etch the isolation material layer 200 with a partial thickness, so as to form the initial isolation layer 210. The dry etching process has anisotropic etching characteristics, which is advantageous for controlling the removal amount of the isolation material layer 200 and for improving the surface flatness of the initial isolation layer 210.
When the fin 110 is subsequently subjected to threshold voltage implantation, dopant ions are longitudinally diffused along a direction from the top of the fin 110 to the bottom of the fin 110, thereby forming the threshold voltage adjusting region 330 in the fin 110. In order to reduce the influence on the inversely doped region 320, the initial isolation structure 210 covers at least the sidewall of the inversely doped region 320, i.e. the top surface of the initial isolation structure 210 is flush with the top surface of the inversely doped region 320, or the top surface of the initial isolation structure 210 is higher than the top surface of the inversely doped region 320.
Moreover, the subsequent steps further include: an isolation structure is formed on the substrate 100 where the fin 110 is exposed, and the isolation structure covers a part of the sidewall of the fin 110. In the step of forming the isolation structure, the height of the fin 110 exposed by the isolation structure is a preset height, and in the step of forming the threshold voltage adjusting region 330, the threshold voltage adjusting region 330 has a preset thickness, and a ratio of the preset thickness to the preset height is not too small or too large. If the ratio is too small, the effect of the threshold voltage adjustment region 330 for reducing the current density at the top of the fin 110 is easily reduced; if the ratio is too large, the formation location of the inversion-doped region 320 in the fin 110 is easily affected, thereby affecting the function of the inversion-doped region 320. For this reason, in the present embodiment, the predetermined thickness is 1/5 to 1/3 of the predetermined height.
Correspondingly, the height of the exposed fin portion 110 of the initial isolation structure 210 is reasonably set according to the ratio of the preset thickness to the preset height.
As shown in fig. 7, the step of forming the threshold voltage adjusting region 330 includes: a threshold voltage implant 335 is performed on the exposed sidewalls of fin 110 from initial isolation layer 210.
By performing the threshold voltage implantation 335 on the sidewalls of the fins 110, the formation location of the threshold voltage adjustment region 330 may be easily controlled, and the uniformity of diffusion of the dopant ions of the threshold voltage adjustment region 330 in the fins 110 may be advantageously improved.
In this embodiment, an ion implantation process is used to perform threshold voltage implantation 335 on the sidewall of the fin 110, and an implantation direction of the ion implantation process forms an included angle with a normal direction of the substrate 100, and the included angle is an acute angle, so as to perform threshold voltage implantation 335 on the sidewall of the fin 110.
The implantation angle of the ion implantation process is not too small or too large. If the implantation angle is too small, it is easy to implant ions into the inversion-type doped region 320, which not only affects the quality of the threshold voltage adjusting region 330 formed in the fin 110, but also affects the function of the inversion-type doped region 320; if the implantation angle is too large, it may easily result in too small a threshold voltage implant 335 implantation depth, which may adversely decrease the current density at the top of the fin 110. For this reason, in the present embodiment, the implantation angle of the ion implantation process is 15 to 20 degrees.
The implantation energy of the ion implantation process is not too small or too large. If the implantation energy is too small, the formation position and thickness of the threshold voltage adjusting region 330 are easily affected, which is not favorable for reducing the current density at the top of the fin 110; if the implantation energy is too large, it is likely that the threshold voltage adjustment region 330 cannot be formed at the target location, and it is also likely that the threshold voltage adjustment region 330 occupies the other doped regions in the fin 110, thereby adversely affecting the performance of the device. For this reason, in the present embodiment, when the type of the doped ions in the threshold voltage adjusting region 330 is P-type ions, the implantation energy is 3KeV to 15 KeV.
The implantation dosage of the ion implantation process is not required to be too small or too large. If the implantation dose is too small, the doping concentration of the threshold voltage adjustment region 330 is too low, which is not favorable for lowering the top of the fin 110Current density of the location; if the implantation dosage is too large, the turn-on voltage of the device is likely to fail to meet the performance requirement. For this reason, in the present embodiment, when the doping ion type of the threshold voltage adjusting region 330 is P-type ions, the implantation dose is 1E13atom/cm2To 5E14atom/cm2。
In other embodiments, when the semiconductor structure is a PMOS transistor, the process parameters of the threshold voltage implantation include: the implanted ions comprise one or more of phosphorus, arsenic and antimony, the implantation energy is 7KeV to 25KeV, and the implantation dosage is 1E13atom/cm2To 5E14atom/cm2。
Referring to fig. 8, an isolation structure 220 is formed on the substrate 100 where the fin 110 is exposed, and the isolation structure 220 exposes the inversion doping region 320 and the threshold voltage adjusting region 330.
The isolation structure 220 serves as a Shallow Trench Isolation (STI) structure for isolating adjacent devices. In this embodiment, the isolation structure 220 is made of silicon oxide. In other embodiments, the material of the isolation structure 220 may also be other insulating materials such as silicon nitride or silicon oxynitride.
In this embodiment, the step of forming the isolation structure 220 includes: after the threshold voltage adjusting region 330 is formed, an etch back process is performed on the initial isolation layer 210 to remove a portion of the thickness of the initial isolation layer 210 (as shown in fig. 7), and the remaining initial isolation layer 210 is remained as the isolation structure 220.
In this embodiment, after the isolation structure 220 is formed, the isolation structure 220 covers the anti-punch through region 310 to prevent the doped ions in the anti-punch through region 310 from diffusing into the channel in the top direction of the fin 110. For example: the top surface of the isolation structure 220 is flush with the top surface of the anti-punch through region 310, or the top surface of the isolation structure 220 is higher than the top surface of the anti-punch through region 310.
However, when the top of the isolation structure 220 is higher than the top of the anti-punch through region 310, the distance from the top surface of the isolation structure 220 to the top surface of the anti-punch through region 310 should not be too large. If the distance from the top surface of the isolation structure 220 to the top surface of the anti-punch-through region 310 is too large, the distance between the anti-punch-through region 310 and the channel is too long, and the effect of the anti-punch-through region 310 for preventing punch-through between the source region and the drain region in the source-drain doped region is correspondingly poor, which adversely affects the performance of the device.
For this reason, in the present embodiment, the distance from the top surface of the isolation structure 220 to the top of the anti-punch-through region 310 is 0nm to 10 nm.
In this embodiment, after the isolation structure 220 is formed, the top surface of the isolation structure 220 is flush with the bottom surface of the inversion doping region 320, or the top surface of the isolation structure 220 is lower than the bottom surface of the inversion doping region 320.
However, when the top surface of the isolation structure 220 is lower than the bottom surface of the inversion doped region 320, the distance from the top surface of the isolation structure 220 to the bottom surface of the inversion doped region 320 is not too large. If the distance from the top surface of the isolation structure 220 to the bottom surface of the inversion doped region 320 is too small, the thickness of the inversion doped region 320 is too small, which may cause the inversion doped region 320 to perform an insignificant effect.
For this reason, in the present embodiment, the distance from the top surface of the isolation structure 220 to the bottom surface of the inversion doped region 320 is 0nm to 30 nm.
In this embodiment, a fin mask layer 150 is further formed on the top of the fin 110 (as shown in fig. 7), so before performing the etch-back process on the initial isolation layer 210, the method further includes: the fin mask layer 150 is removed. In other embodiments, the fin mask layer may be removed after the isolation structure is formed.
Correspondingly, the invention also provides a semiconductor structure. Referring to fig. 8, a schematic structural diagram of an embodiment of a semiconductor structure of the present invention is shown.
The semiconductor structure includes: a substrate 100, wherein a well region 105 is formed in the substrate 100, and a first type of ions are in the well region 105; a fin 110 protruding from the substrate 100; a threshold voltage adjustment region 330 in the fin 110, the threshold voltage adjustment region 330 being located on a top side of the fin 110, the threshold voltage adjustment region 330 having the first type of ions therein; an inversion-type doped region 320 in the fin 110, the inversion-type doped region 320 being located below the threshold voltage adjusting region 330, the inversion-type doped region 320 having a second type of ions therein, the second type of ions having a different conductivity type than the first type of ions; an isolation structure 220 is disposed on the substrate 100 where the fin 110 is exposed, wherein the isolation structure 220 exposes the inversion doping region 320 and the threshold voltage adjusting region 330.
The semiconductor structure is a fin field effect transistor and the substrate 100 is used to provide a process platform for the fin field effect transistor.
In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be another type of substrate such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy integration.
The fin 110 is used to provide a channel for the finfet formed.
In this embodiment, the fin 110 and the substrate 100 are an integral structure. In other embodiments, the fin may also be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of precisely controlling the height of the fin.
For this reason, in this embodiment, the material of the fin portion 110 is the same as the material of the substrate 100, and the material of the fin portion 110 is silicon. In other embodiments, the material of the fin may also be a semiconductor material suitable for forming a fin, such as germanium, silicon carbide, gallium arsenide, or indium gallium, and the material of the fin may also be different from that of the substrate.
In this embodiment, a well region 105 is formed in the fin portion 110 and the substrate 100, and the well region 105 has a first type of ions therein.
Wherein, when the semiconductor structure is a PMOS transistor, the first type of ions are N-type ions comprising one or more of phosphorus, arsenic, and antimony; when the semiconductor structure is an NMOS transistor, the first type ions are P-type ions, and the P-type ions include one or more of boron, gallium, and indium.
In this embodiment, taking the semiconductor structure as an NMOS transistor as an example, the first type ions are P-type ions.
The isolation structure 220 serves as a shallow trench isolation structure for isolating adjacent devices. In this embodiment, the isolation structure 220 is made of silicon oxide. In other embodiments, the material of the isolation structure 220 may also be other insulating materials such as silicon nitride or silicon oxynitride.
The threshold voltage adjustment region 330 is used to adjust the threshold voltage of the transistor.
The current density at the top corner of the fin 110 is higher, which tends to degrade the reliability of the device and also causes flicker noise. Accordingly, by forming the threshold voltage adjustment region 330 on the top side of the fin 110, the turn-on voltage at the top of the fin 110 is increased, thereby reducing the current density at the top of the fin 110 and improving the reliability of the device.
The threshold voltage adjusting region 330 has the first type of ions therein, and the type of the doped ions in the threshold voltage adjusting region 330 is the same as the type of the doped ions in the well 105.
In this embodiment, taking the formed semiconductor structure as an NMOS transistor as an example, the type of the doped ions of the threshold voltage adjusting region 330 is correspondingly P-type ions, that is, the first type of ions includes one or more of boron, gallium, and indium.
The doping concentration of the threshold voltage adjusting region 330 should not be too small or too large. This is detrimental to reducing the current density at the top of fin 110 if the doping concentration of threshold voltage tuning region 330 is too low; if the doping concentration of the threshold voltage adjusting region 330 is too large, the turn-on voltage of the device may not meet the performance requirement. For this reason, in the present embodiment, the doping in the threshold voltage adjusting region 330 is performedWhen the subtype is P-type ions, the doping concentration of the threshold voltage adjusting region 330 is 1E18atom/cm3To 3E19atom/cm3。
In other embodiments, when the semiconductor structure is a PMOS transistor, the first type of ions comprises one or more of phosphorus, arsenic, and antimony, and the threshold voltage adjustment region has a doping concentration of 1E18 atoms/cm3To 3E19atom/cm3。
The threshold voltage adjusting region 330 has a preset thickness, the height of the fin 110 exposed by the isolation structure is a preset height, and the ratio of the preset thickness to the preset height is not too small or too large. If the ratio is too small, the effect of the threshold voltage adjustment region 330 for reducing the current density at the top of the fin 110 is easily reduced; if the ratio is too large, it is easy to affect the inversion-doped region 320, thereby affecting the function of the inversion-doped region 320. For this reason, in the present embodiment, the predetermined thickness is 1/5 to 1/3 of the predetermined height.
The inversion doping region 320 is located below the threshold voltage adjusting region 330.
The inversion doping region 320 has a second type of ions therein, and the type of the doped ions in the inversion doping region 320 is different from the type of the doped ions in the well 105. Through the inversion doping region 320, when the device operates, a device channel is far away from the surface of the fin 110, so that the problem of flicker noise is solved.
In addition, since the threshold voltage adjusting region 330 is formed on the top side of the fin 110, the turn-on voltage at the top of the fin 110 is increased, and the turn-on voltage at the position of the inversion doping region 320 is reduced by the inversion doping region 320, the turn-on voltage of the device can meet the performance requirement through the inversion doping region 320.
In this embodiment, taking the semiconductor structure as an NMOS transistor as an example, the type of the doped ions in the inversion-type doped region 320 is correspondingly N-type ions, that is, the second type of ions includes one or more of phosphorus, arsenic and antimony.
The doping concentration of the inversion doping region 320 should not be too highSmall, too large should not be used. If the doping concentration of the inversion doping region 320 is too small, the effect of the inversion doping region 320 for improving the flicker noise problem is easily reduced; if the doping concentration of the inversion doping region 320 is too high, it is easy to cause the doped ions in the inversion doping region 320 to diffuse into the channel, thereby causing the turn-on voltage of the device to be too high. For this reason, in the present embodiment, when the doping ion type of the inversion doping region 320 is N-type ions, the doping concentration of the inversion doping region 320 is 2E18atom/cm3To 5E19atom/cm3。
In other embodiments, when the semiconductor structure is a PMOS transistor, the second type ions are P-type ions, the second type ions include one or more of boron, gallium, and indium, and the inversion doping region has a doping concentration of 2E18 atoms/cm3To 5E19atom/cm3。
In this embodiment, the semiconductor structure further includes: a punch-through prevention region 310 in the fin 110 below the punch-through prevention region 320, the punch-through prevention region 310 having a first type of ions therein.
The semiconductor structure typically further comprises: a gate structure spanning the fin 110 and covering a portion of the top and a portion of the sidewalls of the fin 110; and the source and drain doped regions are positioned in the fin parts at two sides of the grid structure. The anti-punch-through region 310 is used to prevent punch-through between the source region and the drain region in the source and drain doped regions.
Therefore, the type of the doping ions of the anti-punch-through region 310 is different from the type of the doping ions of the source and drain doping regions, that is, the type of the doping ions of the anti-punch-through region 310 is the same as the type of the doping ions of the well region 105, and the first type of ions are in the anti-punch-through region 310.
In this embodiment, taking the formed semiconductor structure as an NMOS transistor as an example, the first type ions are P-type ions, that is, the type of the doped ions of the anti-punch-through region 310 is P-type ions.
The doping concentration of the anti-punch-through region 310 should not be too low or too high. If the doping concentration of the anti-punch-through region 310 is too low, the anti-punch-through region 310 is easily reduced for preventing source and drainThe punch-through function is generated between the source region and the drain region in the doped region; if the doping concentration of the anti-punch-through region 310 is too high, the doping ions in the anti-punch-through region 310 are likely to diffuse toward the top of the fin 110, and thus the normal performance of the device is likely to be affected. For this reason, in the present embodiment, when the doping ion type of the penetration preventing region 310 is P-type ions, the doping concentration of the penetration preventing region 310 is 3E18atom/cm3To 3E19atom/cm3。
In other embodiments, when the semiconductor structure is a PMOS transistor, the first type ions are N-type ions, the first type ions include one or more of phosphorus, arsenic, and antimony, and the anti-punch-through region has a doping concentration of 3E18atom/cm3To 3E19atom/cm3。
In this embodiment, the isolation structure 220 covers the anti-punch through region 310 to prevent the dopant ions in the anti-punch through region 310 from diffusing into the channel in the top direction of the fin 110. For example: the top surface of the isolation structure 220 is flush with the top surface of the anti-punch through region 310, or the top surface of the isolation structure 220 is higher than the top surface of the anti-punch through region 310.
However, when the top of the isolation structure 220 is higher than the top of the anti-punch through region 310, the distance from the top surface of the isolation structure 220 to the top surface of the anti-punch through region 310 should not be too large. If the distance from the top surface of the isolation structure 220 to the top surface of the anti-punch-through region 310 is too large, the distance between the anti-punch-through region 310 and the channel is too long, and the effect of the anti-punch-through region 310 for preventing punch-through between the source region and the drain region in the source-drain doped region is correspondingly poor, which adversely affects the performance of the device.
For this reason, in the present embodiment, the distance from the top surface of the isolation structure 220 to the top surface of the penetration preventing region 310 is 0nm to 10 nm.
In this embodiment, the top surface of the isolation structure 220 is flush with the bottom surface of the inversion doping region 320, or the top surface of the isolation structure 220 is lower than the bottom surface of the inversion doping region 320.
However, when the top surface of the isolation structure 220 is lower than the bottom surface of the inversion doped region 320, the distance from the top surface of the isolation structure 220 to the bottom surface of the inversion doped region 320 is not too large. If the distance from the top surface of the isolation structure 220 to the bottom surface of the inversion doped region 320 is too small, the thickness of the inversion doped region 320 is too small, which may cause the inversion doped region 320 to perform an insignificant effect.
For this reason, in the present embodiment, the distance from the top surface of the isolation structure 220 to the bottom surface of the inversion doped region 320 is 0nm to 30 nm.
The semiconductor structure may be formed by the formation method described in the foregoing embodiment, or may be formed by another formation method. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (22)
1. A method of forming a semiconductor structure, comprising:
providing a substrate, wherein the substrate comprises a substrate and a fin part protruding out of the substrate, a well region is formed in the substrate, and first type ions are arranged in the well region;
forming an inversion doping region and a threshold voltage adjusting region in the fin portion, wherein the threshold voltage adjusting region is located on one side of the top of the fin portion, the inversion doping region is located below the threshold voltage adjusting region, the threshold voltage adjusting region is provided with first type ions, the inversion doping region is provided with second type ions, and the second type ions are different from the first type ions in conductive types;
and forming an isolation structure on the substrate with the exposed fin part, wherein the isolation structure exposes the inversion doping region and the threshold voltage adjusting region.
2. The method of forming a semiconductor structure of claim 1, wherein the threshold voltage adjustment region is formed after the inversion doping region is formed.
3. The method of forming a semiconductor structure of claim 2, wherein prior to forming said inversion-doped region, further comprising: forming an isolation material layer on the substrate exposed out of the fin portion, wherein the isolation material layer covers the side wall of the fin portion;
the step of forming the inversion doping region comprises the following steps: and performing inverse ion implantation on the isolation material layer and the top of the fin part.
4. The method of forming a semiconductor structure of claim 3, wherein after forming said inversion doping region and before forming said threshold voltage adjustment region, further comprising: removing the isolation material layer with partial thickness to form an initial isolation layer exposing partial side walls of the fin parts;
the step of forming the threshold voltage adjustment region includes: and performing threshold voltage injection on the fin part side wall exposed by the initial isolation layer.
5. The method of forming a semiconductor structure of claim 4, wherein forming the isolation structure comprises: and after the threshold voltage adjusting region is formed, removing part of the initial isolation layer, and reserving the residual initial isolation layer as the isolation structure.
6. The method of forming a semiconductor structure of claim 3, wherein prior to forming said inversion-doped region, further comprising: performing channel stop injection on the isolation material layer and the top of the fin portion, and forming a penetration prevention area in the fin portion, wherein the penetration prevention area is provided with first type ions;
in the step of forming the inversion-type doped region, the inversion-type doped region is positioned above the anti-punch-through region;
in the step of forming the isolation structure, the isolation structure covers the side wall of the penetration preventing region.
7. The method as claimed in claim 1, wherein the fin portion is subjected to an inversion ion implantation process to form the inversion doped region.
8. The method of claim 1, wherein the threshold voltage adjustment region is formed by performing a threshold voltage implantation on the fin using an ion implantation process.
9. The method of claim 1, wherein an ion implantation process is used to perform a channel stop implant on the fin portion to form the anti-punch through region.
10. The method of claim 7 or 9, wherein an implantation angle of the ion implantation process is 0 to 7 degrees.
11. The method of claim 8, wherein an implantation angle of the ion implantation process is 15 to 20 degrees.
12. The method of claim 7, wherein the process parameters of the inversion ion implantation comprise: the second type of ions comprise one or more of boron, gallium and indium, the implantation energy is 6KeV to 30KeV, and the implantation dosage is 2E13atom/cm2To 1E15atom/cm2；
Alternatively, the second type of ions comprises one or more of phosphorus, arsenic and antimony, the implantation energy is 15KeV to 50KeV, and the implantation dose is 2E13atom/cm2To 1E15atom/cm2。
13. The method of forming a semiconductor structure of claim 8, wherein the process parameters of the threshold voltage implant comprise: the first type of ion comprises one or more of phosphorus, arsenic and antimonyThe implantation energy is 7KeV to 25KeV, and the implantation dose is 1E13atom/cm2To 5E14atom/cm2；
Or, the first type ions comprise one or more of boron, gallium and indium, the implantation energy is 3KeV to 15KeV, and the implantation dosage is 1E13atom/cm2To 5E14atom/cm2。
14. The method of forming a semiconductor structure of claim 5, wherein in the step of forming the threshold voltage adjustment region, the threshold voltage adjustment region has a predetermined thickness;
in the step of forming the isolation structure, the height of the fin part exposed out of the isolation structure is a preset height;
the preset thickness is 1/5-1/3 of the preset height.
15. The method of claim 5, wherein after the isolation structure is formed, a distance from a top surface of the isolation structure to a bottom surface of the inversion doped region is 0nm to 30 nm.
16. The method of forming a semiconductor structure of claim 3, wherein in the step of providing a substrate, a fin mask layer is formed on a top of the fin;
in the step of forming the isolation material layer, the isolation material layer exposes the top of the fin portion mask layer;
after the threshold voltage adjusting region is formed, the method further comprises the following steps: and removing the fin mask layer.
17. A semiconductor structure, comprising:
the ion implantation device comprises a substrate, wherein a well region is formed in the substrate, and first type ions are arranged in the well region;
the fin part protrudes out of the substrate;
a threshold voltage adjustment region in the fin, the threshold voltage adjustment region being on a top side of the fin, the threshold voltage adjustment region having the first type of ions therein;
an inversion doped region in the fin portion, the inversion doped region being located below the threshold voltage adjustment region, the inversion doped region having a second type of ions therein, the second type of ions being of a different conductivity type than the first type of ions;
and the isolation structure is positioned on the substrate with the exposed fin part, and the inversion doping area and the threshold voltage adjusting area are exposed out of the isolation structure.
18. The semiconductor structure of claim 17, wherein the semiconductor structure further comprises: the anti-punch-through area is positioned in the fin part below the anti-punch-through area, and first type ions are arranged in the anti-punch-through area;
the isolation structure covers the side wall of the penetration preventing area.
19. The semiconductor structure of claim 17, wherein the threshold voltage adjustment region has a predetermined thickness, wherein a fin height exposed by the isolation structure is a predetermined height, and wherein the predetermined thickness is 1/5-1/3 of the predetermined height.
20. The semiconductor structure of claim 17, wherein a distance from a top surface of the isolation structure to a bottom surface of the inversion doped region is 0nm to 30 nm.
21. The semiconductor structure of claim 17, wherein the first type of ions comprises one or more of phosphorus, arsenic, and antimony, and the threshold voltage adjustment region has a doping concentration of 1E18 atoms/cm3To 3E19atom/cm3；
Or, the first type ions comprise one or more of boron, gallium and indium, and the doping concentration of the threshold voltage adjusting region is 1E18atom/cm3To 3E19atom/cm3。
22. The semiconductor structure of claim 17, characterized in thatCharacterized in that the second type ions comprise one or more of phosphorus, arsenic and antimony, and the doping concentration of the inversion doping region is 2E18atom/cm3To 5E19atom/cm3；
Or, the second type ions comprise one or more of boron, gallium and indium, and the doping concentration of the inversion doping region is 2E18atom/cm3To 5E19atom/cm3。
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113571418A (en) * | 2021-05-31 | 2021-10-29 | 上海华力集成电路制造有限公司 | Super well forming method of FinFET |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8610201B1 (en) * | 2012-08-16 | 2013-12-17 | Kabushiki Kaisha Toshiba | FinFET comprising a punch-through stopper |
| US9142651B1 (en) * | 2014-03-26 | 2015-09-22 | Globalfoundries Inc. | Methods of forming a FinFET semiconductor device so as to reduce punch-through leakage currents and the resulting device |
| CN106611710A (en) * | 2015-10-22 | 2017-05-03 | 中芯国际集成电路制造(上海)有限公司 | A formation method of a semiconductor structure |
| CN107785425A (en) * | 2016-08-31 | 2018-03-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN107785424A (en) * | 2016-08-31 | 2018-03-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
-
2019
- 2019-06-28 CN CN201910577014.2A patent/CN112151594B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8610201B1 (en) * | 2012-08-16 | 2013-12-17 | Kabushiki Kaisha Toshiba | FinFET comprising a punch-through stopper |
| US9142651B1 (en) * | 2014-03-26 | 2015-09-22 | Globalfoundries Inc. | Methods of forming a FinFET semiconductor device so as to reduce punch-through leakage currents and the resulting device |
| CN106611710A (en) * | 2015-10-22 | 2017-05-03 | 中芯国际集成电路制造(上海)有限公司 | A formation method of a semiconductor structure |
| CN107785425A (en) * | 2016-08-31 | 2018-03-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
| CN107785424A (en) * | 2016-08-31 | 2018-03-09 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and forming method thereof |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113571418A (en) * | 2021-05-31 | 2021-10-29 | 上海华力集成电路制造有限公司 | Super well forming method of FinFET |
| US20220384193A1 (en) * | 2021-05-31 | 2022-12-01 | Shanghai Huali Integrated Circuit Corporation | Method for forming finfet super well |
| CN113571418B (en) * | 2021-05-31 | 2024-03-08 | 上海华力集成电路制造有限公司 | Super well forming method of FinFET |
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