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CN112151459B - Package circuit structure and manufacturing method thereof - Google Patents

Package circuit structure and manufacturing method thereof Download PDF

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Publication number
CN112151459B
CN112151459B CN201910562603.3A CN201910562603A CN112151459B CN 112151459 B CN112151459 B CN 112151459B CN 201910562603 A CN201910562603 A CN 201910562603A CN 112151459 B CN112151459 B CN 112151459B
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China
Prior art keywords
layer
antenna
opening
chip
circuit
Prior art date
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Application number
CN201910562603.3A
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Chinese (zh)
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CN112151459A (en
Inventor
魏永超
杨永泉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Avary Holding Shenzhen Co Ltd
Qing Ding Precision Electronics Huaian Co Ltd
Original Assignee
Avary Holding Shenzhen Co Ltd
Qing Ding Precision Electronics Huaian Co Ltd
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Application filed by Avary Holding Shenzhen Co Ltd, Qing Ding Precision Electronics Huaian Co Ltd filed Critical Avary Holding Shenzhen Co Ltd
Priority to CN201910562603.3A priority Critical patent/CN112151459B/en
Priority to US16/550,601 priority patent/US11178777B2/en
Publication of CN112151459A publication Critical patent/CN112151459A/en
Priority to US17/497,809 priority patent/US20220030720A1/en
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Publication of CN112151459B publication Critical patent/CN112151459B/en
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4623—Manufacturing multilayer circuits by laminating two or more circuit boards the circuit boards having internal via connections between two or more circuit layers before lamination, e.g. double-sided circuit boards
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/315—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the encapsulation having a cavity
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/12—Supports; Mounting means
    • H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
    • H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
    • H01Q1/38—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith formed by a conductive layer on an insulating support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/48—Earthing means; Earth screens; Counterpoises
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q1/00—Details of, or arrangements associated with, antennas
    • H01Q1/50—Structural association of antennas with earthing switches, lead-in devices or lightning protectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0243—Printed circuits associated with mounted high frequency components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
    • H05K1/165—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor incorporating printed inductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
    • H05K13/04—Mounting of components, e.g. of leadless components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/103—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by bonding or embedding conductive wires or strips
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02331—Multilayer structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0233—Structure of the redistribution layers
    • H01L2224/02333—Structure of the redistribution layers being a bump
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02373—Layout of the redistribution layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02381—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/03—Manufacturing methods
    • H01L2224/031—Manufacture and pre-treatment of the bonding area preform
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    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H05K1/0203—Cooling of mounted components
    • H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10098—Components for radio transmission, e.g. radio frequency identification [RFID] tag, printed or non-printed antennas
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/06—Lamination
    • H05K2203/061—Lamination of previously made multilayered subassemblies
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components

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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

The utility model provides a packaging circuit structure, is including the circuit board, dielectric layer and the antenna structure that stack gradually the setting, first opening has been seted up to one side that circuit board and dielectric layer combine, be equipped with the second opening on the dielectric layer, the second opening run through the dielectric layer and with first opening correspond in order with first opening constitutes accepts the chamber, the antenna structure is including the first ground plane, first insulation layer and the first antenna layer that stack gradually the setting, still be equipped with conductive structure on the dielectric layer, conductive structure runs through the dielectric layer is with the electricity connection circuit board and first ground plane, packaging circuit structure still includes the chip, the chip set up in accept the intracavity and be connected with the circuit board electricity, just the chip with there is the clearance between the antenna structure. The invention also provides a manufacturing method of the packaging circuit structure.

Description

Package circuit structure and manufacturing method thereof
Technical Field
The present invention relates to a package circuit structure and a method for manufacturing the same, and more particularly, to a package circuit structure having an antenna module and a method for manufacturing the same.
Background
In recent years, electronic products are widely used in daily work and life, and light, thin and small electronic products are increasingly popular. The circuit structure is used as a main component of an electronic product, and occupies a large space of the electronic product, so that the volume of the circuit structure influences the volume of the electronic product to a great extent, and the large-volume circuit structure is difficult to conform to the trend of lightness, thinness, shortness and smallness of the electronic product.
The embedded chip (such as a resistor, a capacitor and the like) is embedded inside the circuit substrate, so that the whole thickness of the circuit structure is reduced, and the thickness of an electronic product is reduced. However, the conventional chip packaging technology is prone to damage when the chip is packaged in the circuit board.
Disclosure of Invention
In view of the above, it is desirable to provide a method for fabricating a circuit package structure that is not prone to damage.
A packaged circuit structure is also provided.
A method for manufacturing a packaged circuit structure comprises the following steps:
providing a circuit board, and forming a first opening on one side of the circuit board;
installing a chip in the first opening and electrically connecting the chip with the circuit board;
providing a dielectric layer, wherein a second opening and at least one conductive structure are arranged on the dielectric layer, and the second opening and the conductive structure respectively penetrate through two opposite surfaces of the dielectric layer;
providing an antenna structure, wherein the antenna structure comprises a first grounding layer, a first insulating layer and a first antenna layer which are sequentially stacked; and
and sequentially stacking and pressing the antenna structure, the dielectric layer and the circuit board provided with the chip to package the chip to obtain a packaged circuit structure, wherein one end of the conductive structure is connected with the first grounding layer, the other end of the conductive structure is connected with the circuit board, the second opening corresponds to the first opening, and a gap exists between the chip and the antenna structure in the packaged circuit structure.
The utility model provides a packaging circuit structure, is including the circuit board, dielectric layer and the antenna structure that stack gradually the setting, first opening has been seted up to one side of circuit board, be equipped with the second opening on the dielectric layer, the second opening run through the dielectric layer and with first opening correspond in order with first opening constitution accepts the chamber, the antenna structure is including the first ground plane, first insulating layer and the first antenna layer that stack gradually the setting, still be equipped with conductive structure on the dielectric layer, conductive structure runs through the dielectric layer is with the electricity connection circuit board and first ground plane, packaging circuit structure still includes the chip, the chip set up in accept the intracavity and be connected with the circuit board electricity, just the chip with there is the clearance between the antenna structure.
In the packaging circuit structure, the dielectric layer in the packaging circuit structure is provided with the second opening corresponding to the chip, so that the chip is communicated with the antenna structure, the heat dissipation of the chip in the direction of the antenna structure is facilitated, and the damage or chip displacement to the chip during pressing is avoided.
Drawings
Fig. 1-15 are schematic diagrams illustrating a method for manufacturing a package circuit structure according to an embodiment of the invention.
Fig. 16 is a schematic cross-sectional view of a package circuit structure according to an embodiment of the invention.
Description of the main elements
Figure BDA0002108684950000021
Figure BDA0002108684950000031
Figure BDA0002108684950000041
The following detailed description will further illustrate the invention in conjunction with the above-described figures.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.
Some embodiments of the invention are described in detail below with reference to the accompanying drawings. The embodiments and features of the embodiments described below can be combined with each other without conflict.
Referring to fig. 1 to 15, a method for manufacturing a package circuit structure according to an embodiment of the invention includes the following steps:
step S1, referring to fig. 1, a circuit board 10 is provided, where the circuit board 10 includes a first dielectric layer 11, and a first circuit layer 12 and a second circuit layer 13 formed on two opposite sides of the first dielectric layer 11, and the circuit board 10 is further provided with a first opening 101, where the first opening 101 is opened from a surface of the first dielectric layer 11 on which the first circuit layer 12 is formed toward the second circuit layer 13 to expose a portion of the second circuit layer 13.
In the present embodiment, the first circuit layer 12 includes at least one first connecting pad 121, the second circuit layer 13 includes at least one second connecting pad 131, and the second connecting pad 131 is exposed from the first opening 101.
The first wiring layer 12 is electrically connected to the second wiring layer 13.
In this embodiment, the circuit board 10 may further include other dielectric layers and other circuit layers or metal layers disposed alternately on a side of the second circuit layer 13 away from the first circuit layer 12. The other circuit layers are electrically connected with the second circuit layer 13.
Specifically, the circuit board 10 further includes a second dielectric layer 14, a third circuit layer 15, a third dielectric layer 16, a fourth circuit layer 17, a fourth dielectric layer 18, and a first metal layer 190, which are sequentially stacked. One side of the second dielectric layer 14, which is away from the third circuit layer 15, is pressed on one side of the second circuit layer 13, which is away from the first circuit layer 12.
In the present embodiment, the wiring density in the circuit board 10 gradually decreases from the second circuit layer 13 toward the direction away from the first circuit layer 12.
Step S2, referring to fig. 2, a chip 20 is mounted in the first opening 101 and electrically connected to the second connecting pad 131, and an adhesive 23 is injected into the first opening 101 to bond the chip 20 and the circuit board 10.
In this embodiment, the chip 20 installed in the first opening 101 does not protrude from the first circuit layer 12. Preferably, the chip 20 is lower than the first opening 101 or flush with the first opening 101.
In this embodiment, the adhesive 23 further reinforces the chip 20 and the circuit board 10. Preferably, the adhesive 23 is an adhesive material with good thermal conductivity, so as to accelerate the heat dissipation of the chip 20 and facilitate the heat dissipation.
In other embodiments, the chip 20 may protrude from the first wiring layer 12.
In other embodiments, the step of injecting the adhesive 23 may also be omitted.
Step S3, please refer to fig. 3, providing a dielectric layer 30, wherein a second opening 301 and at least one conductive structure 31 are disposed on the dielectric layer 30, and the second opening 301 and the conductive structure 31 respectively penetrate two opposite surfaces of the dielectric layer 30.
In this embodiment, at least one through hole 302 is formed on the dielectric layer 30, and the through hole 302 is filled with a conductive paste to form the conductive structure 31. The conductive paste has a good conductive property and a certain adhesive property, and when the dielectric layer 30 is pressed against other elements, the conductive paste realizes good electrical conduction and thermal conduction while adhering the other elements.
In other embodiments, the conductive structure 31 may also be made of other materials such as conductive paste and metal deposition layer.
In this embodiment, the dielectric layer 30 includes three conductive structures 31 disposed at intervals.
In step S4, referring to fig. 4, an antenna structure 40 is provided, where the antenna structure 40 includes a first ground layer 41, a first insulating layer 42 and a first antenna layer 43, which are sequentially stacked.
In this embodiment, the antenna structure 40 may further include a second insulating layer 44, a second ground layer 45, a third insulating layer 46, and a second metal layer 470, which are sequentially stacked. The first ground layer 41 is electrically connected to the second ground layer 45 and the second metal layer 470.
In this embodiment, the antenna structure 40 includes two conductive pillars 401 disposed at intervals and penetrating through the first ground layer 41, the first insulating layer 42, the second insulating layer 44, the second ground layer 45, the third insulating layer 46 and the second metal layer 470, respectively. The conductive pillars 401 are electrically connected to the first ground layer 41, the second ground layer 45 and the second metal layer 470.
In other embodiments, an inner ground layer, an inner insulating layer, and an inner antenna layer may be further disposed between the first antenna layer 43 and the second ground layer 45. The first antenna layer 43 and the inner antenna layer in the antenna structure 40 do not overlap each other in projection in the stacking direction.
The first insulating layer 42, the second insulating layer 44, the third insulating layer 46 and the inner insulating layer in the antenna structure 40 have low dielectric constants (D) k ) And low dielectric dissipation factor (D) f ). In this embodiment, D in the antenna structure 40 k Less than 3.0, D f Less than 0.2.
Step S5, referring to fig. 5, the antenna structure 40, the dielectric layer 30, and the circuit board 10 with the chip 20 are sequentially stacked and pressed, and the chip 20 is packaged to obtain a packaged circuit structure 100. One end of the conductive structure 31 is connected to the first ground layer 41, and the other end is connected to the first connection pad 121. The second opening 301 corresponds to the first opening 101, and a gap exists between the chip 20 and the antenna structure 40 after the lamination.
In other embodiments, when the antenna structure 40, the dielectric layer 30 and the circuit board 10 with the chip 20 mounted thereon are pressed, a heat conductive material (not shown) with a good heat dissipation effect may be further disposed in the second opening 301, so that the heat conductive material is sandwiched between the chip 20 and the antenna structure 40 after the pressing, so as to accelerate the heat dissipation of the chip 20.
In this embodiment, the conductive column 401 is provided corresponding to the conductive structure 31.
In this embodiment, the method for manufacturing the package circuit structure may further include step S6 and step S7, specifically:
in step S6, referring to fig. 5 and fig. 6, the first metal layer 190 and the second metal layer 470 are patterned to form a fifth circuit layer 19 and a second antenna layer 47, respectively. The second antenna layer 47 is not coincident with the projection of the first antenna layer 43 in the stacking direction.
Step S7, referring to fig. 7, a solder mask layer 50 is disposed on the surface of the package circuit structure 100, and the outermost circuit layer of the circuit board 10 away from the first circuit layer 12 is exposed from the solder mask layer 50 for connecting other electronic components.
Specifically, the fifth wiring layer 19 is exposed from the solder mask layer 50.
In other embodiments, the first metal layer 190 and the second metal layer 470 are patterned to form a fifth circuit layer 19 and a second antenna layer 47, respectively, before the antenna structure 40, the dielectric layer 30 and the circuit board 10 mounted with the chip 20 are laminated. The second antenna layer 47 is not coincident with the projection of the first antenna layer 43 in the stacking direction. After the antenna structure 40, the dielectric layer 30 and the circuit board 10 with the chip 20 are laminated, the method for manufacturing the package circuit structure may further include: a solder mask 50 is disposed on the surface of the package circuit structure 100, and an outermost circuit layer of the circuit board 10 away from the first circuit layer 12 is exposed from the solder mask 50 for connecting other electronic components.
In the package circuit structure 100, an antenna structure 40, a dielectric layer 30 and a circuit board 10 are sequentially stacked, wherein the second antenna layer 47 is located at the outermost side of the antenna structure 40 away from the dielectric layer 30, and is connected to the conductive structure 31 in the dielectric layer 30 by the conductive pillar 401 penetrating through the entire antenna structure 40; one side of the conductive structure 31 away from the conductive column 401 is connected to the first circuit layer 12 of the circuit board 10, and the first circuit layer 12 is electrically connected to the second circuit layer 13, so as to achieve conduction between the second antenna layer 47 and the chip 20.
In the present embodiment, the circuit board 10 may be prepared by the following steps S11 to S15:
step S11, please refer to fig. 8, a carrier plate 1 is provided, and a first metal foil 130 is disposed on a surface of the carrier plate 1.
In step S12, referring to fig. 9, a second dielectric layer 14 is laminated on the first metal foil 130, and a third circuit layer 15 is formed on a side of the second dielectric layer 14 away from the first metal foil 130.
Step S13, referring to fig. 10, a third dielectric layer 16 is laminated on the third circuit layer 15, a circuit is formed on a side of the third dielectric layer 16 away from the third circuit layer 15 to form a fourth circuit layer 17, and the carrier plate 1 is removed and the first metal foil 130 is patterned to form a second circuit layer 13. The second circuit layer 13 includes at least one second connecting pad 131.
In step S14, referring to fig. 11, a solder mask structure 60 is formed on the second connecting pads 131, a first single panel (not shown) is bonded on the second circuit layer 13, and a second single panel (not shown) is bonded on the fourth circuit layer 17. The first single-sided board comprises a first dielectric layer 11 and a second metal foil 120 formed on one surface of the first dielectric layer 11, wherein one side of the first dielectric layer 11, which is far away from the second metal foil 120, is combined with the second circuit layer 13; the second single panel includes a fourth dielectric layer 18 and a third metal foil 191 formed on a surface of the fourth dielectric layer 18, and a side of the fourth dielectric layer 18 facing away from the third metal foil 191 is combined with the fourth circuit layer 17.
Step S15, referring to fig. 1, a first circuit layer 12 is formed by performing circuit fabrication on the second metal foil 120, a first opening 101 is opened on the first dielectric layer 11 to expose the second connection pad 131, and the third metal foil 191 is punched and electroplated to form a first metal layer 190 electrically connected to the fourth circuit layer 17.
In the present embodiment, the antenna structure 40 may be prepared through the following steps S41 to S45:
step S41, please refer to fig. 12, a first dual panel A1 and a second dual panel A2 are provided, in which the first dual panel A1 includes a first insulating layer 42 and a first conductive layer 411 and a second conductive layer 430 respectively disposed on two opposite surfaces of the first insulating layer 42, and the second dual panel A2 includes a third insulating layer 46 and a third conductive layer 450 and a fourth conductive layer 471 respectively disposed on two opposite surfaces of the third insulating layer 46.
In step S42, referring to fig. 13, the second conductive layer 430 is subjected to circuit fabrication to form a first antenna layer 43, and the third conductive layer 450 is subjected to circuit fabrication to form a second ground layer 45.
In step S43, referring to fig. 14, the first dual panel A1 with the first antenna layer 43, the second insulating layer 44, and the second dual panel A2 with the second ground layer 45 are pressed together to form an intermediate body 200. The first antenna layer 43 and the second ground layer 45 are respectively bonded to two opposite surfaces of the second insulating layer 44.
In step S44, referring to fig. 15, an opening is formed in the intermediate body 200 and the intermediate body 200 is electroplated, so that the first conductive layer 411 forms a third metal layer 410 correspondingly, the fourth conductive layer 471 forms a second metal layer 470 correspondingly, and the opening is filled to form the conductive pillar 401 correspondingly. The conductive pillar 401 penetrates through the third metal layer 410, the first insulating layer 42, the first antenna layer 43, the second insulating layer 44, the second ground layer 45, the third insulating layer 46 and the second metal layer 470.
In step S45, referring to fig. 4, the third metal layer 410 is subjected to line etching to obtain a first ground layer 41. The conductive pillars 401 penetrate the first ground layer 41, the first insulating layer 42, the first antenna layer 43, the second insulating layer 44, the second ground layer 45, the third insulating layer 46, and the second metal layer 470.
Referring to fig. 16, a package circuit structure 100 according to a preferred embodiment of the present invention includes a circuit board 10, a dielectric layer 30 and an antenna structure 40 stacked in sequence. The circuit board 10 includes a first circuit layer 12, a first dielectric layer 11, and a second circuit layer 13 stacked in sequence. The first circuit layer 12 includes a first connecting pad 121, and the second circuit layer 13 includes a second connecting pad 131. The circuit board 10 is further provided with a first opening 101, and the first opening 101 is opened from the surface of the first dielectric layer 11 on which the first circuit layer 12 is formed to the second circuit layer 13 to expose the second connection pad 131. The antenna structure 40 includes a first ground layer 41, a first insulating layer 42, and a first antenna layer 43, which are sequentially stacked. The dielectric layer 30 is combined with the side of the first dielectric layer 11 where the first circuit layer 12 is disposed and the side of the first insulating layer 42 where the first ground layer 41 is disposed. The dielectric layer 30 is provided with a second opening 301 and at least one conductive structure 31, the second opening 301 and the conductive structure 31 respectively penetrate through two opposite surfaces of the dielectric layer 30, and the conductive structure 31 is connected to the first connection pad 121 and the first ground layer 41. The second opening 301 corresponds to the first opening 101 to form a receiving cavity 70. The package circuit structure 100 further includes a chip 20, the chip 20 is mounted in the receiving cavity 70 and connected to the second connecting pad 131, and a gap (not shown) exists between the chip 20 and the antenna structure 40.
In this embodiment, the chip 20 does not protrude from the first circuit layer 12. Preferably, the chip 20 is completely accommodated in the first opening 101, and does not protrude from the first opening 101.
The package circuit structure 100 may further include an adhesive 23 disposed in the first opening 101, wherein the adhesive 23 bonds the chip 20 and the circuit board 10.
In the present embodiment, the adhesive 23 may be an adhesive material having good thermal conductivity.
A thermally conductive material (not shown) may be disposed in the gap, and the thermally conductive material connects the chip 20 and the antenna structure 40, so as to increase the heat dissipation speed of the chip 20 in the direction of the antenna structure 40.
In this embodiment, the antenna structure 40 may further include a second insulating layer 44, a second ground layer 45, a third insulating layer 46, and a second antenna layer 47, which are sequentially stacked, wherein a side of the second insulating layer 44 facing away from the second ground layer 45 is combined with a side of the first antenna layer 43 facing away from the first ground layer 41. Wherein a projection of the first antenna layer 43 and the second antenna layer 47 in the stacking direction is not coincident.
In other embodiments, the antenna structure 40 may further include other internal antenna layers (not shown) disposed between the first antenna layer 43 and the second ground layer 45 to increase signal transmission. Wherein the first antenna layer 43, the inner antenna layer, and the second antenna layer 47 do not overlap in projection in the stacking direction.
The antenna structure 40 may further include a conductive pillar 401 penetrating the first ground layer 41, the first insulating layer 42, the second insulating layer 44, the second ground layer 45, the third insulating layer 46, and the second antenna layer 47. The conductive pillar 401 is electrically connected to the first ground layer 41, the second ground layer 45, and the second antenna layer 47.
In this embodiment, the circuit board 10 may include another circuit layer disposed on a side of the second circuit layer 13 away from the first circuit layer 12.
Specifically, the circuit board 10 further includes a second dielectric layer 14, a third circuit layer 15, a third dielectric layer 16, a fourth circuit layer 17, a fourth dielectric layer 18, and a fifth circuit layer 19, which are stacked in sequence. The side of the second dielectric layer 14 away from the third circuit layer 15 is pressed on the side of the second circuit layer 13 away from the first circuit layer 12.
The circuit board 10 may further include a solder mask 50 formed on an outermost side, and the fifth circuit layer 19 is exposed from the solder mask 50.
In the package circuit structure 100 of the present invention, the dielectric layer 30 of the package circuit structure 100 has a second opening 301 corresponding to the chip 20, so that the chip 20 is communicated with the antenna structure 40, which is beneficial to heat dissipation of the chip 20 in the direction of the antenna structure 40, and simultaneously avoids damage to the chip 20 or chip displacement during lamination. Further, a heat conducting material is disposed between the chip 20 and the antenna structure 40, so that heat dissipation of the chip 20 in the direction of the antenna structure 40 can be accelerated. Further, the adhesive 23 in the first opening 101 reinforces the chip 20 and the circuit board 10, and when the adhesive 23 is an adhesive material with good thermal conductivity, the heat dissipation of the chip 20 toward the circuit board 10 can be accelerated. Further, the first antenna layer 43 and the second antenna layer 47 do not overlap in projection in the stacking direction, which is beneficial to signal transmission. Meanwhile, the antenna structure 40 can integrate multiple signals and be arranged in layers.
Although the present invention has been described with reference to the above preferred embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (9)

1. A manufacturing method of a packaging circuit structure comprises the following steps:
providing a circuit board, and forming a first opening on one side of the circuit board;
installing a chip in the first opening and electrically connecting the chip with the circuit board;
providing a dielectric layer, wherein a second opening and at least one conductive structure are arranged on the dielectric layer, and the second opening and the conductive structure respectively penetrate through two opposite surfaces of the dielectric layer;
providing an antenna structure, wherein the antenna structure comprises a first grounding layer, a first insulating layer and a first antenna layer which are sequentially stacked; and
and sequentially stacking and pressing the antenna structure, the dielectric layer and the circuit board provided with the chip to package the chip to obtain a packaged circuit structure, wherein one end of the conductive structure is connected with the first grounding layer, the other end of the conductive structure is connected with the circuit board, the second opening corresponds to the first opening, and a gap exists between the chip and the antenna structure in the packaged circuit structure.
2. The method of fabricating a packaged circuit structure according to claim 1, wherein the step of mounting a chip in the first opening and electrically connecting to the circuit board further comprises: and injecting an adhesive into the first opening to bond the chip and the circuit board.
3. The method of claim 1, wherein a thermally conductive material is disposed in the gap to connect the chip and the antenna structure, so as to increase a heat dissipation rate of the chip in a direction of the antenna structure.
4. The method for manufacturing the packaged circuit structure of claim 1, wherein the antenna structure further comprises a second insulating layer, a second ground layer, a third insulating layer and a second antenna layer, which are sequentially stacked, and a side of the second insulating layer away from the second ground layer is combined with the first antenna layer.
5. The method of fabricating the packaged circuit structure of claim 4, wherein the first antenna layer and the second antenna layer do not coincide in projection along the stacking direction.
6. A packaging circuit structure comprises a circuit board, a dielectric layer and an antenna structure which are sequentially stacked, and is characterized in that a first opening is formed in one side of the circuit board, a second opening is formed in the dielectric layer, the second opening penetrates through the dielectric layer and corresponds to the first opening to form a containing cavity with the first opening, the antenna structure comprises a first ground layer, a first insulating layer and a first antenna layer which are sequentially stacked, a conductive structure is further arranged on the dielectric layer and penetrates through the dielectric layer to be electrically connected with the circuit board and the first ground layer, the packaging circuit structure further comprises a chip, the chip is arranged in the containing cavity and is electrically connected with the circuit board, the chip faces towards the surface of the antenna structure and is separated from the antenna structure by a gap, and therefore the antenna structure does not face towards the antenna structure and is in surface contact with the antenna structure, and therefore the antenna structure is prevented from interacting with force between the chips.
7. The packaged circuit structure of claim 6, further comprising an adhesive disposed in the first opening, the adhesive bonding the die and the circuit board.
8. The package circuit structure of claim 6, wherein the antenna structure further comprises a second insulating layer, a second ground layer, a third insulating layer, and a second antenna layer stacked in sequence, wherein a side of the second insulating layer facing away from the second ground layer is combined with a side of the first antenna layer facing away from the first ground layer.
9. The packaged circuit structure of claim 8, wherein the first antenna layer and the second antenna layer do not coincide in projection in a stacking direction.
CN201910562603.3A 2019-06-26 2019-06-26 Package circuit structure and manufacturing method thereof Active CN112151459B (en)

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