CN112151377B

CN112151377B - Semiconductor structure and forming method thereof

Info

Publication number: CN112151377B
Application number: CN201910577066.XA
Authority: CN
Inventors: 赵猛
Original assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp; Semiconductor Manufacturing International Beijing Corp
Priority date: 2019-06-28
Filing date: 2019-06-28
Publication date: 2024-05-31
Anticipated expiration: 2039-06-28
Also published as: CN112151377A

Abstract

A semiconductor structure and a method for forming the same, the method for forming the same includes: providing a substrate, wherein the substrate comprises a substrate, a gate structure positioned on the substrate, source and drain doped regions positioned in the substrate at two sides of the gate structure, an etching resistant layer positioned on the source and drain doped regions and an interlayer dielectric layer covering the etching resistant layer and the side wall of the gate structure, and the interlayer dielectric layer exposes the top of the gate structure; etching the interlayer dielectric layer to form a first opening exposing part of the anti-etching layer; after forming a first opening, removing the anti-etching layer on the source-drain doped region to form a second opening, wherein the projection of the bottom end of the first opening on the substrate is positioned in the projection of the second opening on the substrate; contact hole plugs are formed in the first opening and the second opening. Compared with the condition that only the first opening is formed, the area of the source-drain doped region exposed by the second opening is larger than that of the source-drain doped region exposed by the first opening, so that the contact resistance between the contact hole plug and the source-drain doped region is reduced, and the electrical performance of the semiconductor structure is improved.

Description

Semiconductor structure and forming method thereof

Technical Field

Embodiments of the present disclosure relate to semiconductor manufacturing, and more particularly, to a semiconductor structure and a method for forming the same.

Background

In semiconductor manufacturing, with the trend of very large scale integrated circuits, the feature size of integrated circuits is continuously reduced, and in order to adapt to smaller feature sizes, the channel length of Metal-Oxide-semiconductor field effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device is shortened, the distance between the source and the drain of the device is also shortened, so that the control capability of the gate structure on the channel is further and further reduced, and the difficulty of pinching off (pin off) the channel by the gate voltage is further and further increased, so that the phenomenon of subthreshold leakage (subthreshold leakage), namely the so-called short channel effect (SCE-CHANNEL EFFECTS) is more likely to occur.

Accordingly, to better accommodate the reduction in feature sizes, semiconductor processes are increasingly beginning to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as fin field effect transistors (finfets). In the FinFET, the gate structure can control the ultrathin body (fin part) from at least two sides, and compared with a planar MOSFET, the gate structure has stronger control capability on a channel and can well inhibit short channel effect; the gate structure is also changed from the original polysilicon gate structure to a metal gate structure, and the work function layer in the metal gate structure can adjust the threshold voltage of the semiconductor structure.

Disclosure of Invention

The embodiment of the invention solves the problem of providing a semiconductor structure and a forming method thereof, and improves the electrical performance of a device.

In order to solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate comprises a substrate, a gate structure positioned on the substrate, source and drain doped regions positioned in the substrate at two sides of the gate structure, an etching resistant layer positioned on the source and drain doped regions and an interlayer dielectric layer covering the etching resistant layer and the side wall of the gate structure, and the interlayer dielectric layer exposes the top of the gate structure; etching the interlayer dielectric layer to form a first opening exposing part of the anti-etching layer; after the first opening is formed, removing the etching resistant layer on the source-drain doping region to form a second opening, wherein the projection of the bottom end of the first opening on the substrate is positioned in the projection of the second opening on the substrate; in the process of forming the second opening, the etched rate of the anti-etching layer is larger than the etched rate of the interlayer dielectric layer and the source-drain doped region; and forming contact hole plugs in the first opening and the second opening.

Correspondingly, the embodiment of the invention also provides a semiconductor structure, which comprises: a substrate; a gate structure located on the substrate; the source-drain doped regions are positioned in the substrate at two sides of the grid structure; the interlayer dielectric layer is positioned on the substrate, the source-drain doped region and the side wall of the grid structure, and the top of the grid structure is exposed out of the interlayer dielectric layer; the contact hole plug is positioned in the interlayer dielectric layer, and the top of the contact hole plug is exposed out of the interlayer dielectric layer; the contact hole plug comprises a bottom contact hole plug and a top contact hole plug positioned on the bottom contact hole plug, wherein the projection of the bottom end of the top contact hole plug on the substrate is positioned in the projection of the bottom contact hole plug on the substrate, and the projection of the source-drain doping region on the substrate is positioned in the projection of the bottom contact hole plug on the substrate; and the anti-etching layer is positioned between the gate structure and the interlayer dielectric layer and between the interlayer dielectric layer and the substrate exposed by the source-drain doped region.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:

In the embodiment of the invention, after the interlayer dielectric layer is etched to form the first opening exposing part of the anti-etching layer, the anti-etching layer on the source-drain doping region is removed to form the second opening, the projection of the bottom end of the first opening on the substrate is positioned in the projection of the second opening on the substrate, and contact hole plugs are formed in the first opening and the second opening. Compared with the situation that only the first opening is formed in the semiconductor structure and the contact hole plug electrically connected with the source-drain doped region is formed in the first opening, in the embodiment of the invention, the area of the source-drain doped region exposed by the second opening is larger than that of the source-drain doped region corresponding to the first opening, and the contact hole plug in the second opening is electrically connected with the source-drain doped region, so that the contact resistance of the contact hole plug and the source-drain doped region is reduced, and the electrical property of the semiconductor structure is improved.

Drawings

Fig. 1 and 2 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;

fig. 3 to 13 are schematic structural views corresponding to each step in an embodiment of a method for forming a semiconductor structure according to the present invention.

Detailed Description

The devices formed at present still have the problem of poor performance. The reason for the poor performance of the device is analyzed by combining a forming method of a semiconductor structure.

Referring to fig. 1 and 2, a schematic structure diagram corresponding to each step in a method for forming a semiconductor structure is shown.

As shown in fig. 1, a base is provided, the base comprises a substrate 1 and a fin 6 positioned on the substrate 1; forming a gate structure 2 across the fin 6, and the gate structure 2 covering a portion of the top wall and a portion of the side wall of the fin 6; source-drain doped regions 3 are formed in the fin portions 6 at two sides of the gate structure 2; and forming the interlayer dielectric layer 4 covering the source-drain doped region 3 and the side wall of the gate structure 2, wherein the interlayer dielectric layer 4 exposes the top of the gate structure 2.

As shown in fig. 2, etching the interlayer dielectric layer 4 to form a trench (not shown in the figure) exposing the source-drain doped region 3; in the trench, a conductive material is filled, forming a contact plug 5.

The contact hole plugs 5 electrically connect the source-drain doped regions 3 with a later-stage metal layer formed later.

With the continuous development of integrated circuit process technology, in order to improve the integration level of an integrated circuit, improve the working speed of a device, reduce the power consumption of the device, continuously shrink the feature size of a semiconductor process, correspondingly shrink the sizes of the contact hole plug 5 and the source-drain doped region 3, and cause the contact resistance of the contact hole plug 5 and the source-drain doped region 3 to become larger, thereby affecting the electrical performance of the semiconductor structure.

In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: and etching the interlayer dielectric layer to form a first opening exposing part of the anti-etching layer, removing the anti-etching layer on the source-drain doping region to form a second opening, wherein the projection of the bottom end of the first opening on the substrate is positioned in the projection of the second opening on the substrate, and forming contact hole plugs in the first opening and the second opening. Compared with the situation that only the first opening is formed in the semiconductor structure and the contact hole plug electrically connected with the source-drain doped region is formed in the first opening, in the embodiment of the invention, the area of the source-drain doped region exposed by the second opening is larger than that of the source-drain doped region corresponding to the first opening, and the contact hole plug in the second opening is electrically connected with the source-drain doped region, so that the contact resistance of the contact hole plug and the source-drain doped region is reduced, and the electrical property of the semiconductor structure is improved.

In order that the above objects, features and advantages of embodiments of the invention may be readily understood, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.

Referring to fig. 3-7, a base is provided, the base including a substrate 100, a gate structure 109 (shown in fig. 7) on the substrate 100, source and drain doped regions 103 in the substrate 100 on both sides of the gate structure 109, an etch-resistant layer 104 (Contact Etch Stop Layer, CESL) (shown in fig. 5) on the source and drain doped regions 103, and an interlayer dielectric layer 105 (shown in fig. 5) covering the etch-resistant layer 104 and sidewalls of the gate structure 109, the interlayer dielectric layer 105 exposing a top of the gate structure 109.

The substrate provides a process basis for the subsequent formation of semiconductor structures.

Specifically, the step of forming the substrate includes:

As shown in fig. 3, the semiconductor structure formed in this embodiment is exemplified by a fin field effect transistor (FinFET), and the substrate 100 is a substrate 100 having a fin 101. In other embodiments, the semiconductor structure may be a planar structure, and accordingly, the substrate does not have a fin.

In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate may be made of other materials such as germanium, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may be made of other types of substrates such as silicon on insulator substrates or germanium on insulator substrates. The material of the substrate may be a material suitable for process requirements or easy integration.

The fin 101 is used to subsequently provide a channel for the fin field effect transistor.

In this embodiment, the fin 101 and the substrate 100 are obtained by etching the same semiconductor layer. In other embodiments, the fin may be a semiconductor layer epitaxially grown on the substrate, so as to achieve the purpose of precisely controlling the height of the fin.

Therefore, in this embodiment, the material of the fin 101 is the same as the material of the substrate 100.

The polysilicon gate structure 102 occupies a spatial location for subsequent gate structure formation.

A polysilicon gate structure 102 spans across the fin 101 and covers portions of the sidewalls and top wall of the fin 101.

In this embodiment, the polysilicon gate structure 102 is a stacked structure, and includes a gate oxide layer (not labeled in the figure) conformally covering a portion of the top surface and a portion of the sidewall of the fin 101, and a polysilicon gate layer on the gate oxide layer. In other embodiments, the polysilicon gate structure may also be a single layer structure, i.e., the polysilicon gate structure includes only a polysilicon gate layer.

In this embodiment, the gate oxide layer is made of silicon oxide. In other embodiments, the gate oxide layer may also be silicon oxynitride.

In this embodiment, the polysilicon gate layer is made of polysilicon.

Note that a gate mask layer 106 is further formed on top of the polysilicon gate structure 102. The gate mask layer 106 serves as an etch mask for forming the polysilicon gate structure 102. The gate mask layer 106 protects the polysilicon gate structure 102 from damage during the subsequent formation of the semiconductor structure.

In this embodiment, the substrate 100 is a substrate 100 having a fin 101, and the source-drain doped regions 103 are located in the fin 101 at two sides of the polysilicon gate structure 102.

The source-drain doped region 103 is used to apply stress to the channel, and to increase the migration rate of carriers in the channel when the semiconductor structure is in operation.

In this embodiment, the source-drain doped region 103 is used as the source and drain of the NMOS (NEGATIVE CHANNEL METAL Oxide Semiconductor). During operation of the semiconductor structure, the source drain doped region 103 imparts a tensile stress (TENSILE STRESS) to the channel, which may improve the electron mobility. Specifically, the material of the source-drain doped region 103 is silicon carbide or silicon phosphide doped with N-type ions. The N-type ions include one or more of P, as and Sb.

In other embodiments, the source-drain doped regions are used as the source and drain of PMOS (Positive CHANNEL METAL Oxide Semiconductor). The source-drain doped region imparts a compressive stress (compression stress) to the channel during operation of the semiconductor structure, which compressive channel can improve hole mobility. Specifically, the source-drain doped region is made of silicon germanium doped with P-type ions. The P-type ions include one or more of B, ga and In.

As shown in fig. 4, an etching resist material layer 107 is formed on the polysilicon gate structure 102 and on the fin 101 where the polysilicon gate structure 102 is exposed.

Specifically, the source-drain doped region 103 is located in the fin 101 at two sides of the polysilicon gate structure 102, and therefore, the etching-resistant material layer 107 is located on the source-drain doped region 103.

The etch-resistant material layer 107 provides for the subsequent formation of an etch-resistant layer.

The material of the etching-resistant material layer 107 is a dielectric material.

Specifically, the material of the etching-resistant material layer 107 includes one or more of silicon oxide, silicon oxynitride, silicon carbonitride, and silicon nitride. In this embodiment, the material of the etching-resistant material layer 107 is silicon nitride.

It should be noted that the etching resist layer 107 is not too thick or too thin. If the etching-resistant material layer 107 is too thick, ions are not easy to pass through the etching-resistant layer 104 in the subsequent process of forming the second doped region, so that the doping concentration of the formed second doped region is too low, which is not beneficial to reducing the contact resistance between the subsequently formed contact plug and the source-drain doped region 103. If the etching-resistant material layer 107 is too thin, the lattice of the source-drain doped region 103 is easily damaged in the subsequent process of forming the second doped region by doping, and the doped ions are easily and rapidly diffused into the channel region in the fin portion 101 through lattice defects, so that the depletion layers of the source electrode and the drain electrode of the source-drain doped region 103 are easily expanded during the operation of the semiconductor structure, resulting in serious short channel effect. And if the etching-resistant material layer 107 is too thin, the depth of the second opening formed by subsequently removing the etching-resistant material layer 107 on the source-drain doped region 103 is too small, and the contact plug formed in the second opening is thinner, so that the contact resistance between the bottom of the contact plug and the source-drain doped region 103 is larger, which is not beneficial to improving the electrical performance of the semiconductor structure. In this embodiment, the thickness of the etching resist material layer 107 is1 nm to 4 nm.

In this embodiment, the etch-resistant material layer 107 is formed using an atomic layer deposition process (Atomic layer deposition, ALD). The atomic layer deposition process includes performing multiple atomic layer deposition cycles to form the etch resistant material layer 107 of a desired thickness. The atomic layer deposition process is adopted, so that the uniformity of the thickness of the anti-etching material layer 107 is improved, and the thickness of the anti-etching material layer 107 can be accurately controlled; in addition, the gap filling performance and the step coverage performance of the atomic layer deposition process are good, and the conformal coverage capability of the etching-resistant material layer 107 is correspondingly improved. In other embodiments, other deposition processes may also be used to form the etch resistant material layer, such as: chemical vapor deposition processes, and the like.

As shown in fig. 5, an interlayer dielectric material layer (not shown) is formed on the etching-resistant material layer 107 (shown in fig. 4), and covers the polysilicon gate structure 102; and flattening the interlayer dielectric material layer until the top of the polysilicon gate structure 102 is exposed, wherein the rest of the interlayer dielectric material layer serves as an interlayer dielectric layer 105.

The interlayer dielectric material layer is used for realizing electric isolation between adjacent transistors. The interlayer dielectric material layer is made of insulating materials.

Specifically, the material of the interlayer dielectric material layer comprises one or two of silicon oxide and silicon nitride. In this embodiment, the material of the interlayer dielectric material layer is silicon oxide. The silicon oxide is a dielectric material with common process and low cost, has high process compatibility, is beneficial to reducing the process difficulty and the process cost for forming the interlayer dielectric material layer, has simple removal process, and has good adhesion between the silicon oxide and the anti-etching material layer 107 (shown in fig. 4).

In this embodiment, the interlayer dielectric material layer is formed by a flowable chemical vapor deposition (Flowable Chemical Vapor Deposition, FCVD) process. The flowable chemical vapor deposition process has good filling capability, is beneficial to reducing the probability of forming defects such as cavities in the interlayer dielectric material layer, and is correspondingly beneficial to improving the film forming quality of the interlayer dielectric layer 105.

During the planarization process, the gate mask layer 106 is also removed.

It should be further noted that, during the planarization process, the etching resist material layer 107 located on the gate mask layer 106 (as shown in fig. 4) is also removed, and the remaining etching resist material layer 107 serves as the etching resist layer 104.

As shown in fig. 6 and 7, the polysilicon gate structure 102 is removed to form a gate opening 108; a gate structure 109 is formed in the gate opening 108.

In this embodiment, the gate structure 109 includes a gate dielectric layer (not shown) and a metal gate layer (not shown) disposed on the gate dielectric layer.

The gate dielectric layer is made of a gate dielectric material with a relative dielectric constant larger than that of silicon oxide. In this embodiment, the gate dielectric layer is made of HfO ₂. In other embodiments, the gate dielectric layer may also be HfSiO, hfSiON, hfTaO, hfTiO, hfZrO, zrO ₂ or Al ₂O₃.

In this embodiment, the material of the metal gate layer includes magnesium-tungsten alloy. In other embodiments, the material of the metal gate layer includes one or more of W, al, cu, ag, au, pt, ni and Ti.

In other embodiments, the polysilicon gate structure may not be removed, and the polysilicon gate structure may be used as a gate structure in a semiconductor structure.

Referring to fig. 8, the interlayer dielectric layer 105 is etched to form a first opening 110 exposing a portion of the etch-resistant layer 104.

The first opening 110 provides for the subsequent formation of a contact plug.

In the step of forming the first opening 110, the etching resist layer 104 is used as an etching stop layer.

In this embodiment, a dry etching process is used to etch the interlayer dielectric layer 105, so as to form the first opening 110. The dry etching process is an anisotropic etching process, has good etching profile controllability, reduces damage to other film structures, is favorable for enabling the appearance of the first opening 110 to meet process requirements, improves the forming efficiency of the first opening 110, and can use the anti-etching layer 104 as an etching stop layer in the etching process, so that the etching stop position is easy to control.

It should be noted that, during the process of etching the interlayer dielectric layer 105 to form the first opening 110, polymer impurities generated by etching accumulate at the bottom of the first opening 110, so that the interlayer dielectric layer 105 at the bottom is not easy to be etched, and further, in the direction perpendicular to the extending direction of the gate structure 102, the top dimension of the first opening 110 is larger than the bottom dimension of the first opening 110.

The method for forming the semiconductor structure further comprises the following steps: after providing the substrate, a dielectric layer 111 is formed covering the gate structure 102 and the interlayer dielectric layer 105 before forming the first opening 110.

The dielectric layer 111 is used for realizing electrical isolation between later-stage metal layers formed later, and the material of the dielectric layer 111 is an insulating material.

In this embodiment, the material of the dielectric layer 111 is silicon oxide.

Note that, the dielectric layer 111 is etched during the process of forming the first opening 110.

Referring to fig. 9 to 11, after the first opening 110 is formed, the etching resist layer 104 on the source-drain doped region 103 is removed, and a second opening 112 (as shown in fig. 11) is formed, where a projection of the bottom end of the first opening 110 on the substrate 100 is located in a projection of the second opening 112 on the substrate 100; in the process of forming the second opening 112, the etching rate of the anti-etching layer 104 is greater than the etching rate of the interlayer dielectric layer 105 and the source-drain doped region 103.

In the embodiment of the present invention, after the first opening 110 is formed, the etching resist layer 104 on the source-drain doped region 103 is removed, so as to form a second opening 112, where the projection of the bottom end of the first opening 110 on the substrate 100 is located in the projection of the second opening 112 on the substrate 100, and then contact hole plugs are formed in the first opening 110 and the second opening 112. Compared with the case that only the first opening is formed in the semiconductor structure, and the contact hole plug electrically connected with the source-drain doped region is formed in the first opening, the area of the source-drain doped region 103 exposed by the second opening 112 is larger than the area of the source-drain doped region 103 corresponding to the first opening 110, and the contact hole plug in the second opening 112 is electrically connected with the source-drain doped region 103, so that the contact resistance between the contact hole plug and the source-drain doped region 103 is reduced, and the electrical performance of the semiconductor structure is improved.

The step of forming the second opening 112 includes: as shown in fig. 10, the etching resist layer 104 exposed by the first opening 110 is etched by a dry etching process, so as to form a recess 113 exposing the source-drain doped region 103; as shown in fig. 11, after forming the recess 103, the etching resist layer 104 on the source/drain doped region 103 is etched by a wet etching process, so as to form the second opening 112.

In the process of forming the second opening 112, the etching rate of the anti-etching layer 104 is greater than the etching rate of the interlayer dielectric layer 105, and the etching rate of the anti-etching layer 104 is greater than the etching rate of the source-drain doped region 103.

Specifically, the process parameters of the dry etching process include: the etching gas includes: difluoromethane and carbon tetrafluoride.

The flow rate of the etching gas should not be too large or too small. If the flow of the etching gas is too large, a large etching rate is easy to generate, and in the process of removing the etching resist layer 104 exposed by the first opening 110, the top of the source-drain doped region 103 is easy to be etched by mistake, and when the semiconductor structure works, the stress of the source-drain doped region 103 on the channel is insufficient, so that the carrier migration rate is not high. If the flow of the etching gas is too small, the removal rate of the etching resist layer 104 exposed from the first opening 110 is easy to be slower, which is not beneficial to improving the formation efficiency of the groove 113. In this embodiment, the flow rate of difluoromethane is 8sccm to 50sccm; the flow rate of carbon tetrafluoride is 30sccm to 200sccm.

Specifically, the process parameters of the wet etching process include: the etching solution comprises: a phosphoric acid solution; the mass concentration of the phosphoric acid solution is 50 to 85 percent.

The mass concentration of the phosphoric acid solution should not be too high or too low. If the mass concentration of the phosphoric acid is too high, the top of the source-drain doped region 103 is easily etched by mistake in the process of removing the etching-resistant layer 104 on the source-drain doped region 103, and when the semiconductor structure works, the stress of the source-drain doped region 103 on the channel is insufficient, so that the carrier migration rate is not high. If the mass concentration of the phosphoric acid is too low, the removal rate of the etching resist layer 104 on the source-drain doped region 103 is easy to be slower, which is unfavorable for improving the formation efficiency of the second opening 112. In this example, the mass concentration of the phosphoric acid solution is 50% to 85%.

In other embodiments, the material of the interlayer dielectric layer is silicon nitride, and the material of the etching-resistant layer is silicon oxide. Correspondingly, the etching gas adopted in the dry etching process is hydrogen fluoride; the etching solution adopted in the wet etching process is hydrogen fluoride solution.

It should be noted that, the second opening 112 exposes the source-drain doped region 103, and provides for forming a first doped region in the source-drain doped region 103, where the first doped region is used to reduce the contact resistance between the contact plug formed subsequently and the source-drain doped region 103, and improve the electrical performance of the semiconductor structure.

Note that, as shown in fig. 9, the method for forming the semiconductor structure further includes: after the first opening 110 is formed and before the second opening is formed, the etching resist layer 104 exposed by the first opening 110 is doped with a second ion, the doped ion passes through the etching resist layer 104, and a second doped region 114 is formed in the source/drain doped region 103, wherein the type of the doped ion of the second ion doping is the same as that of the doped ion of the source/drain doped region 103.

In the process of forming the second doped region 114, the anti-etching layer 104 can weaken the energy of doped ions, so that the situation that the excessive implantation energy of the doped ions causes excessive damage to the crystal lattice of the source-drain doped region 103, the doped ions are easy to rapidly diffuse into a channel region in the fin portion 101 through crystal lattice defects is avoided, and when the semiconductor structure works, depletion layers of a source electrode and a drain electrode of the source-drain doped region 103 are easy to expand, so that a short channel effect is caused.

Ions of the same type as the source-drain doped region 103 are doped in the source-drain doped region 103 exposed by the first opening 110, so that the doping ion concentration of the second doped region 114 is greater than that of the source-drain doped region 103. The second doped region 114 reduces the contact resistance between the contact plug formed later and the source/drain doped region 103.

In this embodiment, the second doped region 114 is formed by performing the second ion doping by ion implantation.

In this embodiment, the semiconductor structure is a PMOS, and the process parameters for forming the second doped region 114 include: the doping ions include: one or more of boron, gallium and indium.

The ion implantation energy should not be too large nor too small. If the implantation energy of the ions is too large, in the process of forming the second doped region 114, too large lattice damage is easily caused to the source-drain doped region 103, the subsequent annealing process is difficult to repair, and because the implantation energy is too large, the formed second doped region 114 is easily formed in the central region or the bottom region of the source-drain doped region 103, the subsequently formed contact plug is located in the top region of the source-drain doped region 103, and the contact plug is not easy to contact with the second doped region 114, so that the contact resistance between the contact plug and the source-drain doped region 103 is not easy to reduce. If the implantation energy of the ions is too small, it is easy to cause the ions to be difficult to penetrate through the anti-etching layer 104 and enter the source/drain doped region 103, resulting in poor formation quality of the second doped region 114, and the second doped region 114 is not easy to achieve the purpose of reducing the contact resistance between the contact hole plug and the source/drain doped region 103. In this embodiment, the implantation energy is 1Kev to 5Kev.

The ion implantation dose is not too large nor too small. If the ion implantation dose is too large, the ion doping concentration in the formed second doped region 114 is too large, the doped ions are easy to diffuse into the channel region in the fin portion 101, and when the semiconductor structure works, the depletion layers of the source and drain of the source/drain doped region 103 expand, so that the short channel effect is serious. If the implantation dose of the ions is too small, the doping concentration in the formed second doped region 114 is small, so that the contact resistance between the contact plug and the source/drain doped region 103 is not easily reduced. In this embodiment, the implantation dose of the dopant ions is 1E15 atoms per square centimeter to 3E15 atoms per square centimeter.

In this embodiment, the included angle between the ion implantation direction and the normal line of the substrate is 0 degrees. In the process of ion doping the source/drain doped region 103 exposed by the first opening 110, more doping ions are implanted into the source/drain doped region 103, so that the second doped region 114 is easily located under the first opening 110, which is beneficial to improving the doping concentration of the second doped region 114 and reducing the contact resistance between the contact plug formed subsequently and the source/drain doped region 103.

In other embodiments, the semiconductor structure is an NMOS, and the process parameters for forming the second doped region include: the doping ions include: one or more of phosphorus, arsenic and antimony; the injection energy is 1Kev to 5Kev; the implantation dosage of the doping ions is 1E15 atoms per square centimeter to 3E15 atoms per square centimeter; the included angle between the injection direction and the normal line of the substrate is 0 degree.

After the second doped region 114 is formed, the second doped region 114 is annealed, which is a spike annealing process or a laser annealing process. The peak annealing process and the laser annealing process are annealing processes commonly used in the semiconductor field, and are beneficial to improving process compatibility.

The annealing treatment can activate the doped ions in the second doped region 114 to repair the lattice defect, and because the annealing treatment is short, the ions in the second doped region 114 are not easy to diffuse into the channel region below the gate structure 109, so that the electric field intensity below the gate structure 109 is not easy to be too strong when the subsequent semiconductor structure works, and the gate structure 109 is not easy to be damaged.

Referring to fig. 12, the method for forming the semiconductor structure further includes: after forming the second opening 112, before forming the contact hole plug, the method further includes: and performing first ion doping on the source-drain doped region 103 exposed by the second opening 112 to form a first doped region 115, wherein the doping ion type of the first ion doping is the same as that of the source-drain doped region 103.

In the embodiment of the present invention, the doping ions of the first ion doping are the same as the doping ions of the source/drain doping region 103, so that the ion doping concentration of the first doping region 115 is higher than that of the source/drain doping region 103, and the first doping region 115 is beneficial to reducing the contact resistance between the source/drain doping region 103 and a subsequently formed contact plug, and improving the electrical performance of the semiconductor structure.

In this embodiment, the first doped region 115 is formed by performing a first ion doping on the source-drain doped region 103 exposed by the second opening 112 by using an ion implantation method.

In this embodiment, the semiconductor structure is a PMOS, and the process parameters for forming the first doped region 115 include: the doping ions include: one or more of boron, gallium and indium.

The ion implantation energy should not be too large nor too small. If the implantation energy is too large, in the process of forming the first doped region 115, too large lattice damage is easily caused to the source-drain doped region 103, the subsequent annealing process is difficult to repair, and because the implantation energy is too large, the formed first doped region 115 is located in the central region or the bottom region of the source-drain doped region 103, and the subsequently formed contact hole plug is located in the top region of the source-drain doped region 103, the contact hole plug is not easy to contact with the first doped region 115, and thus the contact resistance between the contact hole plug and the source-drain doped region 103 is not easy to reduce. If the implantation energy is too small, the formation quality of the first doped region 115 is easily poor, and the first doped region 115 is not easy to achieve the purpose of reducing the contact resistance between the contact hole plug and the source/drain doped region 103. In this embodiment, the implantation energy is 0.5Kev to 1Kev.

The ion implantation dose is not too large nor too small. If the ion implantation dose is too large, the ion doping concentration in the formed first doped region 115 is too large, the doped ions are easy to diffuse into the channel region in the fin portion 101, and when the semiconductor structure works, the depletion layers of the source and drain of the source/drain doped region 103 expand, so that the short channel effect is serious. If the implantation dose of the ions is too small, the doping concentration in the formed first doped region 115 is small, so that the contact resistance between the contact plug and the source/drain doped region 103 is not easily reduced. The implantation dose of the doping ions is 1E20 atoms per square centimeter to 5E20 atoms per square centimeter.

The angle between the ion implantation direction and the normal to the substrate 100 should not be too large or too small. If the included angle is too large, the first doped region 115 is easily formed due to the shielding effect of the ion implantation, so that less ions are doped into the source/drain doped region 103, resulting in a lower concentration of the first doped region 115. If the included angle is too small, the concentration of the doped ions at the two ends of the source-drain doped region 103 is smaller in the direction perpendicular to the extending direction of the gate structure 109 according to the shielding effect of the ion implantation, and the contact resistance between the subsequently formed contact plug and the two ends of the source-drain doped region 103 is larger, so that the electrical performance of the semiconductor structure is poor. In this embodiment, the angle between the ion implantation direction and the normal line of the substrate 100 is 0 to 7 degrees.

In other embodiments, when the semiconductor structure is used to form an NMOS, the first ion doped process parameters include: the doping ions include: one or more of phosphorus, arsenic and antimony; the injection energy is 0.5Kev to 1Kev; the implantation dosage of the doping ions is 1E20 atoms per square centimeter to 5E20 atoms per square centimeter; the included angle between the ion implantation direction and the normal line of the substrate is 0-7 degrees.

After the first doped region 115 is formed, the first doped region 115 is annealed. The description of the annealing process will be described with reference to the description after the formation of the second doped region 114, and will not be repeated here.

The method for forming the semiconductor structure further comprises the following steps: after forming the second openings 112, before forming the first doped regions 115, the source-drain doped regions 103 exposed by the second openings 112 are treated by a pre-amorphization process to form amorphized regions (not shown in the figure).

The amorphized region may be used to slow down the stress-retarding reaction (stress-retarded reaction) and increase the nucleation density, so that the metal silicide layer subsequently formed on the top surface of the source-drain doped region 103 is more uniform and thicker, thereby reducing the schottky barrier height between the metal silicide layer and the source-drain doped region 103, and reducing the contact resistance between the metal silicide layer and the source-drain doped region 103, and improving the electrical performance of the semiconductor structure.

Specifically, the pre-amorphization process is a pre-amorphization implant (PAI).

In this embodiment, the pre-amorphization implant ions are selected without changing the conductivity of the source drain doped regions 103.

Specifically, the pre-amorphization implant ions include: one or both of Ge and Si. In this embodiment, the pre-amorphization implant ions comprise Ge.

It should be noted that, after the pre-amorphization treatment is performed on the source-drain doped region 103, the amorphized region is formed, and the segregation coefficient of the N-type ions in the amorphized region is higher than the segregation coefficient of the N-type ions in the source-drain doped region 103, that is, the amorphized region can accommodate more N-type ions than the source-drain doped region 103. The forming of the first doped region 115 includes: the amorphized region is first ion doped to form the first doped region 115.

The method for forming the semiconductor structure further comprises the following steps: after the first doped region 115 is formed, a metal silicide layer 116 is formed on the source-drain doped region 103 exposed by the second opening 112.

The metal silicide layer 116 is used to reduce the contact resistance between the contact plug formed later and the source/drain doped region 103, and improve the electrical performance of the semiconductor structure.

The step of forming the metal silicide layer 116 includes: conformally covering a metal layer on the amorphized region; after the metal layer is formed, a salicide process is used to form the metal silicide layer 116.

In this embodiment, the material of the metal layer is one or two of nickel, titanium and platinum. Accordingly, the materials of the metal silicide layer 116 include: one or more of nickel silicon compound, titanium silicon compound and platinum silicon compound.

In the step of forming the metal layer, tellurium ions are doped in the source/drain doped regions 103.

The tellurium ions can reduce contact resistance, and improve the on-current of the semiconductor structure, so that the overall performance and reliability of the semiconductor structure are higher.

It should be noted that, in this embodiment, during the salicide process, the amorphized regions are all converted into the metal silicide layer 116. In other embodiments, only a portion of the thickness of the amorphized region may be converted into a metal silicide layer during the salicide process.

Referring to fig. 13, contact hole plugs 117 are formed in the first and second openings 110 and 112.

The contact plug 117 is used to make electrical connection within the semiconductor structure and also between the semiconductor structure and the semiconductor structure.

The step of forming the contact hole plug 117 includes: the first opening 110 (as shown in fig. 12) and the second opening 112 (as shown in fig. 12) are filled with a conductive material, the conductive material higher than the dielectric layer 111 is removed, and the conductive material in the first opening 110 and the second opening 112 serves as a contact plug 117.

The contact hole plug 117 located in the first opening 110 serves as a top contact hole plug 1172, and the contact hole plug 117 located in the second opening 112 serves as a bottom contact hole plug 1171.

The projection of the bottom end of the top contact plug 1172 onto the substrate 100 is in the projection of the bottom contact plug 1171 onto the substrate 100, that is, the area of the bottom contact plug 1171 is larger than the area of the bottom end of the top contact plug 1172. The contact of the bottom contact plug 1171 with the source drain doped region 103 reduces the contact resistance of the contact plug 117 with the source drain doped region 103 and improves the electrical performance of the semiconductor structure compared to the direct contact of the top contact plug 1171 with the source drain doped region 103.

In this embodiment, the contact plug 117 is made of W. In other embodiments, the material of the contact hole plug 117 may be Al, cu, ag, au, or the like.

Correspondingly, the embodiment of the invention also provides a semiconductor structure. Referring to fig. 13, a schematic structure diagram of an embodiment of the semiconductor structure of the present invention is shown.

The semiconductor structure includes: a substrate 100; a gate structure 109 on the substrate 100; source-drain doped regions 103 located in the substrate 100 at two sides of the gate structure 109; an interlayer dielectric layer 105 on the substrate 100, the source-drain doped region 103 and the sidewall of the gate structure 109, wherein the interlayer dielectric layer 105 exposes the top of the gate structure 109; an anti-etching layer 104 located between the gate structure 109 and the interlayer dielectric layer 105, and between the interlayer dielectric layer 105 and the substrate 100 where the source-drain doped region 103 is exposed; a contact plug 117 located on the source/drain doped region 103; the contact hole plug 117 includes a bottom contact hole plug 1171 and a top contact hole plug 1172 located on the bottom contact hole plug 1171, wherein a projection of a bottom end of the top contact hole plug 1172 onto the substrate 100 is located in a projection of the bottom contact hole plug 1171 onto the substrate 100; wherein the top contact plug 1172 is located in the interlayer dielectric layer 105, and the top of the top contact plug 1172 exposes the interlayer dielectric layer 105; the bottom contact plug 1171 is located in the etch resistant layer 104.

In the embodiment of the present invention, the projection of the bottom end of the top contact hole plug 1172 onto the substrate 100 is located in the projection of the bottom contact hole plug 1171 onto the substrate 100, that is, the area of the bottom contact hole plug 1171 is larger than the area of the bottom end of the top contact hole plug 1172. Compared with the situation that the top contact plug is electrically connected with the source-drain doped region, in the embodiment of the invention, the contact area between the bottom contact plug 1171 and the source-drain doped region 103 is larger, so that the contact resistance between the contact plug 117 and the source-drain doped region 103 is reduced, and the electrical performance of the semiconductor structure is improved.

In this embodiment, the semiconductor structure is a fin field effect transistor (FinFET), and the substrate 100 is a substrate 100 having a fin 101. In other embodiments, the semiconductor structure may be a planar structure, and accordingly, the substrate does not have a fin.

The gate structure 109 is used to control the opening and closing of the channel during operation of the semiconductor structure.

In this embodiment, the substrate 100 is a substrate 100 having a fin 101, and specifically, the source-drain doped region 103 is located in the fin 101 at two sides of the gate structure 109.

In this embodiment, the source-drain doped region 103 is used as the source and drain of the NMOS. Specifically, the material of the source-drain doped region 103 is silicon carbide or silicon phosphide doped with N-type ions. The N-type ions include one or more of P, as and Sb.

In other embodiments, the source-drain doped regions are used as the source and drain of the PMOS. Specifically, the source-drain doped region is made of silicon germanium doped with P-type ions. The P-type ions include one or more of B, ga and In.

The semiconductor structure further includes: a first doped region 115 located on the source/drain doped region 103, and the contact plug 117 located on the first doped region 115; the doping ion type in the first doping region 115 is the same as the doping ion type of the source drain doping region 103.

The doping ion type in the first doping region 115 is the same as the doping ion type of the source/drain doping region 103, so that the ion doping concentration of the first doping region 115 is higher than that in the source/drain doping region 103, and the first doping region 115 is beneficial to reducing the contact resistance between the source/drain doping region 103 and the contact hole plug 117 and improving the electrical performance of the semiconductor structure.

In this embodiment, when the semiconductor structure is a PMOS, the doping ions of the first doping 115 include: one or more of boron, gallium and indium.

It should be noted that the ion doping concentration of the first doped region 115 is not too high or too low. If the ion doping concentration is too high, the doping ions are easy to diffuse into the channel region in the fin portion 101, and when the semiconductor structure works, the depletion layers of the source and drain of the source/drain doped region 103 expand, resulting in serious short channel effect. If the ion doping concentration is too low, the doping concentration in the formed first doped region 115 is small, so that the contact resistance between the contact hole plug 117 and the source/drain doped region 103 is not easily reduced. In this embodiment, the doping concentration of the first doped region 115 is 1E25 atoms per cubic centimeter to 5E25 atoms per cubic centimeter.

In other embodiments, when the semiconductor structure is an NMOS formed, the doping ions of the first doped region include: one or more of phosphorus, arsenic and antimony; the first doped region has a doping concentration of 1E25 atoms per cubic centimeter to 5E25 atoms per cubic centimeter.

The semiconductor structure further includes: the second doped region 114 is located on the source-drain doped region 103 corresponding to the bottom end of the top contact plug 1172, and the doping ion type in the second doped region 114 is the same as the doping ion type of the source-drain doped region 103. The projection of the second doped region 114 onto the substrate 100 is located in the projection of the first doped region 115 onto the substrate 100.

The doping ion type in the second doped region 114 is the same as the doping ion type of the source/drain doped region 103, so that the ion doping concentration of the second doped region 114 is higher than the ion doping concentration in the source/drain doped region 103, and the second doped region 114 is beneficial to reducing the contact resistance between the source/drain doped region 103 and the contact hole plug 117 and improving the electrical performance of the semiconductor structure.

In this embodiment, when the semiconductor structure is a PMOS, the doping ions of the second doped region 114 include: one or more of boron, gallium and indium.

It should be noted that the ion doping concentration of the second doped region 114 is not too high or too low. If the ion doping concentration is too high, the doping ions are easy to diffuse into the channel region in the fin portion 101, and when the semiconductor structure works, the depletion layers of the source and drain of the source/drain doped region 103 expand, resulting in serious short channel effect. If the ion doping concentration is too low, the doping concentration in the formed second doped region 114 is smaller, so that the contact resistance between the contact hole plug 117 and the source/drain doped region 103 is not easily reduced. In this embodiment, the doping concentration of the second doped region 114 is 1E25 atoms per cubic centimeter to 5E25 atoms per cubic centimeter.

In other embodiments, when the semiconductor structure is an NMOS, the doping ions of the second doped region include: one or more of phosphorus, arsenic and antimony; the doping concentration of the second doping region is 1E25 atoms per cubic centimeter to 5E25 atoms per cubic centimeter.

The interlayer dielectric layer 105 is used to achieve electrical isolation between adjacent transistors. The interlayer dielectric layer 105 is made of an insulating material.

Specifically, the material of the interlayer dielectric layer 105 includes one or both of silicon oxide and silicon nitride. In this embodiment, the material of the interlayer dielectric layer 105 is silicon oxide. The silicon oxide is a dielectric material with common process and low cost, has high process compatibility, is beneficial to reducing the process difficulty and the process cost for forming the interlayer dielectric layer 105, has simple removal process, and has good adhesion between the silicon oxide and the anti-etching layer 104.

In the process of forming the semiconductor structure, an anti-etching layer 104 is formed on the source-drain doped region 103, on the fin portion 101 exposed by the source-drain doped region 103 and on the side wall of the gate structure 109; the process of forming the contact hole plug 117 generally includes: forming an interlayer dielectric layer 105 on the etching-resistant layer 104; etching the interlayer dielectric layer 105 to form a first opening 110 (as shown in fig. 9) exposing a portion of the etching resist layer 104; after removing the etching resist layer 104 on the source/drain doped region 103, forming a second opening 112 (as shown in fig. 11); contact hole plugs 117 formed in the first and second openings 110 and 112.

The method for forming the semiconductor structure further comprises the following steps: after the first opening 110 is formed and before the second opening 112 is formed, the etching resist layer 104 exposed by the first opening 112 is doped with second ions, and the doped ions pass through the etching resist layer 104 to form second doped regions 114 in the source-drain doped regions 103.

It should be noted that the etching resist layer 104 is not too thick or too thin. If the etching resist layer 104 is too thick, ions are not easy to pass through the etching resist layer 104 in the process of forming the second doped region 114, so that the doping concentration of the formed second doped region 114 is too low, which is not beneficial to reducing the contact resistance between the contact hole plug 117 and the source-drain doped region 103. If the etching-resistant layer 104 is too thin, the lattice of the source-drain doped region 103 is easily damaged during the formation of the second doped region 114, and the dopant ions are easily and rapidly diffused into the channel region in the fin portion 101 through lattice defects, so that the depletion layers of the source electrode and the drain electrode of the source-drain doped region 103 are easily expanded during the operation of the semiconductor structure, resulting in serious short channel effect. If the etching-resistant layer 104 is too thin, the depth of the second opening 112 is too small, and the contact hole plug 117 formed in the second opening 112 is thinner, resulting in a larger contact resistance between the bottom contact hole plug 1171 and the source/drain doped region 103, which is not beneficial to improving the electrical performance of the semiconductor structure. In this embodiment, the thickness of the etching resist layer 104 is 1 nm to 4 nm.

The etching-resistant layer 104 and the interlayer dielectric layer 105 have a higher etching selectivity, and the etching-resistant layer 104 and the source-drain doped region 103 have a higher etching selectivity, so that the interlayer dielectric layer 105 and the source-drain doped region 103 are not easily damaged in the process of removing the etching-resistant layer 104 on the source-drain doped region 103.

In this embodiment, the material of the anti-etching layer 104 is a dielectric material.

Specifically, the material of the etch-resistant layer 104 includes one or more of silicon oxide, silicon oxynitride, silicon carbonitride, and silicon nitride. In this embodiment, the material of the etching resist layer 104 is silicon nitride.

In other embodiments, the material of the interlayer dielectric layer 105 may be silicon nitride, and the material of the anti-etching layer 104 may be silicon oxide.

The semiconductor structure further includes: a dielectric layer 111 is disposed on the gate structure 109 and the interlayer dielectric layer 105, and the dielectric layer 111 covers a portion of the sidewall of the contact plug 117.

The dielectric layer 111 is used for realizing electrical isolation between later-stage metal layers formed later, and the material of the dielectric layer 111 is an insulating material. In this embodiment, the material of the dielectric layer 111 is silicon oxide.

The semiconductor structure further includes: a metal silicide layer 116 is located on the source-drain doped region 103.

The metal silicide layer 116 is used to reduce the contact resistance between the contact hole plug 117 and the source/drain doped region 103, and improve the electrical performance of the semiconductor structure.

Specifically, the materials of the metal silicide layer 116 include: one or both of platinum silicon compound and tellurium silicon compound.

The metal silicide layer 116 has tellurium ions formed therein. The tellurium ions can reduce contact resistance, improve conduction current in the channel, and enable the overall performance and reliability of the semiconductor structure to be higher.

In this embodiment, the metal silicide layer 116 is in direct contact with the source-drain doped region 103. In other embodiments, the semiconductor structure further comprises: and the amorphized region is positioned between the metal silicide layer and the source-drain doped region.

The semiconductor structure of this embodiment may be formed by the forming method described in the foregoing embodiment, or may be formed by other forming methods. For a specific description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiment, which is not repeated here.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A method of forming a semiconductor structure, comprising:

providing a substrate, wherein the substrate comprises a substrate, a gate structure positioned on the substrate, source and drain doped regions positioned in the substrate at two sides of the gate structure, an etching resistant layer positioned on the source and drain doped regions and an interlayer dielectric layer covering the etching resistant layer and the side wall of the gate structure, and the interlayer dielectric layer exposes the top of the gate structure;

etching the interlayer dielectric layer to form a first opening exposing part of the anti-etching layer;

the method for forming the semiconductor structure further comprises the following steps: forming a dielectric layer covering the gate structure and the interlayer dielectric layer before forming a first opening after providing the substrate; the dielectric layer is etched through in the process of forming the first opening;

After the first opening is formed, removing the etching resistant layer on the source-drain doping region to form a second opening, wherein the projection of the bottom end of the first opening on the substrate is positioned in the projection of the second opening on the substrate; in the process of forming the second opening, the etched rate of the anti-etching layer is larger than the etched rate of the interlayer dielectric layer and the source-drain doped region;

And forming contact hole plugs in the first opening and the second opening.

2. The method of forming a semiconductor structure of claim 1, wherein after forming the second opening, before forming the contact plug further comprises: and carrying out first ion doping on the source-drain doped region exposed by the second opening to form a first doped region, wherein the doping ion type of the first ion doping is the same as that of the source-drain doped region.

3. The method of forming a semiconductor structure of claim 1 or 2, wherein the material of the etch resistant layer comprises one or more of silicon oxide, silicon oxynitride, silicon carbonitride, and silicon nitride;

the interlayer dielectric layer is made of one or two of silicon oxide and silicon nitride.

4. The method of forming a semiconductor structure according to claim 1 or 2, wherein the step of providing a substrate forms the etch-resistant layer using a chemical vapor deposition process or an atomic layer deposition process.

5. The method of forming a semiconductor structure of claim 1 or 2, wherein the etch-resistant layer has a thickness of 1 nm to 4 nm.

6. The method of forming a semiconductor structure of claim 1 or 2, wherein the step of forming the second opening comprises: etching the anti-etching layer exposed by the first opening by adopting a dry etching process to form a groove exposing the source-drain doped region; and after forming the groove, etching the anti-etching layer on the source-drain doped region by adopting a wet etching process to form the second opening.

7. The method of forming a semiconductor structure of claim 6, wherein the process parameters of the dry etching process comprise: the etching gas includes: difluoromethane and carbon tetrafluoride; the flow rate of difluoromethane is 8sccm to 50sccm; the flow rate of carbon tetrafluoride is 30sccm to 200sccm.

8. The method of forming a semiconductor structure of claim 6, wherein the process parameters of the wet etching process comprise: the etching solution comprises: a phosphoric acid solution; the mass concentration of the phosphoric acid solution is 50 to 85 percent.

9. The method of claim 2, wherein the first doped region is formed by first ion doping the source/drain doped region exposed by the second opening by ion implantation.

10. The method of forming a semiconductor structure of claim 2, wherein when the semiconductor structure is used to form PMOS, the first ion doped process parameters comprise: the doping ions include: one or more of boron, gallium and indium; the injection energy is 0.5Kev to 1Kev; the implantation dose is 1E20 atoms per square centimeter to 5E20 atoms per square centimeter; the included angle between the injection direction and the normal line of the substrate is 0-7 degrees;

Or when the semiconductor structure is used for forming an NMOS, the first ion doped process parameters include: the doping ions include: one or more of phosphorus, arsenic and antimony; the injection energy is 0.5Kev to 1Kev; the implantation dose is 1E20 atoms per square centimeter to 5E20 atoms per square centimeter; the included angle between the implantation direction and the normal of the substrate is 0-7 degrees.

11. The method of forming a semiconductor structure of claim 2, wherein after forming the second opening, prior to forming the first doped region further comprises: processing the source-drain doped region exposed by the second opening by adopting a pre-amorphization process to form an amorphized region;

The method for forming the semiconductor structure further comprises the following steps: and after the first doped region is formed and before the contact hole plug is formed, forming a metal silicide layer on the source-drain doped region exposed by the second opening.

12. The method of forming a semiconductor structure of claim 11, wherein ions employed in the pre-amorphization process comprise one or both of Si and Ge.

13. The method of forming a semiconductor structure of claim 11, wherein the material of the metal silicide layer comprises: one or more of nickel silicon compound, titanium silicon compound and platinum silicon compound.

14. The method of forming a semiconductor structure of claim 1, wherein after forming the first opening, before forming the second opening, further comprises:

And carrying out second ion doping on the etching-resistant layer exposed by the first opening, wherein the doping ions penetrate through the etching-resistant layer to form a second doping region in the source-drain doping region, and the doping ion type of the second ion doping is the same as that of the source-drain doping region.

15. A semiconductor structure, comprising:

A substrate;

A gate structure located on the substrate;

The source-drain doped regions are positioned in the substrate at two sides of the grid structure;

The interlayer dielectric layer is positioned on the substrate, the source-drain doped region and the side wall of the grid structure, and the top of the grid structure is exposed out of the interlayer dielectric layer;

the anti-etching layer is positioned between the gate structure and the interlayer dielectric layer and between the interlayer dielectric layer and the substrate exposed by the source-drain doped region;

The contact hole plug is positioned on the source-drain doping region; the contact hole plug comprises a bottom contact hole plug and a top contact hole plug positioned on the bottom contact hole plug, wherein the projection of the bottom end of the top contact hole plug on the substrate is positioned in the projection of the bottom contact hole plug on the substrate; the top contact hole plug is positioned in the interlayer dielectric layer, and the top of the top contact hole plug is exposed out of the interlayer dielectric layer; the bottom contact hole plug is positioned in the etching resistant layer;

And the dielectric layer is positioned on the grid structure and the interlayer dielectric layer and covers part of the side wall of the contact hole plug.

16. The semiconductor structure of claim 15, wherein the semiconductor structure further comprises: the first doped region is positioned on the source-drain doped region, and the contact hole plug is positioned on the first doped region;

The doping ion type in the first doping region is the same as the doping ion type of the source-drain doping region.

17. The semiconductor structure of claim 15 or 16, wherein the material of the etch-resistant layer comprises one or more of silicon oxide, silicon oxynitride, silicon carbonitride, and silicon nitride;

18. The semiconductor structure of claim 15 or 16, wherein the etch-resistant layer has a thickness of 1 nm to 4 nm.

19. The semiconductor structure of claim 16, wherein when the semiconductor structure is PMOS, the dopant ions of the first doped region comprise: one or more of boron, gallium and indium; the doping concentration of the first doping region is 1E25 atoms per cubic centimeter to 5E25 atoms per cubic centimeter;

Or when the semiconductor structure is NMOS-forming, the doping ions of the first doping region include: one or more of phosphorus, arsenic and antimony; the first doped region has a doping concentration of 1E25 atoms per cubic centimeter to 5E25 atoms per cubic centimeter.

20. The semiconductor structure of claim 15 or 16, wherein the semiconductor structure further comprises: and the metal silicide layer is positioned on the source-drain doped region.