CN112133679A - 半导体装置 - Google Patents
半导体装置 Download PDFInfo
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- CN112133679A CN112133679A CN202010342804.5A CN202010342804A CN112133679A CN 112133679 A CN112133679 A CN 112133679A CN 202010342804 A CN202010342804 A CN 202010342804A CN 112133679 A CN112133679 A CN 112133679A
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- semiconductor chip
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- redistribution layer
- pad
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Abstract
提供了半导体装置,所述半导体装置可以包括:第一半导体芯片;第一重新分布层,位于第一半导体芯片的底表面上;第二半导体芯片,位于第一半导体芯片上;第二重新分布层,位于第二半导体芯片的底表面上;模制层,在第一半导体芯片的侧壁和第二半导体芯片的侧壁上以及第一半导体芯片的底表面上延伸;以及外部端子,延伸穿过模制层并且电连接到第一重新分布层。第二重新分布层可以包括暴露部分。第一重新分布层可以包括电连接到第一半导体芯片的第一导电图案以及与第一半导体芯片电绝缘的第二导电图案。第二重新分布层的暴露部分和第一重新分布层的第二导电图案可以通过第一连接引线电连接。
Description
本专利申请要求于2019年6月25日在韩国知识产权局提交的第10-2019-0075970号韩国专利申请的优先权,该韩国专利申请的公开内容通过引用全部包含于此。
技术领域
发明构思的实施例涉及半导体装置和用于制造该半导体装置的方法。
背景技术
近来,电子市场中对便携式装置的需求已经越来越大,因此已经需要高性能、小且轻的电子组件。具体地,对高性能半导体存储器装置的需求已经越来越大。例如,已经需求具有高带宽和/或高处理能力的半导体存储器装置。
将多个独立组件集成在单个封装件中的半导体封装技术以及使独立组件的尺寸减小的技术可以有益于实现小且轻的电子组件。具体地,用于处理高频信号的半导体封装件可以有益于具有优异的电特性以及小的尺寸。
晶圆级封装件可以是其中半导体芯片的垫(pad,或称为“焊盘”)在无需附加的印刷电路板(PCB)的情况下通过重新分布工艺以晶圆级连接到封装件的焊料球的半导体封装件。
发明内容
发明构思的实施例可以提供具有改善的电特性的半导体装置。
发明构思的实施例还可以提供具有改善的结构稳定性的半导体装置。
发明构思的实施例还可以提供能够简化工艺并降低制造成本的用于制造半导体装置的方法。
根据发明构思的一些实施例,半导体装置可以包括:第一半导体芯片;第一重新分布层,位于第一半导体芯片的底表面上;第二半导体芯片,位于第一半导体芯片上;第二重新分布层,位于第二半导体芯片的底表面上;模制层,在第二半导体芯片的侧壁、第一半导体芯片的侧壁和第一半导体芯片的底表面上延伸;以及外部端子,延伸穿过模制层并且电连接到第一重新分布层。第二重新分布层可以包括不与第一半导体芯片叠置的暴露部分。第一重新分布层可以包括电连接到第一半导体芯片的第一导电图案以及与第一半导体芯片电绝缘的第二导电图案。第二重新分布层的暴露部分和第一重新分布层的第二导电图案可以通过第一连接引线彼此电连接。
根据发明构思的一些实施例,半导体装置可以包括:第一半导体芯片,包括第一有效表面和与第一有效表面背对的第一非有效表面;第一垫,位于第一有效表面上;以及第二半导体芯片,位于第一半导体芯片上。第二半导体芯片可以包括面对第一半导体芯片的第一非有效表面的第二有效表面,并且第二半导体芯片可以与第一半导体芯片竖直地间隔开且可以横向地突出超过第一半导体芯片的第一侧面。第一半导体芯片可以暴露第二半导体芯片的第二有效表面的暴露部分。所述半导体装置还可以包括:第二垫,位于第二半导体芯片的第二有效表面的暴露部分上;外部端子,位于第一半导体芯片的第一有效表面上;以及模制层,从第一半导体芯片的侧壁和第二半导体芯片的侧壁延伸到第一半导体芯片的第一有效表面上。模制层可以至少部分地覆盖外部端子的侧面,并且第一垫和第二垫可以通过第一连接引线彼此电连接。
根据发明构思的一些实施例,半导体装置可以包括:第一半导体芯片;第一垫,位于第一半导体芯片的底表面上;以及第二半导体芯片,位于第一半导体芯片上。第二半导体芯片中的每个可以突出超过第一半导体芯片的相应的侧面,并且可以包括底表面,底表面可以包括被第一半导体芯片暴露的暴露部分。所述半导体装置还可以包括:第二垫,第二垫中的每个位于第二半导体芯片中的相应的第二半导体芯片的底表面的暴露部分上;以及第三垫,位于第一半导体芯片的底表面上。第三垫可以与第一垫间隔开。所述半导体装置还可以包括:连接端子,连接端子中的每个将第一垫中的一个电连接到第二垫中的一个;外部端子,位于第一半导体芯片的底表面上;以及模制层,覆盖第一半导体芯片的底表面和第二半导体芯片的底表面。外部端子中的每个可以电连接到第一垫和第三垫中的相应的垫。模制层可以与外部端子的侧面接触。从第一半导体芯片的底表面到模制层的底表面的距离可以在从第一半导体芯片的底表面到外部端子中的一个的底端的距离的大约10%至50%的范围内。第二半导体芯片中的最上面的第二半导体芯片的顶表面可以与模制层的最顶端共面。
根据发明构思的一些实施例,用于制造半导体装置的方法可以包括:将第一半导体芯片粘附到载体基底上,第一半导体芯片在其与载体基底背对的一个表面上包括第一重新分布层;在第一半导体芯片上移位堆叠第二半导体芯片以暴露第一重新分布层的一部分,第二半导体芯片在其与第一半导体芯片背对的一个表面上包括第二重新分布层;通过连接引线将第一重分布层的暴露部分连接到第二重分布层;形成覆盖第一半导体芯片、第二半导体芯片和连接引线的模制层;以及去除载体基底。
附图说明
鉴于附图和所附详细描述,发明构思将变得更加清楚。
图1A是示出根据发明构思的一些实施例的半导体装置的剖视图。
图1B是示出根据发明构思的一些实施例的半导体装置的平面图。
图2A、图3A、图4A、图5A和图6A是示出根据发明构思的一些实施例的半导体装置的剖视图。
图2B、图3B、图4B、图5B和图6B是示出根据发明构思的一些实施例的半导体装置的平面图。
图7至图11是示出根据发明构思的一些实施例的用于制造半导体装置的方法的剖视图。
具体实施方式
在下文中将参照附图描述根据发明构思的半导体装置。
图1A是示出根据发明构思的一些实施例的半导体装置的剖视图。图1B是示出根据发明构思的一些实施例的半导体装置的平面图。图1A与沿着图1B的线A-A'截取的剖视图对应。
参照图1A和图1B,第一单元结构100可以被设置。第一单元结构100可以包括第一半导体芯片110和第一重新分布层120,第一重新分布层120设置在第一半导体芯片110的一个表面上。
第一半导体芯片110可以被设置。第一半导体芯片110可以具有前表面和后表面。在本说明书中,前表面可以是与半导体芯片中的集成元件或组件的有效表面相邻的表面,并且可以被定义为其上形成有半导体芯片的垫的表面。后表面可以被定义为与前表面背对的另一表面。例如,第一半导体芯片110可以包括设置在其前表面上的第一芯片垫。第一半导体芯片110可以具有在第一方向D1彼此背对且彼此间隔开的第一侧壁110a和第二侧壁110b。在下文中,第一方向D1和第二方向D2可以与第一半导体芯片110的后表面平行并且可以彼此垂直,第三方向D3可以与第一半导体芯片110的后表面垂直。第一半导体芯片110可以是存储器芯片,诸如DRAM、SRAM、MRAM或闪存。在一些实施例中,第一半导体芯片110可以是逻辑芯片。第一半导体芯片110可以包括半导体材料,诸如硅(Si)。这里,术语“侧壁”可以与“侧(侧面)”互换。第一重新分布层120可以设置在第一半导体芯片110的前表面上。第一重新分布层120可以使第一半导体芯片110的第一芯片垫重新分布。第一重新分布层120可以包括第一导电图案122和第一绝缘层124。第一绝缘层124可以覆盖第一半导体芯片110的前表面,并且可以暴露第一导电图案122的部分。第一导电图案122的被第一绝缘层124暴露的部分可以用作第一导电图案122的垫,其可以电连接到外部装置。在下文中,整个导电图案(例如,第一导电图案122)被称为导电图案,而导电图案的暴露部分被称为垫。在一些实施例中,附加连接垫可以设置在第一导电图案122的暴露部分上。当在平面图中观看时,第一导电图案122的垫(例如,第一连接垫CP1和第二连接垫CP2)可以设置在第一半导体芯片110内侧。换言之,第一半导体芯片110和第一重新分布层120可以呈扇入封装件的形式。出于描述发明构思的目的,示出了图1B中的第一导电图案122的数量和布置作为示例。然而,发明构思的实施例不限于此。第一绝缘层124可以包括例如氧化物(例如,氧化物层)。例如,第一绝缘层124可以包括氧化硅(SiOx)。“元件A覆盖元件B的表面”(或类似的语言)意味着元件A位于元件B的表面上,但不必然意味着元件A完全覆盖元件B的表面。第一半导体芯片110的有效表面可以是其上设置有第一重新分布层120的表面。在一些实施例中,第一重新分布层120可以如图1A中所示与第一半导体芯片110的有效表面直接地且物理地接触。
第一导电图案122可以包括第一子图案SP1和第二子图案SP2。第二子图案SP2可以与第一子图案SP1间隔开。例如,第一子图案SP1可以设置在第一半导体芯片110的前表面的第一区域R1上,第二子图案SP2可以设置在第一半导体芯片110的前表面的第二区域R2上。第一区域R1可以位于第二区域R2的在第一方向D1上的一侧处。在一些实施例中,第一区域R1可以如图1B中所示与第一半导体芯片110的第二侧壁110b相邻。第一子图案SP1可以电连接到第一半导体芯片110。在一些实施例中,第一子图案SP1可以电连接到第一半导体芯片110的元件(例如,诸如位线的导线、晶体管和电容器)。第二子图案SP2可以与第一半导体芯片110电绝缘。在一些实施例中,第二子图案SP2可以不与第一半导体芯片110的任何元件电连接。第一子图案SP1的一部分和第二子图案SP2的一部分可以被第一绝缘层124暴露并且可以用作垫。这里,第一子图案SP1的暴露部分可以被定义为第一连接垫CP1,并且可以是电连接到第一半导体芯片110的垫。第二子图案SP2的暴露部分可以被定义为第二连接垫CP2,并且可以是与第一半导体芯片110绝缘(例如,与第一半导体芯片110电绝缘)的垫。换言之,第二连接垫CP2可以是与第一半导体芯片110和第一重新分布层120的第一子图案SP1电隔离(或浮置)的垫。在一些实施例中,第一子图案SP1的第一连接垫CP1可以电连接到第一半导体芯片110的元件,第二子图案SP2的第二连接垫CP2可以不与第一半导体芯片110的任何元件电连接。
在一些实施例中,第一子图案SP1和第二子图案SP2可以彼此电连接。换言之,第一子图案SP1和第二子图案SP2两者可以电连接到第一半导体芯片110。在下文中,作为示例将描述与第一半导体芯片110电绝缘的第二子图案SP2。
外部端子130可以设置在第一半导体芯片110的前表面上。外部端子130可以设置在第一连接垫CP1和第二连接垫CP2上。外部端子130可以不设置在第二连接垫CP2中的一些上。外部端子130可以包括连接到第一连接垫CP1的第一端子132和连接到第二连接垫CP2的第二端子134。这里,第一连接端子BW1可以连接到第二连接垫CP2中的其他第二连接垫CP2。这将稍后被详细描述。第一端子132可以电连接到第一半导体芯片110,并且第二端子134可以与第一半导体芯片110电绝缘。在一些实施例中,第一端子132可以电连接到第一半导体芯片110的元件,第二端子134可以不与第一半导体芯片110的任何元件电连接。在图1B中,为了示出的简化,未示出外部端子130。
第二单元结构200可以设置在第一单元结构100上。如图1A中所示,第一单元结构100和第二单元结构200可以以偏移堆叠(offset stack)结构的形式设置。例如,第一单元结构100和第二单元结构200可以在与第一方向D1相反的方向上倾斜地堆叠,并且该形状可以是在第一方向D1的相反方向上向上倾斜的阶梯形状。详细地,第二单元结构200的一部分可以与第一单元结构100叠置,并且第二单元结构200的另一部分可以横向地突出超过第一单元结构100的一个侧壁。第二单元结构200可以横向地突出超过第一半导体芯片110的第一侧壁110a。换言之,当在平面图中观看时,第二单元结构200可以堆叠在第一单元结构100上,以在第一方向D1的相反方向上从第一单元结构100移位。第二单元结构200可以包括第二半导体芯片210和第二重新分布层220,第二重新分布层220设置在第二半导体芯片210的一个表面上。在一些实施例中,第二单元结构200的在第一方向D1上的中心可以如图1A中所示从第一单元结构100的在第一方向D1上的中心朝向第一方向D1的相反方向偏移。在这里所提及的“元件A与元件B叠置”(或类似的语言)意味着元件A在第三方向D3上与元件B叠置,并且存在沿第三方向D3延伸且与元件A和元件B两者相交的至少一条线。第二半导体芯片210的有效表面可以是其上设置有第二重新分布层220的表面。在一些实施例中,第二重新分布层220可以如图1A中所示与第二半导体芯片210的有效表面直接地且物理地接触。
第二半导体芯片210可以设置在第一半导体芯片110上。第二半导体芯片210可以设置在第一半导体芯片110的后表面上。第二半导体芯片210的构造可以与第一半导体芯片110的构造基本相同或相似。例如,第二半导体芯片210的尺寸(例如,长度、宽度和高度)可以等于第一半导体芯片110的尺寸。在一些实施例中,第二半导体芯片210的长度、宽度和高度可以小于第一半导体芯片110的长度、宽度和高度。第二半导体芯片210可以具有与有效表面对应的前表面和与非有效表面对应的后表面。例如,第二半导体芯片210可以包括设置在其前表面上的第二芯片垫。第二半导体芯片210的前表面可以面对第一半导体芯片110。第二半导体芯片210可以是例如存储器芯片,诸如DRAM、SRAM、MRAM或闪存。第二半导体芯片210可以包括半导体材料,诸如硅(Si)。
第二重新分布层220可以设置在第二半导体芯片210的前表面上。第二重新分布层220可以使第二半导体芯片210的第二芯片垫重新分布。第二重新分布层220可以包括第二导电图案222和第二绝缘层224。第二绝缘层224可以覆盖第二半导体芯片210的前表面,但可以暴露第二导电图案222的部分。第二导电图案222的被第二绝缘层224暴露的部分可以用作第二导电图案222的垫,其可以电连接到外部装置。在一些实施例中,附加连接垫可以设置在第二导电图案222的暴露部分上。在下文中,第二导电图案222的用作垫的暴露部分可以被称为第一垫PAD1。当在平面图中观看时,第一垫PAD1可以设置在第二半导体芯片210内侧。换言之,第二半导体芯片210和第二重新分布层220可以呈扇入封装件的形式。第二绝缘层224可以包括例如氧化物(例如,氧化物层)。第二导电图案222可以电连接到第二半导体芯片210。当在平面图中观看时,第一垫PAD1可以设置在第二半导体芯片210的前表面的在第一方向D1的相反方向上的一个侧部上。
第二重新分布层220可以与第一半导体芯片110的后表面接触。这里,因为第一单元结构100和第二单元结构200以阶梯形状堆叠,所以第二半导体芯片210的前表面(或第二单元结构200的前表面)的一部分可以被暴露。第二半导体芯片210的前表面的该部分可以被第一半导体芯片110暴露。第二半导体芯片210的暴露的前表面可以是有效表面。例如,当在平面图中观看时,第一垫PAD1可以设置在第一半导体芯片110的第一侧壁110a的一侧处。第一垫PAD1可以被暴露在第二半导体芯片210下方。在一些实施例中,如图1B中所示,当在平面图中观看时,第一垫PAD1可以与第一半导体芯片110的第一侧壁110a相邻。
第二连接垫CP2中的一些可以通过第一连接端子BW1电连接到第一垫PAD1。换言之,外部端子130可以连接到第二连接垫CP2中的一些,并且第一连接端子BW1可以连接到第二连接垫CP2中的其他第二连接垫CP2。第一连接端子BW1可以是用于引线键合的连接引线。第一连接端子BW1可以连接到位于第一半导体芯片110的前表面上的第二连接垫CP2中的一些,并且可以连接到第二半导体芯片210的前表面上的第一垫PAD1。这里,其上设置有第二子图案SP2的第二区域R2可以与第一半导体芯片110的第一侧壁110a相邻设置。换言之,第二区域R2可以与第一垫PAD1相邻设置。因此,第一连接端子BW1的长度可以是短的。第一连接端子BW1可以在与第三方向D3相反的方向上从第二连接垫CP2和第一垫PAD1延伸。换言之,第一连接端子BW1的最底端可以位于比第一半导体芯片110的底表面和第一重新分布层120的底表面低的水平处。第一半导体芯片110可以通过第一重新分布层120的第一连接垫CP1电连接到第一端子132,第二半导体芯片210可以通过第二重新分布层220的第一垫PAD1、第一连接端子BW1和第一重新分布层120的第二连接垫CP2电连接到第二端子134。
在一些实施例中,第一半导体芯片110的元件可以通过第一重新分布层120的第一连接垫CP1电连接到一个或多个第一端子132,第二半导体芯片210的元件可以通过第二重新分布层220的第一垫PAD1、第一连接端子BW1和第一重新分布层120的第二连接垫CP2电连接到一个或多个第二端子134。在这里提及的“元件A连接到元件B”(或类似的语言)意味着元件A物理连接和/或电连接到元件B。如在这里使用的术语“和/或”包括相关联的所列项中的一个或更多个的任何组合和全部组合。
在一些实施例中,第一连接端子BW1可以如图1A中所示呈细线的形式,并且第一连接端子BW1的相对端分别与一个第一垫PAD1和一个第二连接垫CP2直接接触。
根据发明构思的实施例,第二半导体芯片210可以通过利用第一重新分布层120来连接到(例如,电连接到)外部端子130,外部端子130用于电连接到外部(例如,外部装置)。因此,能够提供不需要用于第二半导体芯片210的电连接和重新分布的附加组件而结构简单且有利于小型化的半导体装置。
此外,第一半导体芯片110和第二半导体芯片210可以分别连接到第一重新分布层120中的彼此电绝缘的子图案SP1和SP2,因此可以使半导体装置的带宽增大。
此外,连接到第二半导体芯片210的第二连接垫CP2可以与第一垫PAD1相邻设置,因此第二半导体芯片210与外部端子130之间的电连接可以是短的,因而半导体装置的电特性可以改善。
根据发明构思的实施例,第二半导体芯片210可以通过第一连接端子BW1连接到第一重新分布层120。换言之,可以不需要通过高成本的制造工艺所形成的组件(例如,贯穿过孔),因此根据发明构思的制造工艺可以是简单的和廉价的,并且具有简单结构的半导体装置可以被提供。
在一些实施例中,第一子图案SP1和第二子图案SP2可以彼此电连接。第二半导体芯片210和第一半导体芯片110可以通过第一重新分布层120的第一导电图案122彼此电连接,并且可以一起连接到外部端子130。在这种情况下,第一半导体芯片110和第二半导体芯片210可以是执行相同的功能的半导体芯片,并且可以处理和传输相同的信号。当第一半导体芯片110和第二半导体芯片210连接到相同的导电图案时,半导体装置的处理能力可以提高。
再次参照图1A和图1B,第一粘合层230可以设置在第一单元结构100和第二单元结构200之间。第一粘合层230可以设置在第一半导体芯片110的后表面与第二重新分布层220之间,第二重新分布层220设置在第二半导体芯片210的前表面上。换言之,第一粘合层230可以使第二重新分布层220粘附到第一半导体芯片110的后表面。第一粘合层230可以包括例如裸片附着膜(die attach film,DAF)。第二单元结构200可以通过第一粘合层230粘附到第一单元结构100。
模制层140可以被设置。模制层140可以覆盖第一单元结构100的侧壁和第二单元结构200的侧壁。模制层140可以延伸到第一半导体芯片110的前表面上,以覆盖第一重新分布层120。模制层140可以与连接到第一重新分布层120的外部端子130的侧壁接触。这里,从第一重新分布层120的底表面到模制层140的底表面的第一距离d1可以在从第一重新分布层120的底表面到外部端子130的最底端的第二距离d2的大约1/10至大约1/2(即,大约10%至大约50%)的范围内。换言之,模制层140可以暴露外部端子130的下部,并且外部端子130的暴露的下部的体积可以是外部端子130的总体积的至少1/2或更大。模制层140可以掩埋或覆盖第一连接端子BW1。例如,从第一重新分布层120的底表面到第一连接端子BW1的最底端的第三距离d3可以比从第一重新分布层120的底表面到模制层140的底表面的第一距离d1小。换言之,第一连接端子BW1的最底端可以位于比第一重新分布层120的底表面低且比模制层140的底表面高的水平处。模制层140可以暴露第二半导体芯片210的后表面。例如,模制层140的最顶端可以与第二半导体芯片210的后表面位于同一水平处。模制层140可以包括例如环氧模制化合物(EMC)。在一些实施例中,模制层140的最顶端可以如图1A中所示与第二半导体芯片210的后表面共面。
根据发明构思的实施例,模制层140可以覆盖第一半导体芯片110的侧壁和第二半导体芯片210的侧壁,并且还可以覆盖第一半导体芯片110的前表面(或第一重新分布层120的底表面)。换言之,模制层140可以从下方覆盖第一单元结构100和第二单元结构200的堆叠结构,并且可以稳固地保护第一半导体芯片110和第二半导体芯片210。具体地,模制层140可以保护第一半导体芯片110和第二半导体芯片210的角部分。
此外,模制层140可以不覆盖第二半导体芯片210的后表面,因此半导体装置的高度可以减小,并且半导体装置的尺寸可以减小。由于模制层140可以不在第二半导体芯片210的后表面上延伸,所以模制层140不会使半导体装置的高度增大。
图2A和图3A是示出根据发明构思的一些实施例的半导体装置的剖视图。图2B和图3B是示出根发明构思的一些实施例的半导体装置的平面图。图2A与沿着图2B的线B-B'截取的剖视图对应,图3A与沿着图3B的线C-C'截取的剖视图对应。在下面的实施例中,与图1A和图1B的实施例中的组件相同或相似的组件将由相同的附图标号或标记表示,并且出于容易和方便解释的目的,将省略或简要提及对其的描述。换言之,将主要描述下面的实施例与图1A和图1B的实施例之间的差异。
参照图2A和图2B,第三单元结构300可以设置在第二单元结构200上。第一单元结构100、第二单元结构200和第三单元结构300可以以偏移堆叠结构的形式堆叠。例如,第一单元结构100、第二单元结构200和第三单元结构300可以在第一方向D1的相反方向上倾斜地堆叠,并且该形状可以是在第一方向D1的相反方向上向上倾斜的阶梯形状。详细地,第三单元结构300的一部分可以与第二单元结构200叠置,并且第三单元结构300的另一部分可以横向地突出超过第二单元结构200的一个侧壁。第三单元结构300可以在第一方向D1的相反方向上从第二半导体芯片210突出。换言之,当在平面图中观看时,第三单元结构300可以堆叠在第二单元结构200上,以在第一方向D1的相反方向上从第二单元结构200移位。与图2A和图2B不同,第三单元结构300可以设置为多个。多个第三单元结构300可以偏移堆叠在第二单元结构200上。第三单元结构300可以包括第三半导体芯片310和设置在第三半导体芯片310的一个表面上的第三重新分布层320。
第三半导体芯片310可以设置在第二半导体芯片210上。第三半导体芯片310可以设置在第二半导体芯片210的后表面上。第三半导体芯片310可以与第二半导体芯片210基本相同。然而,发明构思的实施例不限于此。第三半导体芯片310可以具有前表面和后表面,所述前表面面向第二半导体芯片210,所述后表面与第三半导体芯片310的前表面背对。
第三重新分布层320可以设置在第三半导体芯片310的前表面上。第三重新分布层320可以包括第三导电图案322和第三绝缘层324。第三绝缘层324可以覆盖第三半导体芯片310的前表面,但可以暴露第三导电图案322的部分。第三导电图案322的被第三绝缘层324暴露的部分可以用作第三导电图案322的垫,其可以电连接到外部装置。在下文中,第三导电图案322的用作垫的暴露部分可以被称为第二垫PAD2。第三导电图案322可以电连接到第三半导体芯片310。当在平面图中观看时,第二垫PAD2可以设置在第三半导体芯片310的前表面的位于与第一方向D1相反的方向上的一个侧部上。在一些实施例中,第三导电图案322可以电连接到第三半导体芯片310的元件(例如,诸如位线的导线、晶体管和电容器)。
第三重新分布层320可以与第二半导体芯片210的后表面接触。这里,因为第二单元结构200和第三单元结构300以阶梯形状堆叠,所以第三半导体芯片310的前表面(或第三单元结构300的前表面)的一部分可以被暴露。第三半导体芯片310的暴露的前表面可以是有效表面。例如,当在平面图中观看时,第二垫PAD2可以设置在第二半导体芯片210的位于第一方向D1的相反方向上的一侧处。第二垫PAD2可以被暴露在第三半导体芯片310下方。在一些实施例中,第二单元结构200可以如图2A中所示暴露第三半导体芯片310的前表面的一部分。此外,在一些实施例中,如图2B中所示,当在平面图中观看时,第二垫PAD2可以与第二半导体芯片210的一侧相邻。
第三半导体芯片310可以电连接到第一单元结构100的第一重新分布层120。例如,第二连接垫CP2中的一些可以通过第二连接端子BW2电连接到第二垫PAD2。第二连接端子BW2可以是用于引线键合的连接引线。第二连接端子BW2可以连接到位于第一半导体芯片110的前表面上的第二连接垫CP2中的一些,并且可以连接到位于第三半导体芯片310的前表面上的第二垫PAD2。这里,其上设置有第二子图案SP2的第二区域R2可以与第一半导体芯片110的第一侧壁110a相邻设置,因此第二连接端子BW2的长度可以是短的。第二连接端子BW2的最底端可以位于比第一半导体芯片110的前表面和第一重新分布层120的底表面低的水平处。
第一连接端子BW1和第二连接端子BW2可以连接到彼此不同的第二连接垫CP2。第一连接端子BW1所连接到的第一子连接垫SCP1可以与第二连接端子BW2所连接到的第二子连接垫SCP2绝缘。第二半导体芯片210和第三半导体芯片310可以分别连接到第一重新分布层120中的彼此电绝缘的导电图案,因此半导体装置的带宽可以增大。
可选择地,第一子连接垫SCP1可以电连接到第二子连接垫SCP2。在这种情况下,第二半导体芯片210和第三半导体芯片310可以是执行相同的功能的半导体芯片,并且可以处理和传输相同的信号。当第二半导体芯片210和第三半导体芯片310连接到相同的导电图案时,半导体装置的处理能力可以提高。
在一些实施例中,第二连接端子BW2可以使第一垫PAD1和第二垫PAD2连接。如图3A和图3B中所示,第二连接端子BW2可以连接到位于第二半导体芯片210的前表面上的第一垫PAD1,并且可以连接到位于第三半导体芯片310的前表面上的第二垫PAD2。第三半导体芯片310可以通过第三重新分布层320的第二垫PAD2、第二连接端子BW2、第二重新分布层220的第一垫PAD1、第一连接端子BW1和第一重新分布层120的第二连接垫CP2电连接到外部端子130。在这种情况下,第二半导体芯片210和第三半导体芯片310可以是执行相同的功能的半导体芯片。当第二半导体芯片210和第三半导体芯片310通过第一垫PAD1公共地连接到第二子图案SP2时,半导体装置的处理能力可以提高。
第二粘合层330可以设置在第二单元结构200与第三单元结构300之间。第二粘合层330可以设置在第二半导体芯片210的后表面与第三重新分布层320之间,第三重新分布层320设置在第三半导体芯片310的前表面上。换言之,第二粘合层330可以使第三重新分布层320粘附到第二半导体芯片210的后表面。第三单元结构300可以通过第二粘合层330粘附到第二单元结构200。
模制层140可以被设置。模制层140可以覆盖第一单元结构100、第二单元结构200和第三单元结构300的侧壁。模制层140可以延伸到第一半导体芯片110的前表面上,以覆盖第一重新分布层120。模制层140可以与连接到第一重新分布层120的外部端子130的侧壁接触。模制层140可以掩埋或覆盖第二连接端子BW2。模制层140可以暴露第三半导体芯片310的后表面。例如,模制层140的最顶端可以与第三半导体芯片310的后表面位于同一水平处。在一些实施例中,模制层140的最顶端可以如图3A中所示与第三半导体芯片310的后表面共面。
图4A是示出根据发明构思的一些实施例的半导体装置的剖视图。图4B是示出根据发明构思的一些实施例的半导体装置的平面图。图4A与沿着图4B的线D-D'截取的剖视图对应。在下文中,将主要描述下面的实施例与图2A和图2B的实施例之间的差异。
参照图4A和图4B,第一单元结构100可以被设置。第一单元结构100可以包括第一半导体芯片110和设置在第一半导体芯片110的前表面上的第一重新分布层120。第一重新分布层120可以包括第一导电图案122和第一绝缘层124。第一导电图案122还可以包括第三子图案SP3。第三子图案SP3可以与第一子图案SP1间隔开。例如,第三子图案SP3可以设置在第一半导体芯片110的前表面的第三区域R3上。第三区域R3可以位于第一区域R1的在第一方向D1上的一侧处。第三子图案SP3可以与第一半导体芯片110电绝缘。第三子图案SP3的一部分可以被第一绝缘层124暴露。第二子图案SP2的暴露部分可以是与第一半导体芯片110绝缘的第三连接垫CP3,第三子图案SP3的暴露部分可以是与第一半导体芯片110绝缘的第四连接垫CP4。在一些实施例中,第三子图案SP3可以不与第一半导体芯片110的任何元件电连接。此外,在一些实施例中,第三连接垫CP3和第四连接垫CP4中的每者可以不与第一半导体芯片110的任何元件电连接。更进一步地,在一些实施例中,第三区域R3可以如图4B中所示与第一区域R1的一侧相邻。
第三单元结构300'可以设置在第二单元结构200上。第三单元结构300'的构造可以与参照图2A和图2B描述的第三单元结构300的构造相似。第二单元结构200和第三单元结构300'可以在第一方向D1上倾斜地堆叠。当在平面图中观看时,第三单元结构300'可以堆叠在第二单元结构200上,以在第一方向D1上从第二单元结构200移位。换言之,第一单元结构100、第二单元结构200和第三单元结构300'可以堆叠为彼此水平交错。这里,当在平面图中观看时,第三单元结构300'可以在第一方向D1上从第二半导体芯片210突出,并且还可以突出超过第一半导体芯片110的第二侧壁110b。
第三半导体芯片310可以设置在第二半导体芯片210的后表面上。第三单元结构300'的第三重新分布层320可以包括第三导电图案322和第三绝缘层324。第三绝缘层324可以覆盖第三半导体芯片310的前表面,但可以暴露第三导电图案322的一部分(即,第二垫PAD2)。当在平面图中观看时,第二垫PAD2可以设置在第三半导体芯片310的前表面的在第一方向D1上的一个侧部上。
因为第二单元结构200和第三单元结构300'以阶梯形状堆叠,所以第三半导体芯片310的前表面(或第三单元结构300'的前表面)的一部分可以被暴露。例如,当在平面图中观看时,第二垫PAD2可以设置在第二半导体芯片210的在第一方向D1上的一侧处。第二垫PAD2可以被暴露在第三半导体芯片310下方。在一些实施例中,第二单元结构200可以如图4A中所示暴露第三半导体芯片310的前表面的部分。此外,在一些实施例中,第二垫PAD2可以如图4B中所示与第二半导体芯片210的一侧相邻。
第三半导体芯片310可以电连接到第一单元结构100的第一重新分布层120。例如,第四连接垫CP4中的一些可以通过第二连接端子BW2电连接到第二垫PAD2。第二连接端子BW2可以是用于引线键合的连接引线。第二连接端子BW2可以连接到位于第一半导体芯片110的前表面上的第四连接垫CP4中的一些,并且可以连接到位于第三半导体芯片310的前表面上的第二垫PAD2。这里,其上设置有第三子图案SP3的第三区域R3可以与第一半导体芯片110的第二侧壁110b相邻设置,因此第二连接端子BW2的长度可以是短的。
第一连接端子BW1所连接到的第三连接垫CP3可以与第二连接端子BW2所连接到的第四连接垫CP4绝缘。第二半导体芯片210和第三半导体芯片310可以分别连接到第一重新分布层120中的彼此电绝缘的导电图案,因此半导体装置的带宽可以增大。
图5A是示出根据发明构思的一些实施例的半导体装置的剖视图。图5B是示出根据发明构思的一些实施例的半导体装置的平面图。图5A与沿着图5B的线E-E'截取的剖视图对应。在下文中,将主要描述下面的实施例与图1A和图1B的实施例之间的差异。
参照图5A和图5B,多个第二单元结构200和200'可以设置在第一单元结构100上。
第一单元结构100的第一重新分布层120可以包括第一导电图案122和第一绝缘层124。第一导电图案122还可以如参照图4A和图4B所述包括第三子图案SP3。其上设置有第三子图案SP3的第三区域R3可以位于第一区域R1的在第一方向D1上的一侧处。第二子图案SP2的被第一绝缘层124暴露的部分可以是第三连接垫CP3,第三子图案SP3的被第一绝缘层124暴露的部分可以是第四连接垫CP4。在一些实施例中,第三区域R3可以如图5B中所示与第一区域R1的一侧相邻。
如上所述,多个第二单元结构200和200'可以设置在第一单元结构100上。第二单元结构200和200'中的每个的组件和布置可以与参照图1A和图1B描述的组件和布置相同或相似。然而,第二单元结构200和200'的尺寸(例如,在第一方向D1上的长度)可以小于第一单元结构100的尺寸(例如,在第一方向D1上的长度)。例如,第二单元结构200和200'的宽度和长度(或第二半导体芯片210和210'的宽度和长度)可以小于第一单元结构100的宽度和长度(或第一半导体芯片110的宽度和长度)。第二单元结构200和200'中的每个可以堆叠在第一单元结构100上以在第一方向D1或第一方向D1的相反方向上倾斜,并且这些形状中的每个可以是在第一方向D1或第一方向D1的相反方向上向上倾斜的阶梯形状。详细地,一个第二单元结构200可以横向地突出超过第一半导体芯片110的第一侧壁110a,并且另一第二单元结构200'可以横向地突出超过第一半导体芯片110的第二侧壁110b。换言之,当在平面图中观看时,第二单元结构200和200'可以在彼此相反的方向上从第一单元结构100移位。第二单元结构200和200'中的每个的一部分可以与第一单元结构100叠置,并且第二单元结构200和200'中的每个的另一部分可以从第一单元结构100的一个侧壁横向地突出。第二单元结构200和200'的顶表面可以设置在同一水平处。第二单元结构200和200'的顶表面可以与模制层140的最顶端设置在同一水平处,并且可以被模制层140暴露。在一些实施例中,第二单元结构200和200'的顶表面以及模制层140的最顶端可以彼此共面。
第二单元结构200的第一垫PAD1和第二单元结构200'的第一垫PAD1'可以被第一单元结构100暴露。详细地,一个第二单元结构200的第一垫PAD1可以设置在第一半导体芯片110的第一侧壁110a的一侧处或与第一半导体芯片110的第一侧壁110a的一侧相邻,并且另一第二单元结构200'的第一垫PAD1'可以设置在第一半导体芯片110的第二侧壁110b的一侧处或与第一半导体芯片110的第二侧壁110b的一侧相邻。第二单元结构200和200'可以在第一单元结构100上彼此间隔开(例如,在第一方向D1上彼此间隔开)。
第二半导体芯片210和210'可以电连接到第一单元结构100的第一重新分布层120。例如,第二单元结构200的第一垫PAD1可以通过第一连接端子BW1电连接到第三连接垫CP3,并且第二单元结构200'的第一垫PAD1'可以通过第三连接端子BW3电连接到第四连接垫CP4。第一连接端子BW1和第三连接端子BW3可以是用于引线键合的连接引线。第一连接端子BW1可以连接到位于第一半导体芯片110的前表面上的第三连接垫CP3中的一些,第三连接端子BW3可以连接到位于第一半导体芯片110的前表面上的第四连接垫CP4中的一些。
第一连接端子BW1所连接到的第三连接垫CP3可以与第三连接端子BW3所连接到的第四连接垫CP4绝缘。第二半导体芯片210和210'可以分别连接到第一重新分布层120中的彼此电绝缘的导电图案,因此半导体装置的带宽可以增大。
在图5A和图5B中,两个第二单元结构被设置。然而,发明构思的实施例不限于此。三个或更多个第二单元结构可以被设置。图6A是示出根据发明构思的一些实施例的半导体装置的剖视图。图6B是示出根据发明构思的一些实施例的半导体装置的平面图。图6A与沿着图6B的线F-F'截取的剖视图对应。
参照图6A和图6B,第一单元结构100的第一半导体芯片110可以具有在第一方向D1上彼此背对的第一侧壁110a和第二侧壁110b,并且可以具有在第二方向D2上彼此背对的第三侧壁110c和第四侧壁110d。
第二单元结构200可以在第一单元结构100上分别横向地突出超过第一半导体芯片110的第一侧壁110a、第二侧壁110b、第三侧壁110c和第四侧壁110d。换言之,当在平面图中观看时,第二单元结构200中的每个可以在朝向第一半导体芯片110的侧壁中的每个的方向上从第一单元结构100移位。第二单元结构200中的每个的一部分可以与第一单元结构100叠置,并且第二单元结构200中的每个的另一部分可以横向地突出超过第一单元结构100的一个侧壁。
第二单元结构200的第一垫PAD1可以从第一单元结构100暴露。详细地,当在平面图中观看时,第二单元结构200中的每个的第一垫PAD1可以设置在第一半导体芯片110的侧壁110a、110b、110c和110d中的一个的一侧处或与第一半导体芯片110的侧壁110a、110b,110c和110d中的一个的一侧相邻。第二单元结构200可以在第一单元结构100上彼此间隔开。
第二半导体芯片210可以电连接到第一单元结构100的第一重新分布层120。例如,第二单元结构200的第一垫PAD1可以分别通过连接端子BW电连接到第一重新分布层120的第二连接垫CP2。连接端子BW可以是用于引线键合的连接引线。连接端子BW可以连接到位于第一半导体芯片110的前表面上的第二连接垫CP2中的一些,并且可以连接到位于第二半导体芯片210的前表面上的第一垫PAD1。
连接端子BW所分别连接到的第二连接垫CP2可以彼此绝缘。换言之,第二半导体芯片210可以分别连接到彼此电绝缘的导电图案。第二半导体芯片210可以分别连接到第一重新分布层120中的彼此电绝缘的导电图案,因此半导体装置的带宽可以增大。
图7至图11是示出根据发明构思的一些实施例的用于制造半导体装置的方法的剖视图。
参照图7,可以在载体基底400上设置第二单元结构200。可以将第二单元结构200粘附在载体基底400上。可以通过载体粘合层410将第二单元结构200粘附到载体基底400。可以使第二单元结构200在载体基底400上彼此间隔开。可以以如下这样的方式设置第二单元结构200:第二半导体芯片210的后表面(即,非有效表面)面对载体基底400,并且第二重新分布层220与载体基底400背对。换言之,在第二单元结构200中,可以将第二重新分布层220形成在第二半导体芯片210的与载体基底400背对的前表面(即,有效表面)上。
参照图8,可以在第二单元结构200上堆叠第一单元结构100。可以将第一单元结构100粘附在第二单元结构200上。可以通过第一粘合层230将第一单元结构100粘附到第二单元结构200。可以以如下这样的方式设置第一单元结构100:第一单元结构100的第一半导体芯片110的后表面(即,非有效表面)面对载体基底400,并且第一单元结构100的第一重新分布层120与载体基底400背对。换言之,在第一单元结构100中,可以在第一半导体芯片110的与载体基底400背对的前表面(即,有效表面)上形成第一重新分布层120。
第一重新分布层120的第一导电图案122可以包括电连接到第一半导体芯片110的第一子图案SP1以及与第一半导体芯片110电绝缘的第二子图案SP2。第一子图案SP1的被第一绝缘层124暴露的部分可以被定义为第一连接垫CP1,并且可以是电连接到第一半导体芯片110的垫。第二子图案SP2的被第一绝缘层124暴露的部分可以被定义为第二连接垫CP2,并且可以是与第一半导体芯片110绝缘的垫。
这里,可以将第一单元结构100设置为当在平面图中观看时在与第一方向D1相反的方向上从第二单元结构200移位。因此,可以使第二单元结构200的第二重新分布层220的第一垫PAD1暴露。
参照图9,可以通过引线键合工艺将第一单元结构100连接到第二单元结构200。例如,可以通过使用第一连接端子BW1来将第一单元结构100的第二连接垫CP2电连接到第二单元结构200的第一垫PAD1。
然后,可以将外部端子130粘附到第一单元结构100。可以在第一重新分布层120的第一连接垫CP1和一些第二连接垫CP2上设置外部端子130。
在一些实施例中,可以在引线键合工艺之前执行将外部端子130粘附到第一单元结构100的工艺。在一些实施例中,可以在第一单元结构100被堆叠在第二单元结构200上之前设置粘附有外部端子130的第一单元结构100。
参照图10,可以在载体基底400上形成模制层140。例如,可以将环氧模制化合物(EMC)材料施用到载体基底400的顶表面上,从而掩埋或覆盖第一单元结构100、第二单元结构200和第一连接端子BW1,并且可以使EMC材料硬化,从而形成模制层140。模制层140可以覆盖第二单元结构200的顶表面和侧壁以及第一单元结构100的顶表面和侧壁。可以将第一连接端子BW1掩埋在模制层140中。这里,可以使外部端子130的部分在模制层140上暴露。
然后,可以去除载体基底400和载体粘合层410。可以通过去除载体基底400和载体粘合层410来使第二半导体芯片210的后表面暴露。
参照图11,可以切割模制层140以使半导体装置彼此分离,半导体装置中的每个包括第一单元结构100和第二单元结构200。例如,可以沿着切线SL对模制层140执行单片化(singulation)工艺。换言之,因为模制层140被切开,所以可以使第一单元结构100彼此分离,可以使第二单元结构200彼此分离,从而制造半导体装置。半导体装置中的每个可以与参照图1A描述的半导体装置基本相同。
根据发明构思的实施例,引线键合工艺可以用于将堆叠的单元结构100和200电连接。换言之,针对单元结构100和200的电连接,可以不需要通过高成本的工艺所形成的组件(例如,贯穿过孔)。因此,根据发明构思的实施例的用于制造半导体装置的方法可以简化工艺并且可以降低成本。
根据发明构思的实施例,能够提供不需要用于第二半导体芯片的电连接和重新分布的附加组件而结构简单且有利于小型化的半导体装置。
此外,根据发明构思的实施例,半导体装置的带宽可以增大。根据发明构思的实施例,半导体装置的处理能力可以提高。
此外,根据发明构思的实施例,第二半导体芯片与外部端子之间的电连接可以是短的,半导体装置的电特性可以改善。
根据发明构思的实施例,可以不需要通过高成本的制造工艺所形成的组件(例如,贯穿过孔),因此制造工艺可以是简单的和廉价的,并且可以提供具有简单结构的半导体装置。
尽管已经参照示例实施例描述了发明构思,但是对本领域技术人员而言将清楚的是,在不脱离发明构思的范围的情况下,可以做出各种改变和修改。因此,应理解的是,以上实施例不是限制性的,而是说明性的。因此,发明构思的范围将通过对权利要求和它们的等同物的最宽可允许解释来确定,而不应受前述描述约束或限制。
Claims (20)
1.一种半导体装置,所述半导体装置包括:
第一半导体芯片;
第一重新分布层,位于第一半导体芯片的底表面上;
第二半导体芯片,位于第一半导体芯片上;
第二重新分布层,位于第二半导体芯片的底表面上;
模制层,在第二半导体芯片的侧壁、第一半导体芯片的侧壁和第一半导体芯片的底表面上延伸;以及
外部端子,延伸穿过模制层并且电连接到第一重新分布层,
其中,第二重新分布层包括不与第一半导体芯片叠置的暴露部分,
其中,第一重新分布层包括电连接到第一半导体芯片的第一导电图案以及与第一半导体芯片电绝缘的第二导电图案,并且
其中,第二重新分布层的暴露部分和第一重新分布层的第二导电图案通过第一连接引线彼此电连接。
2.根据权利要求1所述的半导体装置,其中,第一半导体芯片的侧壁包括第一侧壁和与第一侧壁背对的第二侧壁,并且第一半导体芯片和第二半导体芯片彼此竖直地间隔开,
其中,第二半导体芯片水平地突出超过第一半导体芯片的第一侧壁,
其中,第二导电图案与第一半导体芯片的第一侧壁相邻,并且
其中,第一导电图案与第一半导体芯片的第二侧壁相邻。
3.根据权利要求1所述的半导体装置,其中,第一连接引线掩埋在模制层中。
4.根据权利要求3所述的半导体装置,其中,从第一重新分布层的底表面到第一连接引线的最底端的第一距离比从第一重新分布层的底表面到模制层的最底端的第二距离短。
5.根据权利要求1所述的半导体装置,其中,第二半导体芯片的顶表面与模制层的最顶端共面。
6.根据权利要求1所述的半导体装置,其中,外部端子包括:
第一端子,位于第一导电图案上并且电连接到第一半导体芯片;以及
第二端子,位于第二导电图案上并且电连接到第二半导体芯片。
7.根据权利要求1所述的半导体装置,所述半导体装置还包括:
第三半导体芯片,位于第二半导体芯片上;以及
第三重新分布层,位于第三半导体芯片的底表面上,
其中,第三重新分布层包括不与第二半导体芯片叠置的暴露部分,并且
其中,第三重新分布层的暴露部分通过第二连接引线电连接到第一重新分布层。
8.根据权利要求7所述的半导体装置,其中,第一半导体芯片、第二半导体芯片和第三半导体芯片共同地限定具有阶梯形状的偏移堆叠结构。
9.根据权利要求7所述的半导体装置,其中,第一半导体芯片的侧壁包括第一侧壁和与第一侧壁背对的第二侧壁,并且第一半导体芯片、第二半导体芯片和第三半导体芯片彼此竖直地间隔开,
其中,第二半导体芯片水平地突出超过第一半导体芯片的第一侧壁,并且
其中,第三半导体芯片水平地突出超过第一半导体芯片的第二侧壁。
10.根据权利要求7所述的半导体装置,其中,第一重新分布层还包括第三导电图案,第三导电图案与第一半导体芯片电绝缘并且电连接到第二连接引线。
11.根据权利要求7所述的半导体装置,其中,第三半导体芯片的顶表面与模制层的最顶端共面。
12.根据权利要求1所述的半导体装置,其中,从第一重新分布层的底表面到模制层的底表面的距离在从第一重新分布层的底表面到外部端子的底端的距离的10%至50%的范围内。
13.根据权利要求1所述的半导体装置,所述半导体装置还包括:
粘合层,位于第一半导体芯片与第二半导体芯片之间。
14.一种半导体装置,所述半导体装置包括:
第一半导体芯片,包括第一有效表面和与第一有效表面背对的第一非有效表面;
第一垫,位于第一有效表面上;
第二半导体芯片,位于第一半导体芯片上,其中,第二半导体芯片包括面对第一半导体芯片的第一非有效表面的第二有效表面,并且其中,第二半导体芯片与第一半导体芯片竖直地间隔开并且横向地突出超过第一半导体芯片的第一侧面,并且第一半导体芯片暴露第二半导体芯片的第二有效表面的暴露部分;
第二垫,位于第二半导体芯片的第二有效表面的暴露部分上;
外部端子,位于第一半导体芯片的第一有效表面上;以及
模制层,从第一半导体芯片的侧壁和第二半导体芯片的侧壁延伸到第一半导体芯片的第一有效表面上,
其中,模制层至少部分地覆盖外部端子的侧面,并且
其中,第一垫和第二垫通过第一连接引线彼此电连接。
15.根据权利要求14所述的半导体装置,其中,第一垫包括:
第一连接垫,电连接到第一半导体芯片;以及
第二连接垫,电连接到第一连接引线,
其中,第二连接垫与第一半导体芯片电绝缘。
16.根据权利要求15所述的半导体装置,其中,第一半导体芯片还包括与第一半导体芯片的第一侧面背对的第二侧面,
其中,第一半导体芯片的第一有效表面包括与第一半导体芯片的第二侧面相邻的第一区域以及与第一半导体芯片的第一侧面相邻的第二区域,
其中,第一连接垫位于第一区域上,并且
其中,第二连接垫位于第二区域上。
17.根据权利要求14所述的半导体装置,其中,第二半导体芯片包括多个第二半导体芯片,并且
其中,所述多个第二半导体芯片在第一半导体芯片的第一非有效表面上彼此间隔开。
18.根据权利要求17所述的半导体装置,其中,所述多个第二半导体芯片中的每个包括不与第一半导体芯片叠置的部分。
19.根据权利要求14所述的半导体装置,其中,第一连接引线掩埋在模制层中。
20.一种半导体装置,所述半导体装置包括:
第一半导体芯片;
第一垫,位于第一半导体芯片的底表面上;
第二半导体芯片,位于第一半导体芯片上,其中,第二半导体芯片中的每个突出超过第一半导体芯片的相应的侧面并且包括底表面,所述底表面包括被第一半导体芯片暴露的暴露部分;
第二垫,其中,第二垫中的每个位于第二半导体芯片中的相应的第二半导体芯片的底表面的暴露部分上;
第三垫,位于第一半导体芯片的底表面上,其中,第三垫与第一垫间隔开;
连接端子,连接端子中的每个将第一垫中的一个电连接到第二垫中的一个;
外部端子,位于第一半导体芯片的底表面上;以及
模制层,覆盖第一半导体芯片的底表面和第二半导体芯片的底表面,
其中,外部端子中的每个电连接到第一垫和第三垫中的相应的垫,
其中,模制层与外部端子的侧面接触,
其中,从第一半导体芯片的底表面到模制层的底表面的距离在从第一半导体芯片的底表面到外部端子中的一个的底端的距离的10%至50%的范围内,并且
其中,第二半导体芯片中的最上面的第二半导体芯片的顶表面与模制层的最顶端共面。
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US11257793B2 (en) | 2022-02-22 |
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TWI784285B (zh) | 2022-11-21 |
US11830853B2 (en) | 2023-11-28 |
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US20220149013A1 (en) | 2022-05-12 |
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