CN112104368A - Feedback signal high-speed sampling holding circuit driven by PWM (pulse-Width modulation) wave to load - Google Patents

Abstract

A high-speed sampling and holding circuit of a feedback signal driven by a PWM wave load belongs to the technical field of signal sampling circuits. The invention includes a control time sequence module and an integral sampler, the control time sequence module synchronizes the PWM signal and outputs it cyclically, and the control time sequence module integrates, maintains and clears the feedback signal within a period of three or more PWM signals by controlling the integral sampler. The average value of the feedback signal is obtained, and the integral sampler is controlled to provide at least one PWM signal period for A/D sampling and at least one PWM signal period for regulating the output. The invention is based on the combined design of the basic digital logic circuit and the analog circuit, and can achieve at least three PWM signal cycles, use one PWM signal cycle to obtain an accurate feedback signal average value, and at the same time provide the system with at least one PWM signal cycle time. After A/D sampling, at least one PWM signal cycle time is used to condition the output.

Description

A high-speed sample-and-hold circuit for feedback signal driven by PWM wave

technical field

The invention belongs to the technical field of signal sampling circuits, in particular to a high-speed sampling and holding circuit of feedback signals driven by PWM waves.

Background technique

There are many objects that use PWM waves as driving signals, such as motor control, DC/AC conversion, DC/DC conversion, and piezoelectric drive. In order to carry out closed-loop control of the controlled object, it is necessary to detect the working current or voltage feedback signal of the controlled object in real time. Most of the actual feedback signals of the working object are based on the fundamental wave of the driving signal PWM, and a large number of high-order harmonics are superimposed. a complex combination of signals. Two methods are usually used to detect the feedback signal of the working object: one is precise rectification and filtering; the other is the high-speed A/D sampling of the microprocessor to obtain the average value of the feedback signal in one or more cycles.

The precision rectification and filtering method is used to process the feedback signal of the object with the PWM wave as the driving signal. The characteristic is that the output is a DC signal. The disadvantage is very obvious, that is, to obtain a stable DC signal, a relatively long filtering lag time is required. In case of reaction, this scheme cannot be used. Microprocessor high-speed A/D sampling performs object feedback signal processing. In the case of providing a sufficiently high sampling speed, the average value of the feedback signal can be obtained in one or more PWM signal cycles, but when the PWM frequency is relatively high and When the high-frequency components of the feedback signal of the controlled object are more complex, the high-speed A/D sampling speed and processing speed of the microprocessor are also high, so that the high-cost solutions of DSP, FPGA and high-speed independent A/D are required to be used. Solve the problem.

Therefore, it is necessary to propose a new solution to solve this problem.

SUMMARY OF THE INVENTION

The present invention mainly solves the technical problems existing in the above-mentioned prior art, and provides a high-speed sampling and holding circuit of a feedback signal driven by a PWM wave.

The above-mentioned technical problems of the present invention are mainly solved by the following technical solutions: a high-speed sampling and holding circuit of feedback signals driven by a PWM wave load, comprising a control sequence module and an integral sampler, the control sequence module and the integral sampler Connected to each other, the control timing module synchronizes the PWM signal and outputs it cyclically, and the control timing module integrates, maintains and clears the feedback signal by controlling the integral sampler within a period greater than or equal to 3 PWM signals, thereby obtaining the feedback signal. The average value, the control timing module controls the integral sampler to provide at least one PWM signal cycle time for feedback signal integration, at least one PWM signal cycle time to hold the sampling result, and at least one PWM signal cycle time for A/D sampling, at least one PWM signal cycle time. Time is used to clear the integral sampler and adjust the output.

Preferably, when the integrating sampler enters the hold state, the control timing module synchronously triggers A/D sampling; when the integrating sampler enters the clearing state, the control timing module adjusts the calculation and updates the control output.

Preferably, the control timing module includes a decimal counter and a dual four-input terminal OR gate chip, the decimal counter feeds back one of the output terminals to the reset terminal to form a ternary counter, and the remaining output terminals of the decimal counter are used for cyclic output, And it is connected with the corresponding input terminal of the dual four-input terminal or gate chip.

Preferably, the integrating sampler includes a sampling circuit and a rectifying circuit, the sampling circuits are respectively connected with the rectifying circuit and the control timing module, and the sampling circuit integrates, maintains and clears the output signal of the rectifying circuit.

Preferably, the rectifier circuit includes an operational amplifier U1A, an operational amplifier U1B, and peripheral devices, the peripheral devices include a resistor R1, a resistor R2 and a diode D1, the non-inverting input end of the operational amplifier U1A is grounded, and the operational amplifier The inverting input terminal of U1A is respectively connected to one end of the resistor R1 and one end of the resistor R2, the other end of the resistor R1 is used as the signal input terminal VIN of the integrating sampler, and the non-inverting input terminal of the operational amplifier U1B is respectively connected to the one end of the resistor R2. The other end and the anode of the diode D1, the cathode of the diode D1 is connected to the output terminal of the operational amplifier U1A, the output terminal of the operational amplifier U1B is respectively connected to its reverse input terminal and the sampling circuit, and its common connection terminal is used as the output of the rectifier circuit Output of signal V1.

Preferably, the sampling circuit includes a resistor R3, a resistor R4, a resistor R5, a capacitor C1, a MOS transistor T1, a MOS transistor T2, a MOS transistor T3, a MOS transistor T4, and an operational amplifier U2A, and one end of the resistor R3 is connected to the rectifier circuit , the other end of the resistor R3 is respectively connected to one end of the resistor R4 and the drain of the MOS transistor T1, and its common connection end is used as the output end of the output signal V2 of the rectifier circuit, and the source of the MOS transistor T1 is connected to the MOS transistor T2. The source, the drain of the MOS transistor T2 is grounded, the gate of the MOS transistor T1 is connected to the gate of the MOS transistor T2, and its common connection terminal is connected to the control timing module, and the non-inverting input terminal of the operational amplifier U2A is grounded , the reverse input end of the operational amplifier U2A is respectively connected to the other end of the resistor R4, one end of the capacitor C1 and the drain of the MOS transistor T3, the output end of the operational amplifier U2A is respectively connected to the other end of the capacitor C1 and the other end of the resistor R5 One end, and its common connection end is used as the signal output end VOUT of the integral sampler, the other end of the resistor R5 is connected to the drain of the MOS transistor T4, the source of the MOS transistor T4 is connected to the source of the MOS transistor T3, the The gate of the MOS transistor T4 is connected to the gate of the MOS transistor T3, and its common connection terminal is connected to the control timing module.

The beneficial effects that the present invention has:

1. In the present invention, the control sequence module is divided into three stages: integration, holding and clearing. The time of these three stages can be set to an integer multiple of the PWM signal cycle, and the control sequence module can be performed in multiple PWM signal cycles. Setting, the control timing module can be set to at least three PWM signal cycles;

2. The present invention is based on the combined design of basic digital logic circuit and analog circuit, which can achieve at least three PWM signal cycles, use one PWM signal cycle to obtain an accurate feedback signal average value, and provide the system with at least one PWM signal cycle. time for A/D adoption, time for at least one PWM signal cycle to regulate the output;

3. Under the control of the control sequence module, the integrating sampler can first integrate the feedback signal in three or more PWM signal cycles and obtain the average value of the feedback signal, and then enter the hold state, which is the A/D conversion of the controller. The controller provides a stable sampling signal and a long enough sampling and holding time, and finally enters the clearing state to prepare for the zero starting point for the next integral link.

Description of drawings

Fig. 1 is a kind of circuit diagram of the present invention;

2 is a schematic diagram of the main logic control point waveform and the main waveform point waveform of the integral sampler in Embodiment 1 of the present invention;

3 is a circuit diagram of a control sequence module in Embodiment 2 of the present invention;

FIG. 4 is a timing chart of the main output of the control logic circuit in Embodiment 2 of the present invention.

In the figure: 1. Control timing module; 2. Integral sampler.

Detailed ways

The technical solutions of the present invention will be further described in detail below through embodiments and in conjunction with the accompanying drawings.

Embodiment 1: A high-speed sample-and-hold circuit for feedback signals driven by a PWM wave load, comprising a control sequence module 1 and an integral sampler 2, the control sequence module 1 and the integral sampler 2 are connected, and the control sequence module 1 is synchronized The PWM signal is output in a loop, and the control timing module 1 integrates, maintains, and clears the feedback signal by controlling the integral sampler 2 in a period greater than or equal to 3 PWM signals, so as to obtain the average value of the feedback signal, and the control The timing module 1 controls the integral sampler 2 to provide at least one PWM signal cycle time for feedback signal integration, at least one PWM signal cycle time to hold the sampling result and for A/D sampling, and at least one PWM signal cycle time for integration Sampler clears and regulates output.

As shown in FIG. 1 , the control timing module 1 includes a decimal counter and a dual-quad input terminal OR gate chip. The model of the decimal counter is CD4017, the type of the dual-quad input terminal OR gate chip is CD4072, and the decimal The output terminals of the counter are Q0-Q9, the output terminal Q3 of the decimal counter is fed back to the reset terminal RESET through the diode D2 to form a ternary counter, and the output terminal Q0, the output terminal Q1 and the output terminal Q2 of the decimal counter are used for cyclic output. , to complete the control sequence of three PWM signal cycles, namely: integration of one PWM signal cycle, maintenance of one PWM signal cycle, and clearing of one PWM signal cycle. The dual four-input terminal OR gate chip includes a chip U4A and a chip U4B, the second pin of the chip U4A is connected to the output end Q2 of the decimal counter, and the third pin, the fourth pin and the fifth pin of the chip U4A are connected to the second pin. pin, the output end of the chip U4A is used as the output end CTL1_1 of the control timing module 1, the ninth pin of the chip U4B is connected to the output end Q1 of the decimal counter, and the tenth pin of the chip U4B is connected to the output end Q2 of the decimal counter, so The eleventh pin and the twelfth pin of the chip U4B are both connected to the tenth pin, and the output end of the chip U4B is used as the output end CTL2_1 of the control timing module 1 .

The timing design is: Q0 corresponds to the integration stage, Q1 corresponds to the hold stage, and Q2 corresponds to the clear stage. Use the NOR signal of Q0 and Q1 to control the integral sampler 2 to clear, and use the or signal of Q1 and Q2 to cooperate with the NOR signal of Q0 and Q1 to complete integration, holding and clearing.

The integrating sampler 2 includes a sampling circuit and a rectifying circuit, the sampling circuits are respectively connected with the rectifying circuit and the control timing module 1, and the sampling circuit integrates, maintains and clears the output signal of the rectifying circuit.

The rectifier circuit includes an operational amplifier U1A, an operational amplifier U1B, and peripheral devices. The peripheral devices include a resistor R1, a resistor R2, and a diode D1. Connect one end of the resistor R1 and one end of the resistor R2 to the input terminals, respectively, and the other end of the resistor R1 is used as the signal input terminal VIN of the integral sampler 2 for connection with the feedback signal. The same-direction input terminal of the operational amplifier U1B The other end of the resistor R2 and the anode of the diode D1 are respectively connected, the cathode of the diode D1 is connected to the output end of the operational amplifier U1A, and the output end of the operational amplifier U1B is respectively connected to its reverse input end and one end of the resistor R3 in the sampling circuit , and its common connection terminal is used as the output terminal of the output signal V1 of the rectifier circuit.

The sampling circuit includes a resistor R3, a resistor R4, a resistor R5, a capacitor C1, a MOS transistor T1, a MOS transistor T2, a MOS transistor T3, a MOS transistor T4, and an operational amplifier U2A. One end of the resistor R3 is connected to the output of the operational amplifier U1B. The other end of the resistor R3 is respectively connected to one end of the resistor R4 and the drain of the MOS transistor T1, and its common connection end is used as the output end of the output signal V2 of the rectifier circuit, and the source of the MOS transistor T1 is connected to the MOS transistor T2. The source of the MOS transistor T2 is grounded, the gate of the MOS transistor T1 is connected to the gate of the MOS transistor T2, and its common connection terminal is connected to the output terminal CTL2_1 of the control timing module 1, and the operational amplifier U2A The non-inverting input terminal of the operational amplifier U2A is grounded, the reverse input terminal of the operational amplifier U2A is respectively connected to the other end of the resistor R4, one end of the capacitor C1 and the drain of the MOS transistor T3, and the output terminal of the operational amplifier U2A is respectively connected to the capacitor C1. The other end and one end of the resistor R5, and its common connection end is used as the signal output end VOUT of the integral sampler 2, the other end of the resistor R5 is connected to the drain of the MOS transistor T4, and the source of the MOS transistor T4 is connected to the MOS transistor The source of T3, the gate of the MOS transistor T4 is connected to the gate of the MOS transistor T3, and its common connection terminal is connected to the output terminal CTL1_1 of the control timing module 1 .

The rectifying circuit rectifies the AC signal and transmits it to the sampling circuit. Corresponding to the effective stage of Q0, both the output terminal CTL1_1 and the output terminal CTL2_1 output a low level, the MOS transistor T1, MOS transistor T2, MOS transistor T3 and MOS transistor T4 are turned off, and the integral sampler 2 integrates the output signal V1 of the rectifier circuit; Corresponding to the effective stage of Q1, the output terminal CTL1_1 outputs a low level, the output terminal CTL2_1 outputs a high level, and the MOS transistor T1 and the MOS transistor T2 are connected to ground, which is equivalent to zero potential of the output signal V2 of the rectifier circuit. At this time, the integral sampler 2 Because the input signal is zero, it enters the hold state, which lasts for a period of the PWM signal. At the same time, the control sequence module 1 uses the rising edge of Q2 to synchronously trigger A/D sampling; corresponding to the effective stage of Q2, the output terminal CTL1_1 Both the output terminal CTL2_1 and the output terminal CTL2_1 output a high level, the MOS tube T1, MOS tube T2, MOS tube T3 and MOS tube T4 are turned on, the output signal V2 of the rectifier circuit has zero potential, and the integrating capacitor C1 is discharged, and the integral sampler 2 Enter the clear state. For the control sequence module 1, after A/D sampling, there is one PWM signal cycle time for adjusting the calculation and updating the control output until the end of clearing.

In Figure 1, the working voltage of the decimal counter, dual four-input terminal OR gate chip, operational amplifier U1A and operational amplifier U2A is taken as an example of ±5V, which can be adjusted according to the actual working conditions. The logic circuit is mainly CMOS logic chip , and can be adjusted according to the actual working conditions during use. The operational amplifier U1A, the operational amplifier U1B and the operational amplifier U2A take the OPA2227 as an example, and can be adjusted according to the actual working conditions during use. FIG. 2 is a schematic diagram of the main logic control point waveform and the main waveform point waveform of the integral sampler 2 in this embodiment. In Fig. 2, the PWM signal is taken as an example of a 50% duty cycle state, and the feedback signal VIN is taken as an example of a triangular wave.

Embodiment 2: A high-speed sample-and-hold circuit for feedback signals driven by a PWM wave, the difference from Embodiment 1 is only that the decimal counter completes an integration with 2 PWM signal periods, a hold with 2 PWM signal periods, A clear with 2 PWM signal periods.

For some applications, the average error of sampling only one cycle may be large due to the high noise of the feedback signal, and it is necessary to sample a pair of cycles to obtain an average value with higher precision; The sample and hold time of one cycle; some applications may have a large delay in the system output response, and it is necessary to reserve several cycles of system stability response time after adjusting the output. In this case, the logic sequence in Embodiment 1 can be simply modified to obtain the integration time of multiple PWM signal cycles, the sampling hold time of multiple PWM signal cycles, and the clearing time of multiple PWM signal cycles.

As shown in FIG. 3 , it is a control logic circuit with an integration time of 2 PWM signal cycles, a hold time of 2 PWM signal cycles, and a clearing time of 2 PWM signal cycles. When CD4017 is used as a counter, the integration time, sampling time and clearing time can be assigned in any combination within 3-10 PWM signal cycles. If the counter is expanded, it can be combined and assigned within more PWM signal cycles.

When in use, the output terminal Q6 of the decimal counter is fed back to the reset terminal RESET through the diode D2 to form a ternary counter, and the output terminal Q0, output terminal Q1, output terminal Q2, output terminal Q3, output terminal Q4 and The output terminal Q5 is used for cyclic output. The dual four-input terminal OR gate chip includes a chip U4A and a chip U4B. The second pin of the chip U4A is connected to the output terminal Q4 of the decimal counter, and the third pin of the chip U4A is connected to the output terminal Q5 of the decimal counter. , the fourth and fifth pins of the chip U4A are connected to the third pin, the output end of the chip U4A is used as the output end CTL1_1 of the control timing module 1, the ninth pin of the chip U4B is connected to the output end Q2 of the decimal counter, and the first end of the chip U4B is connected to the output end Q2 of the decimal counter. The tenth pin is connected to the output terminal Q3 of the decimal counter, the eleventh pin of the chip U4B is connected to the output terminal Q4 of the decimal counter, the twelfth pin of the chip U4B is connected to the output terminal Q5 of the decimal counter, and the output terminal of the chip U4B is used as the control timing module 1 The output of CTL2_1. The timing sequence is designed as follows: Q0 and Q1 correspond to the integration stage, Q2 and Q3 correspond to the hold stage, and Q4 and Q5 correspond to the clearing stage.

As shown in FIG. 4 , the main output timing diagram of the control logic circuit of this embodiment is shown. Corresponding to the continuous valid stage of Q0 and Q1, the output terminal CTL1_1 and the output terminal CTL2_1 both output low level, the MOS transistor T1, MOS transistor T2, MOS transistor T3 and MOS transistor T4 are turned off, and the integral sampler 2 outputs the signal V1 to the rectifier circuit. Integrate; corresponding to the continuous effective stage of Q2 and Q3, the output terminal CTL1_1 outputs a low level, the output terminal CTL2_1 outputs a high level, and the MOS transistor T1 and the MOS transistor T2 are connected to the ground, which is equivalent to the output signal V2 of the rectifier circuit. The potential of the point is zero , at this time, the integral sampler 2 enters the hold state because the input signal is zero; corresponding to the continuous effective stage of Q4 and Q5, the output terminal CTL1_1 and the output terminal CTL2_1 both output high level, MOS transistor T1, MOS transistor T2, MOS transistor T3 and The MOS tube T4 is turned on, the potential of the output signal V2 of the rectifier circuit is zero, and the integrating capacitor C1 is discharged at the same time, and the integrating sampler 2 enters the zero-clearing state.

To sum up, in the present invention, the control sequence module is divided into three stages: integration, holding and clearing. The time of these three stages can be set to an integer multiple of the PWM signal period, and the control sequence module can be used in multiple PWM signals. The control timing module can be set to at least three PWM signal cycles; the invention is based on the combined design of basic digital logic circuits and analog circuits, and can achieve at least three PWM signal cycles with one PWM signal cycle to obtain Accurate feedback signal average value, and at the same time provide the system with at least one PWM signal cycle time for A/D adoption, and at least one PWM signal cycle time for adjusting the output; under the control of the control sequence module, the integral sampler can firstly Integrate the feedback signal in more than or equal to 3 PWM signal cycles and obtain the average value of the feedback signal, and then enter the hold state to provide a stable sampling signal and a long enough sampling and holding time for the A/D converter of the controller, and finally Enter the clearing state, and prepare for the zero starting point for the next integral link.

Finally, it should be pointed out that the above embodiments are only representative examples of the present invention. Obviously, the present invention is not limited to the above-mentioned embodiments, and many modifications are possible. Any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention shall be considered to belong to the protection scope of the present invention.

Claims (6)

1. a feedback signal high-speed sample-and-hold circuit by PWM wave drive load, is characterized in that, comprises control sequence module and integral sampler, described control sequence module is connected with integral sampler, and described control sequence module synchronizes PWM signal and Loop output, the control timing module integrates, maintains, and clears the feedback signal within a period greater than or equal to 3 PWM signals by controlling the integral sampler, thereby obtaining the average value of the feedback signal, and the control timing module controls the integral sampling The device provides at least one PWM signal cycle time for feedback signal integration, at least one PWM signal cycle time to hold sampling results and for A/D sampling, at least one PWM signal cycle time for integrating the sampler to clear and adjust the output . 2. a kind of feedback signal high-speed sampling and holding circuit driven by PWM wave load according to claim 1, is characterized in that, when described integral sampler enters hold state, described control sequence module synchronously triggers to carry out A/D sampling; When the integral sampler enters the clearing state, the control timing module adjusts the calculation and updates the control output. 3. a kind of feedback signal high-speed sample-and-hold circuit driven by PWM wave load according to claim 1, is characterized in that, described control sequence module comprises decimal counter and dual four-input terminal or gate chip, described decimal counter will be wherein One output terminal is fed back to the reset terminal to form a ternary counter, and the remaining output terminals of the decimal counter are used for cyclic output and are connected to the corresponding input terminals of the dual-quad input terminal or gate chip. 4. a kind of feedback signal high-speed sampling and holding circuit driven by PWM wave load according to claim 1, is characterized in that, described integral sampler comprises sampling circuit and rectifying circuit, and described sampling circuit is respectively with rectifying circuit and control sequence The modules are connected, and the sampling circuit integrates, maintains and clears the output signal of the rectifier circuit. 5. a kind of feedback signal high-speed sample-and-hold circuit driven by PWM wave load according to claim 4, is characterized in that, described rectifier circuit comprises operational amplifier U1A, operational amplifier U1B and peripheral device, and described peripheral device comprises resistance R1, resistor R2 and diode D1, the non-inverting input terminal of the operational amplifier U1A is grounded, and the inverting input terminal of the operational amplifier U1A is respectively connected to one end of the resistor R1 and one end of the resistor R2, and the other end of the resistor R1 is used as The signal input terminal VIN of the integral sampler, the non-inverting input terminal of the operational amplifier U1B is respectively connected to the other end of the resistor R2 and the anode of the diode D1, the cathode of the diode D1 is connected to the output terminal of the operational amplifier U1A, the operational amplifier The output end of U1B is respectively connected to its reverse input end and the sampling circuit, and its common connection end is used as the output end of the output signal V1 of the rectifier circuit. 6. The high-speed sampling and holding circuit of a feedback signal driven by a PWM wave according to claim 4, wherein the sampling circuit comprises a resistor R3, a resistor R4, a resistor R5, a capacitor C1, a MOS tube T1, a MOS tube T2, MOS transistor T3, MOS transistor T4, and operational amplifier U2A, one end of the resistor R3 is connected to the rectifier circuit, and the other end of the resistor R3 is respectively connected to one end of the resistor R4 and the drain of the MOS transistor T1, and they are connected in common The terminal is used as the output terminal of the output signal V2 of the rectifier circuit, the source of the MOS transistor T1 is connected to the source of the MOS transistor T2, the drain of the MOS transistor T2 is grounded, and the gate of the MOS transistor T1 is connected to the gate of the MOS transistor T2. The gate, and its common connection terminal is connected to the control timing module, the non-inverting input terminal of the operational amplifier U2A is grounded, and the reverse input terminal of the operational amplifier U2A is respectively connected to the other end of the resistor R4, one end of the capacitor C1 and the MOS tube The drain of T3, the output end of the operational amplifier U2A is connected to the other end of the capacitor C1 and one end of the resistor R5 respectively, and its common connection end is used as the signal output end VOUT of the integral sampler, and the other end of the resistor R5 is connected to the MOS The drain of the transistor T4, the source of the MOS transistor T4 is connected to the source of the MOS transistor T3, the gate of the MOS transistor T4 is connected to the gate of the MOS transistor T3, and the common connection terminal is connected to the timing control module.

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