CN112104368A

CN112104368A - Feedback signal high-speed sampling holding circuit driven by PWM (pulse-Width modulation) wave to load

Info

Publication number: CN112104368A
Application number: CN202010975358.1A
Authority: CN
Inventors: 梁伟
Original assignee: University of Shaoxing
Current assignee: University of Shaoxing
Priority date: 2020-09-16
Filing date: 2020-09-16
Publication date: 2020-12-18
Anticipated expiration: 2040-09-16
Also published as: CN112104368B

Abstract

A feedback signal high-speed sampling holding circuit driven by PWM wave belongs to the technical field of signal sampling circuits. The invention comprises a control time sequence module and an integral sampler, wherein the control time sequence module synchronizes PWM signals and circularly outputs the PWM signals, the control time sequence module integrates, keeps and clears feedback signals in a period which is more than or equal to 3 PWM signals by controlling the integral sampler to obtain an average value of the feedback signals, the control integral sampler provides time of at least one PWM signal period for A/D sampling, and the time of at least one PWM signal period is used for adjusting output. The invention is based on the combined design of a basic digital logic circuit and an analog circuit, can obtain an accurate feedback signal average value by using one PWM signal period in at least three PWM signal periods, and simultaneously provides the system with the time of at least one PWM signal period for A/D sampling and the time of at least one PWM signal period for regulating output.

Description

Feedback signal high-speed sampling holding circuit driven by PWM (pulse-Width modulation) wave to load

Technical Field

The invention belongs to the technical field of signal sampling circuits, and particularly relates to a feedback signal high-speed sampling and holding circuit driven by PWM (pulse-width modulation) waves.

Background

Many objects of the driving signal are PWM waves, and for example, the driving signal is used in motor control, DC/AC conversion, DC/DC conversion, piezoelectric driving, and the like. In order to perform closed-loop control on a controlled object, a working current or voltage feedback signal of the controlled object needs to be detected in real time, and the actual feedback signal of the controlled object is mostly a complex combined signal which is based on the fundamental wave of the driving signal PWM and is superposed with a large amount of higher harmonics. Two methods are commonly used for detection of the work object feedback signal: firstly, precise rectification and filtering; secondly, the microprocessor performs high-speed A/D sampling to obtain the average value of the feedback signal in one or more periods.

The method is characterized in that a direct current signal is output, the defect is obvious, a long filtering lag time is needed for obtaining a stable direct current signal, and the scheme cannot be used in occasions requiring high-speed response of an object. The microprocessor high-speed A/D sampling is used for object feedback signal processing, under the condition that a sufficiently high sampling speed can be provided, the average value of a feedback signal can be obtained in one or more PWM signal periods, but when the frequency of PWM is high and the high-frequency component of the feedback signal of the controlled object is complex, the requirements on the speed and the processing speed of the microprocessor high-speed A/D sampling are high, so that the problems can be solved by adopting a high-cost scheme of a DSP, an FPGA and a high-speed independent A/D.

Therefore, a new solution is needed to solve this problem.

Disclosure of Invention

The present invention mainly solves the technical problems of the prior art, and provides a feedback signal high-speed sample-and-hold circuit driven by a PWM wave.

The technical problem of the invention is mainly solved by the following technical scheme: a feedback signal high-speed sampling holding circuit driven by PWM waves comprises a control time sequence module and an integral sampler, wherein the control time sequence module is connected with the integral sampler, the control time sequence module synchronizes PWM signals and outputs the PWM signals in a circulating mode, the control time sequence module integrates, holds and clears the feedback signals in a period which is more than or equal to 3 PWM signals by controlling the integral sampler so as to obtain an average value of the feedback signals, and the control time sequence module controls the integral sampler to provide time of at least one PWM signal period for feedback signal integration, time holding sampling results of at least one PWM signal period and time for A/D sampling and at least one PWM signal period for clearing and adjusting output of the integral sampler.

Preferably, when the integral sampler enters a holding state, the control timing module synchronously triggers to perform A/D sampling; and when the integral sampler enters a zero clearing state, the control time sequence module adjusts calculation and updates control output.

Preferably, the control time sequence module comprises a decimal counter and a double four-input end or gate chip, one output end of the decimal counter is fed back to the reset end to form a ternary counter, and the rest output ends of the decimal counter are circularly output and are connected with the corresponding input ends of the double four-input end or gate chip.

Preferably, the integral sampler comprises a sampling circuit and a rectifying circuit, the sampling circuit is respectively connected with the rectifying circuit and the control timing module, and the sampling circuit integrates, holds and clears the output signal of the rectifying circuit.

Preferably, the rectifier circuit comprises an operational amplifier U1A, an operational amplifier U1B and peripheral devices, the peripheral devices comprise a resistor R1, a resistor R2 and a diode D1, the same-direction input end of the operational amplifier U1A is grounded, the reverse-direction input end of the operational amplifier U1A is respectively connected with one end of a resistor R1 and one end of a resistor R2, the other end of the resistor R1 is used as a signal input end VIN of an integral sampler, the same-direction input end of the operational amplifier U1B is respectively connected with the other end of a resistor R2 and the anode of a diode D1, the cathode of the diode D6337 is connected with the output end of the operational amplifier U1A, the output end of the operational amplifier U1B is respectively connected with the reverse-direction input end and a sampling circuit, and the common connection end thereof is used as the output end of the rectifier circuit output.

Preferably, the sampling circuit includes a resistor R3, a resistor R4, a resistor R5, a capacitor C1, a MOS transistor T1, a MOS transistor T2, a MOS transistor T3, a MOS transistor T4, and an operational amplifier U2A, one end of the resistor R3 is connected to the rectifying circuit, the other end of the resistor R3 is connected to one end of a resistor R4 and the drain of the MOS transistor T1, respectively, and a common connection end thereof is used as an output end of a rectifying circuit output signal V2, a source of the MOS transistor T1 is connected to the source of the MOS transistor T2, a drain of the MOS transistor T2 is grounded, a gate of the MOS transistor T1 is connected to the gate of the MOS transistor T2, and a common connection thereof is connected to the control timing module, a common-direction input end of the operational amplifier U2 2 is grounded, reverse-direction input ends of the operational amplifier U2 2 are connected to the other end of the resistor R2, one end of the capacitor C2 and the drain of the MOS transistor T2, respectively, and the common connection end of the resistor is used as a signal output end VOUT of the integral sampler, the other end of the resistor R5 is connected with the drain electrode of the MOS tube T4, the source electrode of the MOS tube T4 is connected with the source electrode of the MOS tube T3, the grid electrode of the MOS tube T4 is connected with the grid electrode of the MOS tube T3, and the common connection end of the resistor R4 is connected with the control timing module.

The invention has the following beneficial effects:

1. in the invention, the control time sequence module is divided into three stages of integration, holding and zero clearing, the time of the three stages can be set to be integral multiple of the PWM signal period, the control time sequence module can be set in a plurality of PWM signal periods, and the control time sequence module can be set to be three PWM signal periods at least;

2. the invention is based on the combined design of a basic digital logic circuit and an analog circuit, can realize that an accurate feedback signal average value is obtained by using one PWM signal period in at least three PWM signal periods, and simultaneously, the time of at least one PWM signal period is provided for A/D (analog/digital) adoption and the time of at least one PWM signal period is used for regulating output;

3. under the control of the control time sequence module, the integral sampler can firstly integrate the feedback signal in more than or equal to 3 PWM signal periods and obtain the average value of the feedback signal, then enters a holding state, provides a stable sampling signal and enough long sampling holding time for an A/D converter of the controller, and finally enters a zero clearing state to prepare for a zero starting point of the next integral link.

Drawings

FIG. 1 is a circuit diagram of the present invention;

FIG. 2 is a schematic diagram of a main control point waveform and a main point waveform of an integral sampler in accordance with embodiment 1 of the present invention;

FIG. 3 is a circuit diagram of a control timing module according to embodiment 2 of the present invention;

FIG. 4 is a timing diagram of the main outputs of the control logic circuit according to embodiment 2 of the present invention.

In the figure: 1. a control timing module; 2. an integrating sampler.

Detailed Description

The technical scheme of the invention is further specifically described by the following embodiments and the accompanying drawings.

Example 1: a feedback signal high-speed sampling holding circuit driven by PWM waves comprises a control time sequence module 1 and an integral sampler 2, wherein the control time sequence module 1 is connected with the integral sampler 2, the control time sequence module 1 synchronizes PWM signals and outputs in a circulating mode, the control time sequence module 1 integrates, holds and clears the feedback signals by controlling the integral sampler 2 in a period which is more than or equal to 3 PWM signals so as to obtain an average value of the feedback signals, and the control time sequence module 1 controls the integral sampler 2 to provide time of at least one PWM signal period for feedback signal integration, time of at least one PWM signal period for holding sampling results and time of at least one PWM signal period for A/D sampling and adjusting output.

As shown in fig. 1, the control timing module 1 includes a decimal counter and a dual four-input or gate chip, the model of the decimal counter is CD4017, the model of the dual four-input or gate chip is CD4072, the output terminals of the decimal counter are Q0-Q9, the output terminal Q3 of the decimal counter is fed back to a RESET terminal RESET through a diode D2 to form a ternary counter, the output terminals Q0, Q1 and Q2 of the decimal counter perform cyclic output, and control timings of three PWM signal periods are respectively: integration of one PWM signal period, hold of one PWM signal period, zero clearing of one PWM signal period. The double four-input end or gate chip comprises a chip U4A and a chip U4B, wherein a second pin of the chip U4A is connected with an output end Q2 of a decimal counter, a third pin, a fourth pin and a fifth pin of the chip U4A are connected with the second pin, an output end of the chip U4A is used as an output end CTL1_1 of the control timing module 1, a ninth pin of the chip U4B is connected with the output end Q1 of the decimal counter, a tenth pin of the chip U4B is connected with the output end Q2 of the decimal counter, a eleventh pin and a twelfth pin of the chip U4B are connected with the tenth pin, and an output end of the chip U4B is used as an output end CTL2_1 of the control timing module 1.

The time sequence is designed as follows: q0 corresponds to the integration phase, Q1 corresponds to the hold phase, and Q2 corresponds to the clear phase. The integration sampler 2 is controlled to zero by using the NOR signals of Q0 and Q1, and the integration, the holding and the zero clearing are completed by using the OR signals of Q1 and Q2 to match the NOR signals of Q0 and Q1.

The integral sampler 2 comprises a sampling circuit and a rectifying circuit, the sampling circuit is respectively connected with the rectifying circuit and the control time sequence module 1, and the sampling circuit integrates, keeps and clears the output signal of the rectifying circuit.

The rectifying circuit comprises an operational amplifier U1A, an operational amplifier U1B and peripheral devices, wherein the peripheral devices comprise a resistor R1, a resistor R2 and a diode D1, the equidirectional input end of the operational amplifier U1A is grounded, the reverse input end of the operational amplifier U1A is respectively connected with one end of a resistor R1 and one end of a resistor R2, the other end of the resistor R1 is used as a signal input end VIN of the integral sampler 2 and is used for being connected with a feedback signal, the equidirectional input end of the operational amplifier U1B is respectively connected with the other end of a resistor R2 and the anode of a diode D1, the cathode of the diode D1 is connected with the output end of the operational amplifier U1A, the output end of the operational amplifier U1B is respectively connected with the reverse input end thereof and one end of a resistor R3 in the sampling circuit, and the common connection end thereof is used as.

The sampling circuit comprises a resistor R3, a resistor R4, a resistor R5, a capacitor C1, a MOS tube T1, a MOS tube T2, a MOS tube T3, a MOS tube T4 and an operational amplifier U2A, wherein one end of the resistor R3 is connected with the output end of the operational amplifier U1B, the other end of the resistor R3 is respectively connected with one end of the resistor R4 and the drain of the MOS tube T4, the common connection end of the resistor R3 is used as the output end of a rectification circuit output signal V4, the source of the MOS tube T4 is connected with the source of the MOS tube T4, the drain of the MOS tube T4 is grounded, the gate of the MOS tube T4 is connected with the gate of the MOS tube T4, the common connection end of the resistor R4 is connected with the output end CTL 4 _1 of the control timing module 1, the same-direction input end of the operational amplifier U2 4 is grounded, the reverse input end of the operational amplifier U2 4 is respectively connected with the other end of the resistor R4, the drain of the capacitor C4 and the output end of the operational amplifier U4, and the common connection end of the resistor is used as a signal output end VOUT of the integral sampler 2, the other end of the resistor R5 is connected with the drain electrode of the MOS tube T4, the source electrode of the MOS tube T4 is connected with the source electrode of the MOS tube T3, the grid electrode of the MOS tube T4 is connected with the grid electrode of the MOS tube T3, and the common connection end of the resistor R4 is connected with an output end CTL1_1 of the control timing module 1.

The rectifying circuit rectifies the alternating current signal and transmits the alternating current signal to the sampling circuit. Corresponding to the effective stage of Q0, both the output end CTL1_1 and the output end CTL2_1 output low levels, the MOS tube T1, the MOS tube T2, the MOS tube T3 and the MOS tube T4 are turned off, and the integral sampler 2 integrates the output signal V1 of the rectifier circuit; corresponding to the effective stage of Q1, the output end CTL1_1 outputs low level, the output end CTL2_1 outputs high level, the MOS tube T1 and the MOS tube T2 are conducted and grounded, which is equivalent to the zero point potential of the output signal V2 of the rectifying circuit, at this time, the integral sampler 2 enters a holding state because the input signal is zero, the holding state lasts for a period of PWM signals, and meanwhile, the control timing module 1 synchronously triggers to carry out A/D sampling by using the rising edge of Q2; corresponding to the effective stage of Q2, both the output terminal CTL1_1 and the output terminal CTL2_1 output high levels, the MOS transistor T1, the MOS transistor T2, the MOS transistor T3, and the MOS transistor T4 are turned on, the potential of the output signal V2 point of the rectifier circuit is zero, the integrating capacitor C1 is discharged, and the integrating sampler 2 enters a zero clearing state. For the control timing module 1, after a/D sampling, until the end of zeroing, there is a period of time for the PWM signal to adjust the calculations and update the control output.

In fig. 1, the operating voltages of the decimal counter, the dual four-input-end or gate chip, the operational amplifier U1A, and the operational amplifier U2A are ± 5V, and can be adjusted according to the actual working condition when in use, the logic circuit is mainly a CMOS logic chip, and can be adjusted according to the actual working condition when in use, and the operational amplifier U1A, the operational amplifier U1B, and the operational amplifier U2A are OPA2227, and can be adjusted according to the actual working condition when in use. FIG. 2 is a diagram illustrating the main control point waveforms and the main point waveforms of the integral sampler 2 according to the present embodiment. In fig. 2, the PWM signal is illustrated in a 50% duty cycle state, and the feedback signal VIN is illustrated in a triangular wave.

Example 2: a feedback signal high-speed sampling hold circuit driven by PWM wave is different from the embodiment 1 only in that a decimal counter completes integration with 2 PWM signal periods, holding with 2 PWM signal periods and zero clearing with 2 PWM signal periods.

For some applications, it may be that because the feedback signal is noisy, the error of the average value sampled for only one period is large, and it is necessary to sample for every period to obtain an average value with high accuracy; some applications may have slow system sampling speed, requiring multiple cycles of sample and hold time; some applications may have a large lag in system output response, requiring a system settling response time of several cycles to be reserved after the output is adjusted. In this case, the logic timing in embodiment 1 can be simply modified to obtain the integration time of a plurality of PWM signal periods, the sample-and-hold time of a plurality of PWM signal periods, and the clear time of a plurality of PWM signal periods.

As shown in fig. 3, the control logic circuit has an integration time of 2 PWM signal periods, a hold time of 2 PWM signal periods, and a clear time of 2 PWM signal periods. When the CD4017 is used as a counter, the integration time, the sampling time and the zero clearing time can be randomly combined and distributed in 3-10 PWM signal periods, and if the counter is expanded, the integration time, the sampling time and the zero clearing time can be combined and distributed in more PWM signal periods.

When in use, the output end Q6 of the decimal counter is fed back to the RESET end RESET through a diode D2 to form a ternary counter, the output end Q0, the output end Q1, the output end Q2, the output end Q3, the output end Q4 and the output end Q5 of the decimal counter are circularly output, the double four-input end or gate chip comprises a chip U4A and a chip U4B, the second pin of the chip U4A is connected with the output end Q4 of the decimal counter, the third pin of the chip U4A is connected with the output end Q5 of the decimal counter, the fourth pin and the fifth pin of the chip U4A are both connected with the third pin, the output end of the chip U4A is used as the output end CTL 9 _1 of the control timing module 1, the ninth pin of the chip U4B is connected with the output end Q2 of the decimal counter, the tenth pin of the chip U4B is connected with the output end Q3 of the decimal counter, the eleventh pin 68628 of the chip U B is connected with the output end Q4 of the decimal counter, and the twelfth pin 5 of the chip U5, the output terminal of the chip U4B serves as the output terminal CTL2_1 of the control timing module 1. The time sequence is designed as follows: q0 and Q1 correspond to the integration phase, Q2 and Q3 correspond to the hold phase, and Q4 and Q5 correspond to the clear phase.

Fig. 4 shows a main output timing diagram of the control logic circuit of the present embodiment. Corresponding to the continuous effective stages of Q0 and Q1, both the output end CTL1_1 and the output end CTL2_1 output low levels, the MOS tube T1, the MOS tube T2, the MOS tube T3 and the MOS tube T4 are turned off, and the integral sampler 2 integrates the output signal V1 of the rectifier circuit; corresponding to the continuous effective stages of Q2 and Q3, the output end CTL1_1 outputs low level, the output end CTL2_1 outputs high level, the MOS tube T1 and the MOS tube T2 are conducted and grounded, namely the potential of an output signal V2 point of the rectifying circuit is zero, at the moment, the integral sampler 2 enters a holding state because the input signal is zero; corresponding to the continuous effective stages of Q4 and Q5, the output end CTL1_1 and the output end CTL2_1 both output high levels, the MOS tube T1, the MOS tube T2, the MOS tube T3 and the MOS tube T4 are conducted, the potential of the output signal V2 point of the rectifying circuit is zero, meanwhile, the integrating capacitor C1 is discharged, and the integrating sampler 2 enters a zero clearing state.

In summary, in the present invention, the control timing module is divided into three stages, i.e., integration, hold, and zero clearing, the time of the three stages can be set to be an integral multiple of the PWM signal period, the control timing module can be set in multiple PWM signal periods, and the control timing module can be set to be at least three PWM signal periods; the invention is based on the combined design of a basic digital logic circuit and an analog circuit, can realize that an accurate feedback signal average value is obtained by using one PWM signal period in at least three PWM signal periods, and simultaneously, the time of at least one PWM signal period is provided for A/D (analog/digital) adoption and the time of at least one PWM signal period is used for regulating output; under the control of the control time sequence module, the integral sampler can firstly integrate the feedback signal in more than or equal to 3 PWM signal periods and obtain the average value of the feedback signal, then enters a holding state, provides a stable sampling signal and enough long sampling holding time for an A/D converter of the controller, and finally enters a zero clearing state to prepare for a zero starting point of the next integral link.

Finally, it should be noted that the above embodiments are merely representative examples of the present invention. It is obvious that the invention is not limited to the above-described embodiments, but that many variations are possible. Any simple modification, equivalent change and modification made to the above embodiments in accordance with the technical spirit of the present invention should be considered to be within the scope of the present invention.

Claims

1. A feedback signal high-speed sampling holding circuit driven by PWM waves is characterized by comprising a control time sequence module and an integral sampler, wherein the control time sequence module is connected with the integral sampler, the control time sequence module synchronizes PWM signals and outputs the PWM signals in a circulating mode, the control time sequence module integrates, holds and clears the feedback signals in a period which is more than or equal to 3 PWM signals by controlling the integral sampler so as to obtain an average value of the feedback signals, and the control time sequence module controls the integral sampler to provide time of at least one PWM signal period for feedback signal integration, time of at least one PWM signal period for holding sampling results and time of at least one PWM signal period for A/D sampling and A/D sampling for integral sampler and regulation output.

2. The high-speed sampling and holding circuit of the feedback signal of the PWM wave driven load according to claim 1, wherein when the integral sampler enters a holding state, the control timing module synchronously triggers A/D sampling; and when the integral sampler enters a zero clearing state, the control time sequence module adjusts calculation and updates control output.

3. The high-speed sample-and-hold circuit of claim 1, wherein the control timing module comprises a decimal counter and a dual four-input or gate chip, the decimal counter feeds one of the output terminals back to the reset terminal to form a ternary counter, and the remaining output terminals of the decimal counter are circularly output and connected to the corresponding input terminals of the dual four-input or gate chip.

4. The high-speed sampling and holding circuit of the feedback signal of the PWM wave driven load according to claim 1, wherein the integral sampler comprises a sampling circuit and a rectifying circuit, the sampling circuit is respectively connected with the rectifying circuit and the control timing module, and the sampling circuit integrates, holds and clears the output signal of the rectifying circuit.

5. The high-speed sample-and-hold circuit of the feedback signal of the PWM-wave-driven load according to claim 4, the rectification circuit is characterized by comprising an operational amplifier U1A, an operational amplifier U1B and peripheral devices, the peripheral devices comprise a resistor R1, a resistor R2 and a diode D1, the same-direction input end of the operational amplifier U1A is grounded, the inverting input terminal of the operational amplifier U1A is respectively connected with one end of a resistor R1 and one end of a resistor R2, the other end of the resistor R1 is used as a signal input end VIN of the integral sampler, the same-direction input end of the operational amplifier U1B is respectively connected with the other end of the resistor R2 and the anode of the diode D1, the cathode of the diode D1 is connected with the output end of the operational amplifier U1A, the output end of the operational amplifier U1B is respectively connected with the inverting input end and the sampling circuit, and the common connection end of the operational amplifier is used as the output end of the output signal V1 of the rectifying circuit.

6. The high-speed sampling and holding circuit of the feedback signal of the PWM wave driven load according to claim 4, wherein the sampling circuit comprises a resistor R3, a resistor R4, a resistor R5, a capacitor C1, a MOS transistor T1, a MOS transistor T2, a MOS transistor T3, a MOS transistor T4, and an operational amplifier U2A, one end of the resistor R3 is connected to the rectifying circuit, the other end of the resistor R3 is connected to one end of the resistor R4 and the drain of the MOS transistor T1 respectively, and the common connection end thereof is used as the output end of the rectifying circuit output signal V2, the source of the MOS transistor T1 is connected to the source of the MOS transistor T2, the drain of the MOS transistor T2 is grounded, the gate of the MOS transistor T1 is connected to the gate of the MOS transistor T2, and the common connection end thereof is connected to the control timing module, the same-direction input end of the operational amplifier U2A is grounded, the reverse input end of the operational amplifier U2 is connected to one end of the resistor R6356, the drain of the other end of the capacitor C1 and, the output end of the operational amplifier U2A is respectively connected with the other end of the capacitor C1 and one end of the resistor R5, the common connection end of the operational amplifier is used as a signal output end VOUT of the integral sampler, the other end of the resistor R5 is connected with the drain electrode of the MOS tube T4, the source electrode of the MOS tube T4 is connected with the source electrode of the MOS tube T3, the grid electrode of the MOS tube T4 is connected with the grid electrode of the MOS tube T3, and the common connection end of the MOS tube T4 is connected with the control timing module.