CN112087276A - Clock calibration method and device - Google Patents
Clock calibration method and device Download PDFInfo
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- CN112087276A CN112087276A CN201910518154.2A CN201910518154A CN112087276A CN 112087276 A CN112087276 A CN 112087276A CN 201910518154 A CN201910518154 A CN 201910518154A CN 112087276 A CN112087276 A CN 112087276A
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
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- H04J3/0635—Clock or time synchronisation in a network
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Abstract
The application discloses a method and a device for clock calibration, wherein the method comprises the steps of receiving a standard pulse-per-second signal; obtaining a first local pulse-per-second signal; acquiring a first phase difference between the first local pulse-per-second signal and the standard pulse-per-second signal; and acquiring a threshold value for filtering the phase difference according to the first phase difference, and filtering the interference signal in the standard pulse-per-second signal by using the threshold value for filtering the phase difference. By means of the method, the threshold value of the filtering phase difference for filtering the interference signals can be automatically adjusted, the influence of the interference signals is reduced, and the stability of the local clock is improved.
Description
Technical Field
The present application relates to the field of communications technologies, and in particular, to a method and an apparatus for clock calibration.
Background
The time reference of the communication System is from a GNSS (Global Navigation Satellite System), and Satellite signals are easily interfered by weather, a shelter, an electromagnetic field, or the like, and the interference may cause instability of the standard pulse-per-second signal output by the GNSS chip, so the communication System needs to eliminate the interference of the standard pulse-per-second signal in order to obtain a stable time reference and obtain better performance. The inventor of the application finds that in long-term research and development, the mode of setting a threshold value is usually adopted for eliminating the interference, namely, the pulse per second which is normally input to a system is considered to be periodic and can appear in the preset time, and the signal which belongs to the normal signal appears in the threshold value range of the standard time, otherwise, the signal is considered to be the interference signal and is filtered; however, because the threshold for filtering the interference signal is fixed, in order to adapt to all application environments, the threshold must be relatively large, so that part of the interference signal cannot be filtered, thereby causing the performance of the clock system to be reduced; furthermore, when the external second pulse is fixed to change to another position and the phase difference exceeds a threshold value, it is filtered as a disturbing signal.
Disclosure of Invention
The method and the device for calibrating the clock can automatically adjust and filter the threshold value of the interference signal, reduce the influence of the interference signal and improve the stability of the local clock.
In order to solve the above technical problem, a technical solution adopted by the present application is to provide a method for clock calibration, including: receiving a standard pulse-per-second signal; obtaining a first local pulse-per-second signal; acquiring a first phase difference between the first local pulse-per-second signal and the standard pulse-per-second signal; and acquiring a threshold value for filtering the phase difference according to the first phase difference, and filtering the interference signal in the standard pulse-per-second signal by using the threshold value.
In order to solve the above technical problem, another technical solution adopted by the present application is to provide a clock calibration apparatus, including at least: the clock source is coupled with the clock source and the local clock generating circuit, one end of the processor is coupled with the phase discriminator, the other end of the processor is coupled with one end of the local clock generating circuit, the phase discriminator and the processor form negative feedback, the clock source is used for outputting a standard second pulse signal, the local clock generating circuit is used for obtaining a first local second pulse signal, the phase discriminator is used for receiving the standard second pulse signal and the first local second pulse signal and obtaining a first phase difference between the first local second pulse signal and the standard second pulse signal, and the processor is used for obtaining a threshold value for filtering the phase difference according to the first phase difference and filtering interference signals in the standard second pulse signal by utilizing the threshold value for filtering the phase difference.
Through the scheme, the beneficial effects of the application are that: firstly, receiving a standard second pulse signal and a first clock signal, performing frequency multiplication on the first clock signal by using a phase-locked loop, generating a second clock signal, and then counting the second clock signal to generate a first local second pulse signal; then acquiring a first phase difference between the first local pulse-per-second signal and the standard pulse-per-second signal; the threshold value of the filtering phase difference is obtained by utilizing the first phase difference, and the interference signal mixed in the standard pulse-per-second signal is filtered by utilizing the threshold value of the filtering phase difference, so that the threshold value of the filtering interference signal can be automatically adjusted and filtered, and when the externally input standard pulse-per-second is stable, a small threshold value is generated, and a better filtering effect is achieved; meanwhile, when the externally input standard pulse per second is stably switched to another phase, a new phase can be locked again, so that the interference filtering effect is improved, the function of locking the standard pulse per second is ensured, the frequency change of a local clock is reduced, and the stability of the local clock is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:
FIG. 1 is a timing diagram of signals for interference rejection in the prior art;
FIG. 2 is another timing diagram of signals for interference rejection in the prior art;
FIG. 3 is a schematic flow chart diagram illustrating an embodiment of a method for clock calibration provided herein;
FIG. 4 is a schematic flow chart diagram illustrating another embodiment of a method for clock calibration provided herein;
FIG. 5 is a schematic flow chart diagram illustrating a clock calibration method according to another embodiment of the present application;
FIG. 6 is a timing diagram of signals in another embodiment of a method of clock calibration as provided herein;
FIG. 7 is a state transition diagram of a phase threshold in yet another embodiment of the method of clock calibration provided herein;
FIG. 8 is a schematic diagram of phase differences in a further embodiment of a method of clock calibration provided herein;
FIG. 9 is a schematic structural diagram of an embodiment of a clock calibration apparatus provided in the present application;
fig. 10 is a schematic structural diagram of another embodiment of a clock calibration apparatus provided in the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
At present, two main solutions for filtering the interference signal are available, one is to generate a window second pulse, as shown in fig. 1, if the GPS second pulse is not located within the window second pulse, it is considered as an interference signal, and actually, the range that it can filter is a pulse outside the window, and if the interference signal is within the window second pulse, it cannot be filtered; another way to achieve interference cancellation is to use a counter, for example, which counts the period of GPS second pulses using counting pulses with a frequency of 2MHz, the interval between the normal two standard GPS second pulses being 2X 106The counting pulses, as shown in fig. 2, are normal pulses of seconds occurring within a preset threshold range, and interference pulses of seconds occurring outside the threshold range, such as: the preset threshold is 20 clock cycles of counting pulses, and the interval between two pulses is [2 × 10 ]6-20，2×106+20]All signals belong to normal signals in one clock cycle, if two second pulses are monitored to have an interval of 2 multiplied by 106+30 clock cycles, which is out of the normal range, is considered as a jamming signal.
In both of the two modes, a method of fixing a threshold is used for filtering the interference signal, and in order to achieve the stability of the filtering function, the threshold is usually set to be larger, so that the interference signal within the threshold range cannot be filtered, and the filtering effect is not good enough.
Referring to fig. 3, fig. 3 is a schematic flowchart of an embodiment of a clock calibration method provided in the present application, where the method includes:
step 31: a standard pulse-per-second signal is received.
In order to realize clock calibration, a standard pulse-per-second signal needs to be received firstly.
Step 32: a first local pulse-per-second signal is obtained.
The first clock signal may be generated using an oscillator, which may be an oven controlled crystal oscillator; then, the first clock signal can be subjected to frequency multiplication by using a phase-locked loop, a second clock signal is generated, and then the second clock signal is counted to generate a first local second pulse signal with the period of 1 second; for example: the period of the first clock signal is 100ns, a phase-locked loop is used for generating a second clock signal with the period of 10ns, and then the period number of the second clock signal is counted, and each time 100 x 10 of the second clock signal is received6A first local pulse-per-second signal is generated after the second clock signal.
Step 33: a first phase difference between the first local pulse-per-second signal and the standard pulse-per-second signal is obtained.
In order to realize the tracking of the local clock signal to the standard pulse-per-second signal, so that the phase of the first local pulse-per-second signal is consistent with the phase of the standard pulse-per-second signal, it is necessary to acquire a first phase difference between the first local pulse-per-second signal and the standard pulse-per-second signal, and reduce the first phase difference by adjusting the phase of the first local pulse-per-second signal, so as to realize the following of the local clock signal to the standard pulse-per-second signal.
Step 34: and acquiring a threshold value for filtering the phase difference according to the first phase difference, and filtering the interference signal in the standard pulse-per-second signal by using the threshold value for filtering the phase difference.
Since satellite signals are easily interfered, the phase of the standard pulse-per-second signal may be suddenly changed, and in order to prevent the local clock from tracking the wrong input signal, the input signal with the wrong phase needs to be filtered, i.e. the interference signal is filtered.
After a first phase difference between a first local pulse per second signal and a standard pulse per second signal is obtained, a threshold value for filtering the phase difference is determined by using the first phase difference, so that interference signals in the obtained standard pulse per second signal are filtered, and the interference signals are prevented from influencing the local pulse signals.
Different from the prior art, the embodiment provides a clock calibration method, which includes receiving a standard pulse-per-second signal and a first clock signal, performing frequency multiplication on the first clock signal by using a phase-locked loop, generating a second clock signal, and then counting the second clock signal to generate a first local pulse-per-second signal; then acquiring a first phase difference between the first local pulse-per-second signal and the standard pulse-per-second signal; the threshold value of the filtering phase difference is obtained by utilizing the first phase difference, the interference signal mixed in the standard pulse per second signal is filtered by utilizing the threshold value of the filtering phase difference, the threshold value of the filtering phase difference for filtering the interference signal can be automatically adjusted, and when the externally input standard pulse per second is stable, the small threshold value of the filtering phase difference is generated, so that a better filtering effect is achieved; meanwhile, when the externally input standard pulse per second is stably switched to another phase, a new phase can be locked again, so that the interference filtering effect is improved, the function of locking the standard pulse per second is ensured, the frequency change of a local clock is reduced, and the stability of the local clock is improved.
Referring to fig. 4, fig. 4 is a schematic flowchart of another embodiment of a clock calibration method provided in the present application, the method including:
step 41: a standard pulse-per-second signal is received.
The standard pulse per second signal is a pulse signal generated by a global navigation satellite system or a Precision clock synchronization Protocol (PTP).
Step 42: a first local pulse-per-second signal is obtained.
Step 43: a first phase difference between the first local pulse-per-second signal and the standard pulse-per-second signal is obtained.
Wherein, steps 41-43 are the same as steps 31-33 in the above embodiment, and are not described herein again.
Step 44: and comparing each first phase difference in the preset period with a preset phase difference threshold value.
After the first phase difference between the first local pulse per second signal and the standard pulse per second signal is obtained, in order to obtain a threshold value of filtering phase difference for filtering interference signals included in the standard pulse per second signal, each first phase difference in a preset period may be compared with a preset phase difference threshold value, the preset phase difference threshold value is a threshold value of preset first filtering phase difference, the threshold value of the first filtering phase difference is also a threshold value of a maximum filtering phase difference, the preset phase difference threshold value may be infinite, and specific data may be used to represent infinity.
Step 45: after the system is powered on, the threshold value of the filtering phase difference is defaulted to be the threshold value of a preset first filtering phase difference; when all the first phase differences in the preset period are smaller than the threshold value of the preset second filtering phase difference, setting the threshold value of the filtering phase difference as the threshold value of the preset second filtering phase difference; and when all the first phase differences in the preset period are smaller than the preset threshold value of the third filtering phase difference, setting the threshold value of the filtering phase difference as the preset threshold value of the third filtering phase difference.
When all the first phase differences are smaller than a preset second filtering phase difference threshold value in a preset period, the fact that the threshold value of the current preset first filtering phase difference is larger is indicated, and in order to filter out interference signals, the threshold value of the preset first filtering phase difference needs to be reduced to the threshold value of the preset second filtering phase difference; if all the first phase differences in the preset period are smaller than the preset threshold value of the third filtering phase difference, setting the threshold value of the filtering phase difference as the preset threshold value of the third filtering phase difference; the threshold value of the first filtering phase difference is larger than the threshold value of the second filtering phase difference, and the threshold value of the second filtering phase difference is larger than the threshold value of the third filtering phase difference; and when all the first phase differences in the preset period are larger than the threshold value of the preset first filtering phase difference, directly filtering.
Step 46: and filtering the interference signals in the standard pulse-per-second signals by utilizing a threshold value for filtering the phase difference.
After the threshold value of the current filtering phase difference is determined, the interference signal in the standard pulse-per-second signal can be filtered by using the threshold value of the filtering phase difference, and the signal outside the threshold value of the filtering phase difference is filtered as the interference signal.
Step 47: and processing the first phase difference after the interference signals are filtered out to obtain a second local pulse per second signal, so that a second phase difference between the second local pulse per second signal and the standard pulse per second signal is smaller than the first phase difference.
After the interference signal is filtered, in order to realize the following of the first local pulse per second signal to the standard pulse per second signal, the first phase difference after the interference signal is filtered can be processed, the frequency or the phase of the first local pulse per second signal is adjusted, and the first local pulse per second signal is changed into the second local pulse per second signal, so that the second phase difference between the second local pulse per second signal and the standard pulse per second signal is smaller than the first phase difference.
The steps can be repeatedly executed to reduce the phase difference between the local pulse per second signal and the standard pulse per second signal, so that the phase difference between the local pulse per second signal and the standard pulse per second signal is close to 0, and the purpose of following the standard pulse per second signal is achieved.
Different from the prior art, the application provides a clock calibration method, which includes the steps of obtaining a first phase difference between a first local pulse per second signal and a standard pulse per second signal, comparing each first phase difference in a preset period with a preset phase difference threshold value, directly filtering when all the first phase differences in the preset period are larger than the preset phase difference threshold value, reducing the threshold value of the filtered phase difference when the first phase differences are smaller than the preset phase difference threshold value, automatically adjusting the threshold value of the filtered phase difference for filtering interference signals, adjusting the threshold value of the filtered phase difference according to the current first phase difference instead of directly setting the threshold value of the filtered phase difference as a fixed value, amplifying the threshold value to infinity, and when the phase difference between the standard pulse per second signal and the first local pulse per second signal suddenly changes and exceeds the threshold value of the filtered phase difference, the clock signal is not filtered as an interference signal, the influence of the interference signal is reduced, and meanwhile, the standard second pulse signal or the first local second pulse signal can be effectively prevented from being filtered as the interference signal, and the stability of the local clock is improved.
Referring to fig. 5, fig. 5 is a schematic flowchart of a clock calibration method according to another embodiment of the present application, the method including:
step 51: a standard pulse-per-second signal is received.
Step 52: a first clock signal output by an oscillator is received.
The steps 51-52 are the same as the steps 31-32 in the above embodiment, and are not described again here.
Step 53: and carrying out frequency multiplication on the first clock signal output by the oscillator, and counting the frequency-multiplied first clock signal to generate a first local pulse per second signal.
Carrying out frequency multiplication on a first clock signal output by an oscillator, counting the number of the received frequency-multiplied first clock signals, and generating a first local pulse signal after receiving the first clock signal in a preset period; for example: the frequency of the first clock signal output by the oscillator is 1MHz, and is 1 × 106The first local pulse-per-second signal is generated after one clock cycle as shown in fig. 6.
Step 54: a first phase difference between the first local pulse-per-second signal and the standard pulse-per-second signal is obtained.
Step 55: and acquiring a threshold value for filtering the phase difference according to the first phase difference, and filtering the interference signal in the standard pulse-per-second signal by using the threshold value for filtering the phase difference.
Wherein, steps 54-55 are the same as steps 33-34 in the above embodiment, and are not described again.
Step 56: and processing the first phase difference by using a clock calibration algorithm to obtain a digital signal, and converting the digital signal into an analog signal.
After obtaining the first phase difference, the first phase difference may be processed using a clock alignment algorithm (e.g., PID algorithm, proportional-Integral-derivative), the first phase difference may be converted into a digital signal, and the digital signal may be converted into an analog signal.
And 57: the analog signal is used to cause the oscillator to output a first clock signal.
The analog signal may be a voltage signal, and the generated voltage may be used to adjust an oscillation frequency of the oscillator, so that the oscillator outputs the first clock signal.
Step 58: the first clock signal is multiplied to generate a second clock signal.
Step 59: the second clock signal is counted to generate a second local pulse-per-second signal.
After the first clock signal is obtained, frequency multiplication is carried out on the first clock signal to generate a second clock signal, then the second clock signal is counted, and a second local second pulse signal with the period of 1 second is obtained; and the second phase difference between the second local pulse-per-second signal and the standard pulse-per-second signal is smaller than the first phase difference, so that the following of the local pulse-per-second signal to the standard pulse-per-second signal is realized.
Further, the threshold value of the filtering phase difference can be defaulted to be the maximum value after the power is on, the threshold value of the filtering phase difference is not changed before the clock is locked, and the threshold value of the filtering phase difference is adjusted after the clock is locked; the method comprises the steps of firstly calculating the maximum value and the minimum value of a plurality of first phase differences between a first local pulse per second signal and a standard pulse per second signal within preset time, and then judging whether to modify a phase difference threshold value according to the threshold value of the current filtering phase difference, the maximum value and the minimum value of the current first phase difference.
And recording the signal with the phase difference with the standard pulse-per-second signal larger than the modified phase difference threshold value as a useless signal, and recording the signal with the phase difference with the standard pulse-per-second signal smaller than the modified phase difference threshold value as a useful signal, thereby filtering the interference signal.
The following describes the variation of the phase difference threshold in detail, assuming that there are three phase difference thresholds: the states corresponding to the first phase difference threshold, the second phase difference threshold and the third phase difference threshold are respectively represented by State1, State2 and State3, and the automatic adjustment of the phase difference threshold is realized by State jump, as shown in fig. 7.
After the clock is locked, the clock enters a first phase difference threshold value, namely a maximum allowable range of phase difference, and at the moment, the threshold value for filtering the phase difference is also a maximum value (the threshold value for filtering the phase difference is preset).
When all the first phase differences within the preset time are smaller than the second phase difference threshold value, the first phase difference between the first local pulse per second signal and the standard pulse per second signal is considered to be reduced, a State2 corresponding to the second phase difference threshold value needs to be jumped to, the threshold value for filtering the phase difference is reduced along with the reduction of the first phase difference and is set as the preset second threshold value for filtering the phase difference.
And if all the first phase differences are smaller than the third phase difference threshold value within the preset time, jumping to a State3 corresponding to the third phase difference threshold value, reducing the threshold value of the filtered phase difference to be lower, and setting the threshold value of the filtered phase difference as the threshold value of the preset third filtered phase difference.
If at least one first phase difference is larger than the second phase difference threshold value and smaller than the first phase difference threshold value, the state corresponding to the first phase difference threshold value is kept unchanged, namely the threshold value of the filtered phase difference is the preset threshold value of the first filtered phase difference.
When the State is in a State2 corresponding to the second phase difference threshold value
If all the first phase differences within the preset time are greater than the second phase difference threshold, that is, the phase differences within the preset time are all filtered, it is determined that the first phase differences are increasing, and the State1 corresponding to the first phase difference threshold is skipped.
And if all the first phase differences are smaller than the third phase difference threshold value within the preset time, jumping to a State3 corresponding to the third phase difference threshold value, and further reducing the threshold value of the filtered phase difference to the threshold value of the third filtered phase difference.
If at least one first phase difference is larger than the third phase difference threshold and smaller than the second phase difference threshold, the State2 corresponding to the second phase difference threshold is kept unchanged, that is, the threshold for filtering the phase difference is the preset threshold for filtering the phase difference.
State3 corresponding to the third phase difference threshold
If all the first phase differences within the preset time are greater than the third phase difference threshold value, that is, the phase differences within the preset time are all filtered, it is considered that the first phase differences are increasing, the State2 corresponding to the second phase difference threshold value is jumped to, and the threshold value for filtering the phase differences is set as the threshold value for presetting the second filtering phase differences.
And if all the first phase differences within the preset time are greater than the second phase difference threshold value, jumping to a State1 corresponding to the first phase difference threshold value, and setting the threshold value for filtering the phase differences as the threshold value for presetting the first filtering phase differences.
If at least one first phase difference is smaller than the third phase difference threshold value, the State3 corresponding to the third phase difference threshold value is kept unchanged, that is, the threshold value of the filtered phase difference is the preset threshold value of the third filtered phase difference.
If the first phase difference is smaller and smaller, the local clock tracks the standard clock well, the phase difference threshold value is reduced, the threshold value for filtering the phase difference is reduced, and signals larger than the threshold value for filtering the phase difference are considered as interference signals and are filtered; if the first phase difference is larger and larger, the phase difference threshold value is increased, and the phase difference filtering threshold value is increased; therefore, a threshold value of the filtering phase difference more fitting the actual environment can be generated according to the first phase difference data of the actual local pulse per second signal and the standard pulse per second signal.
In the following process of the first local pulse per second signal to the standard pulse per second signal, the three states may be continuously switched, the threshold value of the current filtering phase difference can be continuously adjusted according to the current first phase difference, the threshold value of the filtering phase difference is automatically adjusted, and the effect of filtering interference signals is improved.
For example, as shown in fig. 8, the power-on is started at the 0 th second, at this time, the threshold of the default phase difference is the maximum, the clock is locked after M seconds, and the State1 corresponding to the first threshold of the phase difference is entered.
At the end of the first N seconds, since all the first phase differences are less than the second phase difference threshold Diff2, the State2 corresponding to the second phase difference threshold is jumped to.
At the end of the second N seconds, the State rises to State1, which corresponds to the first phase difference threshold, since all first phase differences are greater than second phase difference threshold Diff 2.
At the end of the third N seconds, the State drops to State2 corresponding to the second phase difference threshold, since all of the first phase differences are less than second phase difference threshold Diff 2.
At the end of the last fourth N seconds, since all the first phase differences are smaller than the third phase difference threshold Diff3, the State falls to State3 corresponding to the third phase difference threshold.
As can be seen from the above, the mutual jump between two adjacent states (e.g., State2 and State1) uses the same decision value Diff2, but one condition is that all the first phase differences within a predetermined time are greater than the second phase difference threshold Diff2, and the other condition is that all the first phase differences within a predetermined time are less than the second phase difference threshold Diff2, which are not the same, so that different states can be distinguished, and the threshold for filtering the phase differences can be changed.
In summary, if the State2 corresponding to the second phase difference threshold is currently in, and the threshold for filtering the phase difference is kept unchanged, at least one first phase difference must fall between the phase difference thresholds [ Diff1, Diff2] within the preset time; if the phase difference threshold value is reduced to the third phase difference threshold value Diff3, all the first phase differences within the preset time are smaller than the third phase difference threshold value Diff 3; if the phase difference threshold is increased to the first phase difference threshold Diff1, then all of the first phase differences within the predetermined time period are greater than the second phase difference threshold Diff 2.
The method is characterized by acquiring a first phase difference between a first local pulse per second signal and a standard pulse per second signal, adjusting a threshold value of a filtering phase difference according to a relation between the first phase difference and a preset phase difference, automatically adjusting the threshold value of the filtering phase difference for filtering interference signals, reducing the influence of the interference signals, processing the first phase difference by using a clock calibration algorithm to obtain a digital signal, converting the digital signal into an analog signal, controlling an oscillator to output a second clock signal by using the analog signal to generate a second local pulse per second signal, and re-generating the second phase difference between the second local pulse per second signal and the standard pulse to be smaller than the first phase difference so as to achieve the purpose of locking the standard pulse per second.
Referring to fig. 9, fig. 9 is a schematic structural diagram of an embodiment of a clock calibration apparatus provided in the present application; the clock calibration apparatus includes at least a clock source 91, a local clock generation circuit 92, a phase detector 93, and a processor 94.
The phase detector 93 is coupled to the clock source 91 and the local clock generation circuit 92, one terminal of the processor 94 is coupled to the phase detector 93, the other terminal of the processor 94 is coupled to one terminal of the local clock generation circuit 92, and the local clock generation circuit 92, the phase detector 93, and the processor 94 form negative feedback.
The clock source 91 is configured to output a standard pulse-per-second signal, the local clock generating circuit 92 is configured to obtain a first local pulse-per-second signal, the phase discriminator 93 is configured to receive the standard pulse-per-second signal and the first local pulse-per-second signal and obtain a first phase difference between the first local pulse-per-second signal and the standard pulse-per-second signal, and the processor 94 is configured to obtain a threshold value for filtering the phase difference according to the first phase difference and filter an interference signal in the standard pulse-per-second signal by using the threshold value for filtering the phase difference.
Different from the prior art, the present application provides a clock calibration apparatus, a first phase difference between a standard second pulse signal output by a clock source 91 and a first local second pulse signal output by a local clock generation circuit 92 is obtained by a phase detector 93, and a threshold of a filtering phase difference is adjusted by a processor 94 according to the first phase difference, so as to automatically adjust and filter the threshold of the filtering phase difference of an interference signal, thereby reducing the influence of the interference signal, and meanwhile, the processor 94 is used to control the local clock generation circuit 102, so that the first local second pulse output by the local clock generation circuit 102 locks the clock source 91, and the stability of the local clock is improved.
Referring to fig. 10, fig. 10 is a schematic structural diagram of another embodiment of the clock calibration apparatus provided in the present application; the clock calibration apparatus includes at least a clock source 101, a local clock generation circuit 102, a phase detector 103, and a processor 104.
The clock source 101 is a global navigation satellite system or a precision clock synchronization protocol and is used for outputting a standard second pulse signal; the local clock generation circuit 102 includes a frequency multiplication and counting circuit 1021 and an oscillator 1022 connected to each other.
The frequency doubling and counting circuit 1021 is a local clock source, and is configured to receive the first clock signal output by the oscillator 1022, generate a higher frequency clock by frequency doubling, and generate a first local pulse per second signal by counting, and output the first local pulse per second signal to the phase detector 103.
The phase detector 103 is coupled to the clock source 101 and the frequency doubling and counting circuit 1021, and configured to receive the standard pulse-per-second signal and the first local pulse-per-second signal, and obtain a first phase difference between the first local pulse-per-second signal and the standard pulse-per-second signal.
The processor 104 includes at least: a regulation filter circuit 1041, a regulator 1042, a digital-to-analog converter 1043 and a clock status reporting circuit 1044.
The adjusting and filtering circuit 1041 is coupled to the phase detector 103, and is configured to obtain a threshold value of a filtered phase difference according to the first phase difference, and filter an interference signal in the standard pulse-per-second signal by using the threshold value of the filtered phase difference; the adjusting and filtering circuit 1041 is further configured to compare the first phase difference in the preset period with a preset phase difference threshold, and after the system is powered on, the threshold for filtering the phase difference is default to the threshold for presetting the first filtering phase difference; when all the first phase differences in the preset period are smaller than the threshold value of the preset second filtering phase difference, setting the threshold value of the filtering phase difference as the threshold value of the preset second filtering phase difference; when all the first phase differences in the preset period are smaller than a preset threshold value of a third filtering phase difference, setting the threshold value of the filtering phase difference as the preset threshold value of the third filtering phase difference; and determining whether to adjust the threshold value and to which threshold value according to the value intervals of all the first phase differences in the preset period. The threshold value of the first filtering phase difference is larger than the threshold value of the second filtering phase difference, and the threshold value of the second filtering phase difference is larger than the threshold value of the third filtering phase difference.
The clock status reporting circuit 1044 is coupled to the adjusting and filtering circuit 1041, and is configured to upload the status of whether the clock is locked and the first phase difference to a central processing unit (not shown in the figure).
The regulator 1042 is coupled to the regulation filter circuit 1041 for processing the first phase difference by using a clock calibration algorithm to obtain a digital signal, and the regulator 1042 may be a PID controller.
One end of the digital-to-analog converter 1043 is coupled to the regulator 1042 for converting the digital signal sent by the regulator 1042 into an analog signal.
The other end of the digital-to-analog converter 1043 is coupled to an oscillator 1022, the oscillator 1022 is configured to generate a first clock signal according to the analog signal and send the first clock signal to the frequency doubling and counting circuit 1021, and the oscillator 1022 may be a voltage controlled oscillator; specifically, the oscillator 1022 may be an oven controlled crystal oscillator, and the frequency of the first clock signal may be 10 MHz.
The frequency doubling and counting circuit 1021 is connected to the phase detector 103, and is configured to frequency-double the first clock signal output by the oscillator 1022, and count the received frequency-doubled first clock signal to generate a first local pulse-per-second signal.
The processor 104 adjusts the frequency of the first clock signal output by the oscillator 1022 using the first phase difference output by the phase detector 103, and specifically, the processor 104 outputs different voltage signals according to different first phase differences, thereby controlling the frequency of the first clock signal output by the oscillator 1022; when the first phase difference output by the phase detector 103 is non-zero, the processor 104 adjusts the frequency of the output first clock signal, so as to adjust the phase of the first local pulse-per-second signal output by the frequency doubling and counting circuit 1021, so that the phase difference between the adjusted frequency doubling and first local pulse-per-second signal output by the counting circuit 1021 and the standard pulse-per-second signal output by the clock source 101 is reduced.
Negative feedback is formed by the phase discriminator 103, the adjusting and filtering circuit 1041, the adjuster 1042, the digital-to-analog converter 1043 and the frequency multiplication and counting circuit 1021; when the frequency of the clock signal output by the oscillator 1022 is greater than the standard frequency value, the phase detector 103 compares a first phase difference between the standard second pulse signal output by the clock source 101 and a first local second pulse signal output by the frequency doubling and counting circuit 1021, then the adjusting and filtering circuit 1041 is used to determine a threshold value for filtering the phase difference, and an interference signal is filtered by using the threshold value for filtering the phase difference, then the first phase difference is input to the adjuster 1042 to be processed into a digital signal, the adjuster 1042 transmits the digital signal to the digital-to-analog converter 1043, so that the analog signal output by the digital-to-analog converter 1043 is reduced, and the output frequency of the oscillator 1022 is reduced to approach the standard value.
For example, assuming that the frequency output by the oscillator 1022 is 10MHz +10Hz, which is slightly greater than the preset value (10MHz), the phase of the first local pulse-per-second signal is advanced by the standard pulse-per-second signal by comparing the phases of the first local pulse-per-second signal and the standard pulse-per-second signal, and then the PID regulator is used to reduce the value of the output digital signal, so that the voltage output by the digital-to-analog converter 1043 is correspondingly reduced, and therefore the frequency output by the oscillator 1022 is correspondingly reduced, and the frequency is reduced to 10MHz +5Hz, so that the first phase difference between the first local pulse-per-second signal and the standard pulse-per-second signal is reduced, and this process is repeated, so that the frequency output by the oscillator 1022 approaches 10 MHz.
On the contrary, if the frequency output by the oscillator 1022 is 10MHz-10Hz, which is smaller than the preset value, the phase of the local second pulse signal lags the phase of the standard second pulse signal by comparing the first local second pulse signal with the standard second pulse signal, and the PID regulator is used to increase the value of the output digital signal, the voltage output by the digital-to-analog converter 1043 is correspondingly increased, so that the frequency output by the oscillator 1022 is correspondingly increased, the frequency is increased to 10MHz-5Hz, thereby reducing the first phase difference between the first local second pulse signal and the standard second pulse signal, and repeating the process, so as to obtain a local accurate 10M clock, and provide an accurate clock for the communication system. .
Different from the prior art, the application provides a clock calibration device, obtain the phase difference between clock source 101 and frequency multiplication and counting circuit 1021 through phase discriminator 103, utilize and adjust filtering circuit 1041 and realize the threshold value of the filtering phase difference of automatic adjustment filtering interference signal, reduced the influence of interference signal, then adjust the voltage of input oscillator 1022 through regulator 1042 and digital-to-analog converter 1043, thereby change the output frequency of oscillator 1022, make the local second pulse phase change of frequency multiplication and counting circuit 1021 output, reduce the phase difference between local second pulse signal and the standard second pulse signal, thereby realize that local second pulse signal locks standard second pulse signal, obtain accurate stable local clock finally.
In the several embodiments provided in the present application, it should be understood that the disclosed method and apparatus may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of modules or units is merely a logical division, and an actual implementation may have another division, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed.
Units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.
In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units may be integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The above embodiments are merely examples, and not intended to limit the scope of the present application, and all modifications, equivalents, and flow charts using the contents of the specification and drawings of the present application, or those directly or indirectly applied to other related arts, are included in the scope of the present application.
Claims (10)
1. A method of clock calibration, comprising:
receiving a standard pulse-per-second signal;
obtaining a first local pulse-per-second signal;
acquiring a first phase difference between the first local pulse-per-second signal and the standard pulse-per-second signal;
and acquiring a threshold value for filtering the phase difference according to the first phase difference, and filtering the interference signal in the standard pulse-per-second signal by using the threshold value for filtering the phase difference.
2. The method of clock calibration according to claim 1, wherein said step of obtaining a threshold for filtering the phase difference based on the first phase difference comprises:
after the system is powered on, the threshold value of the filtering phase difference is defaulted to be the threshold value of a preset first filtering phase difference;
when all the first phase differences in the preset period are smaller than the threshold value of the preset second filtering phase difference, setting the threshold value of the filtering phase difference as the threshold value of the preset second filtering phase difference;
when all the first phase differences in the preset period are smaller than the threshold value of the preset third filtering phase difference, setting the threshold value of the filtering phase difference as the threshold value of the preset third filtering phase difference;
the threshold value of the first filtering phase difference is larger than the threshold value of the second filtering phase difference, the threshold value of the second filtering phase difference is larger than the threshold value of the third filtering phase difference, and the standard second pulse signal is a pulse signal generated by a global navigation satellite system or a precision clock synchronization protocol.
3. The method of clock calibration according to claim 1, further comprising:
and processing the first phase difference after the interference signal is filtered out to obtain a second local pulse per second signal, so that a second phase difference between the second local pulse per second signal and the standard pulse per second signal is smaller than the first phase difference.
4. The method according to claim 3, wherein the step of processing the first phase difference after filtering the interference signal to obtain a second local pulse-per-second signal, so that a second phase difference between the second local pulse-per-second signal and the standard pulse-per-second signal is smaller than the first phase difference comprises:
processing the first phase difference by using a clock calibration algorithm to obtain a digital signal, and converting the digital signal into an analog signal;
causing an oscillator to output the first clock signal using the analog signal;
multiplying the first clock signal to generate a second clock signal;
counting the second clock signal to generate the second local pulse-per-second signal.
5. The method of clock calibration according to claim 1, wherein said step of obtaining a first local pulse-per-second signal comprises:
and carrying out frequency multiplication on the first clock signal output by the oscillator, and counting the frequency-multiplied first clock signal to generate the first local pulse per second signal.
6. A clock calibration device is characterized by at least comprising a clock source, a phase discriminator, a local clock generating circuit and a processor, wherein the phase discriminator is coupled with the clock source and the local clock generating circuit, one end of the processor is coupled with the phase discriminator, the other end of the processor is coupled with one end of the local clock generating circuit, the phase discriminator and the processor form negative feedback, the clock source is used for outputting a standard second pulse signal, the local clock generating circuit is used for obtaining a first local second pulse signal, the phase discriminator is used for receiving the standard second pulse signal and the first local second pulse signal and obtaining a first phase difference between the first local second pulse signal and the standard second pulse signal, and the processor is used for obtaining a threshold value for filtering the phase difference according to the first phase difference, and filtering the interference signal in the standard pulse-per-second signal by using the threshold value of the filtering phase difference.
7. The clock calibration apparatus of claim 6,
the clock source is a global navigation satellite system or a precision clock synchronization protocol.
8. The clock calibration apparatus of claim 6, wherein the local clock generation circuit comprises an oscillator and a frequency multiplication and counting circuit connected to each other, and the processor comprises at least: a regulation filter circuit, a regulator, a digital-to-analog converter and a clock state reporting circuit,
the adjusting and filtering circuit is coupled with the phase discriminator and used for acquiring a threshold value of a filtering phase difference according to the first phase difference and filtering an interference signal in the standard pulse-per-second signal by using the threshold value of the filtering phase difference; the clock state reporting circuit is coupled with the adjusting and filtering circuit and is used for uploading the first phase difference to a central processing unit; the adjuster is coupled with the adjusting filter circuit and used for processing the first phase difference by utilizing a clock calibration algorithm to obtain a digital signal; one end of the digital-to-analog converter is coupled with the regulator and is used for converting the digital signal sent by the regulator into an analog signal; one end of the oscillator is coupled with the digital-to-analog converter, and the oscillator is used for generating the first clock signal according to the analog signal and sending the first clock signal to the frequency multiplication and counting circuit; the frequency doubling and counting circuit is connected with the phase discriminator and is used for frequency doubling the first clock signal output by the oscillator, counting the frequency-doubled first clock signal and generating the first local pulse per second signal.
9. The clock calibration apparatus of claim 8,
after the system is powered on, the threshold value of the filtering phase difference is defaulted to be the threshold value of a preset first filtering phase difference; when all the first phase differences in the preset period are smaller than the threshold value of the preset second filtering phase difference, setting the threshold value of the filtering phase difference as the threshold value of the preset second filtering phase difference; when all the first phase differences in the preset period are smaller than the threshold value of the preset third filtering phase difference, setting the threshold value of the filtering phase difference as the threshold value of the preset third filtering phase difference; wherein the threshold value of the first filtered phase difference is greater than the threshold value of the second filtered phase difference, and the threshold value of the second filtered phase difference is greater than the threshold value of the third filtered phase difference.
10. The clock calibration apparatus of claim 8,
the oscillator is an oven controlled crystal oscillator, and the frequency of the first clock signal is 10 MHz.
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