CN112071351B

CN112071351B - Flash memory programming operation method and operation circuit

Info

Publication number: CN112071351B
Application number: CN202010892461.XA
Authority: CN
Inventors: 黄明永
Original assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2020-08-31
Filing date: 2020-08-31
Publication date: 2023-06-30
Anticipated expiration: 2040-08-31
Also published as: CN112071351A

Abstract

The application relates to the field of memory, in particular to a flash memory programming operation method and an operation circuit. Wherein. The method comprises the following steps: providing a pulse sequence signal to a bit line of a memory cell, the pulse sequence signal comprising: a high level period and a low level period which alternate in sequence in the time domain; under the control of the programming permission signal, the memory unit performs programming operation according to programming input data during a period of high level of the pulse sequence signal; during a low level of the pulse sequence signal, making the memory cell perform a read detection operation; the read detect operation includes: reading out data stored in the memory cell, comparing whether the data read out during the low level period is consistent with the programming input data; if the two values are consistent, stopping programming operation; otherwise, the memory cell is made to perform a program operation again according to the program input data during the next high level period, and a read sensing operation during the subsequent low level period. Wherein the circuit is configured to perform the above method.

Description

Flash memory programming operation method and operation circuit

Technical Field

The application relates to the field of memory, in particular to a flash memory programming operation method and an operation circuit.

Background

Flash memory (Flash), which is a non-volatile memory, is capable of performing an Erase operation (Erase) and a Program operation (Program) on a block (sector), wherein all bits (bits) of the block are erased to a "1" state when the block is erased, and some bits (bits) of the block are changed from a "1" state to a "0" state when the block is programmed, and the Erase operation is required before the Program operation is performed, and all bits (bits) are erased to a "1" state.

In many cases, such as flash memory is used in a financial card, it is required that the total time for an erase operation and a program operation for one block is less than 1ms, and for this reason, means for reducing the time for the program operation is generally used to reduce the total time for the erase operation and the program operation.

However, the related art generally employs increasing the number of bits of one program operation to reduce the total time of the erase operation and the program operation, but such a measure increases the power consumption of the flash memory when performing the program operation.

Disclosure of Invention

The application provides a flash memory programming operation method and an operation circuit, which can solve the problem of larger programming power consumption when the total time of an erasing operation and a programming operation is reduced in the related art.

As a first aspect of the present application, there is provided a flash memory programming operation method including:

providing a pulse sequence signal to a bit line of a memory cell, the pulse sequence signal comprising: a high level period and a low level period which alternate in sequence in the time domain;

under control of a program permission signal, the memory unit performs a program operation according to program input data during a high level period of the pulse sequence signal;

during a low level of the pulse sequence signal, causing the memory cell to perform a read detection operation; the read detect operation includes: reading out the data stored in the memory cell, comparing whether the data read out during the low level period is consistent with the programming input data;

if the two values are consistent, stopping programming operation; otherwise, the memory cell is made to perform the program operation again according to the program input data during the next high level period, and the read sensing operation is performed during the subsequent low level period until the read data is identical to the program input data, and the program operation is stopped.

Optionally, the method further comprises:

if the memory cell has not been correctly read out after sequentially going through the high level period of the specific segment of the pulse sequence signal, the programming operation is stopped and the programming input data is replaced.

The method of claim 1, wherein the pulse sequence signal is reset to a low level period when the generation of the program enable signal is started.

Optionally, the charge pump module is configured to generate a high voltage signal that enables the memory cell to perform a programming operation; the pulse control module is connected between the output end of the charge pump module and the bit line of the storage unit, and is periodically turned off according to a pulse control signal to convert the high-voltage signal into the pulse sequence signal.

Optionally, the duty ratio of the high voltage signal is smaller than the duty ratio of the pulse control signal, and the duty ratio of the pulse control signal is equal to the duty ratio of the pulse sequence signal.

As a second aspect of the present application, there is provided a flash memory programming operation circuit including:

a memory cell on which a bit line is drawn;

the output end of the pulse sequence generating unit is connected with the bit line and is used for generating a pulse sequence signal to the bit line;

and the programming signal generating circuit is connected with the pulse sequence generating unit and is used for enabling the storage unit to perform programming operation according to programming input data in a high level period of the pulse sequence signal and performing reading detection operation in a low level period of the pulse sequence signal under the control of the programming permission signal.

Optionally, the pulse sequence generating unit comprises a charge pump module and a pulse control module;

the charge pump module is used for generating a high-voltage signal which can enable the memory cell to perform a programming operation;

the pulse control module is connected between the charge pump module and the bit line and is used for converting the high-voltage signal into the pulse sequence signal according to a pulse control signal.

Optionally, the program signal generating circuit is further configured to reset the pulse sequence signal to a low level period when the program enable signal starts to be generated.

The technical scheme of the application at least comprises the following advantages: the flash memory programming operation method and the flash memory programming operation circuit can reduce the time occupied by programming operation while guaranteeing the reliability of the programming operation.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a timing diagram of a high level signal applied to a bit line of a memory cell for a predetermined time Tprog in the related art;

FIG. 2 is a schematic diagram of a flash memory programming circuit according to one embodiment of the present application;

FIG. 3 is a waveform diagram of a PULSE sequence signal PULSE referred to in the present application;

fig. 4 is a timing diagram showing the program enable signal PROG, the PULSE control signal prog_interface, the high voltage signal SW provided by the charge pump module, and the PULSE sequence signal PULSE referred to in the present application;

fig. 5 is a flowchart of a flash memory programming method according to an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made apparent and complete in conjunction with the accompanying drawings, in which embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.

In addition, the technical features described below in the different embodiments of the present application may be combined with each other as long as they do not collide with each other.

In the related art, a unified program operation is generally performed on each bit of a memory cell, that is, a high level signal for a predetermined time Tprog is applied to a bit line of the memory cell, and the high level signal refers to fig. 1, so that each bit in the memory cell performs a program operation according to binary values on each bit of program input data. In principle, after a programming operation, the amount of electrons in the corresponding bit floating gate of the memory cell is changed to a target value, so that the binary number stored in each bit of the memory cell corresponds to the binary number value of each bit of the programming input data. However, in the memory cell, since there is a difference in performance of each bit, when the memory cell is subjected to the unified programming operation, there may be a case where the time required for the floating gate charge amount of each bit to reach the target value is different, that is, the charge amount in part of the bits can reach the target value faster and the charge amount in part of the bits reaches the target value slower. Bits that reach the target value faster are bits that are easier to program, and bits that reach the target value slower are bits that are harder to program. Therefore, in order to ensure the reliability of the programming operation, the predetermined time Tprog for which the high level signal for the programming operation is sustained is generally set to be long, typically 6us to 7.5us, but the time taken to perform the programming operation on the memory cell is long to pull down the read data rate of the memory, so that the performance of the memory is deteriorated.

In order to reduce the time occupied by the programming operation and ensure the reliability of the programming operation, the application provides a flash memory programming circuit and a flash memory programming method.

Fig. 2 shows a flash memory programming circuit according to an embodiment of the present application, the flash memory programming circuit includes:

a memory cell 100, a bit line BL is led out from the memory cell 100, and a PULSE sequence signal PULSE is applied to the bit line BL, so that the memory cell 100 performs a program operation during a high level of the PULSE sequence signal PULSE and performs a read detection operation during a low level of the PULSE sequence signal PULSE.

And a PULSE sequence generating unit 200, wherein an output terminal of the PULSE sequence generating unit 200 is connected to the bit line BL of the memory cell 100, for generating the PULSE sequence signal PULSE applied to the bit line BL.

Fig. 3 shows a waveform diagram of a PULSE sequence signal PULSE, which is a rectangular PULSE signal with alternating high and low levels, including high level periods H and low level periods L in the time domain, with reference to fig. 3, and the voltage amplitude of the PULSE sequence signal PULSE is a. During the high level period H of the waveform diagram of the PULSE sequence signal PULSE, the PULSE sequence generating unit 200 applies a high level on the bit line BL, and the memory cell 100 performs a program operation. During the low level period L of the waveform diagram of the PULSE sequence signal PULSE, the PULSE sequence generating unit 200 applies a low level to the bit line BL, and the memory cell 100 performs a read detection operation.

With continued reference to fig. 2, the flash memory programming circuit further includes a programming signal generating circuit 300, and the programming signal generating circuit 300 is connected to the PULSE sequence generating unit 200, and is configured to enable the memory cell 100 to perform a programming operation according to the programming input data Din during a high level period H of the PULSE sequence signal PULSE under the control of the program enable signal PROG.

In this embodiment, the memory unit 100 is capable of performing a single program operation according to the program input data Din during a high level period H of the PULSE sequence signal PULSE, and the duration of the high level period of the PULSE sequence signal PULSE is generally short, about 1us; after a short one-time programming operation, the memory cell 100 immediately performs a read sensing operation, i.e., reads out the data stored in the memory cell 100 during a low level period L of the PULSE sequence signal PULSE, compares the read-out data with the program input data Din, if the read-out data is identical to the program input data Din, stops the programming operation, and if the read-out data is different from the program input data Din, performs the programming operation again according to the program input data Din during a high level period H of the PULSE sequence signal PULSE, and performs the read sensing operation during a subsequent low level period L until the read-out data is identical to the program input data Din. For example, if the memory cell 100 sequentially goes through the 10 high periods H and the 10 low periods L of the PULSE sequence signal PULSE and is not correctly read, the programming operation is stopped and the programming input data Din is replaced.

With continued reference to fig. 1, the pulse train generation unit 200 includes a charge pump module 210 and a pulse control module 220.

The charge pump module 210 is configured to generate a high voltage signal SW for enabling the memory cell 100 to perform a programming operation, and the programming signal generating circuit 300 is connected to an output terminal of the charge pump module 210.

As an embodiment, the charge pump module 210 includes a charge pump 211 and a comparator 212, wherein a reference terminal Vref of the comparator 212 is connected to a power source, a feedback terminal FD of the comparator 212 is connected to an output terminal OUT of the charge pump 211, and the output terminal OUT of the charge pump 211 is an output terminal of the charge pump module 210; the output end of the comparator 212 is connected to the enable end EN of the charge pump 211, and the clock end CLK of the charge pump 211 is connected to a clock signal.

The PULSE control module 220 is connected between the charge pump module 210 and the bit line BL of the memory cell 100, and is configured to periodically turn off according to a PULSE control signal prog_interface, and convert a high voltage signal generated by the charge pump module 210 and used for performing a programming operation on the memory cell into the PULSE sequence signal PULSE, where a high level voltage amplitude of the PULSE sequence signal PULSE is equal to a high voltage generated by the charge pump module 210. Illustratively, the high voltage signal SW generated by the charge pump module 210 is a rectangular wave with a duty cycle that is smaller than the duty cycle of the PULSE control signal prog_interface, which is equal to the duty cycle of the PULSE sequence signal PULSE.

As an embodiment, the pulse control module 220 includes a first MOS switch tube N1, where a source of the first MOS switch tube N1 is connected to an output terminal of the charge pump 211, a drain is connected to a bit line of the memory cell 100, and a gate is connected to a pulse control signal prog_interface, and the pulse control signal prog_interface may be generated by a timer. The pulse control signal prog_interface is a rectangular wave with high and low levels alternating. When the PULSE control signal prog_interface is at a high level, the PULSE control module 220 is turned on, a high voltage signal generated by the charge pump module 210 can be transmitted to the bit line BL of the memory cell, and when the PULSE control signal prog_interface is at a low level, the PULSE control module 220 is turned off, and a voltage input to the bit line BL of the memory cell 100 is at a low level, thereby generating a PULSE sequence signal PULSE sequentially alternating in time domain during the high level period and the low level period.

Referring to fig. 1, the program signal generating circuit 300 includes: d flip-flop 310 and constant current source module 320.

The constant current source module 320 includes a second MOS switch tube N2 and a constant current source I1, a gate of the second MOS switch tube N2 is connected to the output end of the D flip-flop 310 through an inverter, a source of the second MOS switch tube N2 is connected to the constant current source I1, and a drain of the second MOS switch tube N2 is connected to the output end of the charge pump module 210.

The D flip-flop 310 includes a reset terminal RST, an input terminal D, and an output terminal Q; the reset end RST of the D flip-flop 310 is connected to the program enable signal PROG through an inverter, the output end Q of the D flip-flop 310 is connected to the gate of the second MOS switch transistor N2 through an inverter, and the input end D of the D flip-flop is used for inputting the program input data Din.

Fig. 4 shows a timing diagram of the program enable signal PROG, the PULSE control signal prog_interface, the high voltage signal SW provided by the charge pump module, and the PULSE sequence signal PULSE.

It can be seen from fig. 4 that the duty cycle of the high voltage signal SW is smaller than the duty cycle of the PULSE control signal prog_interface, which is equal to the duty cycle of the PULSE sequence signal PULSE.

Referring to fig. 4, the high level and the low level of the pulse control signal prog_interface are provided periodically alternately. The program enable signal PROG starts to be generated at time t0, i.e., the program enable signal PROG at time t0 is a rising edge, the program enable signal PROG stops at time tn, i.e., the program enable signal PROG at time tn is a falling edge, and the memory cell performs at least one programming operation and at least one read detection operation within the time period t 0-tn. For example, in the period t11 to t12, the program enable signal PROG is high, and the memory cell sequentially performs a set of program operation and read detection operation.

At time t0, the program enable signal PROG starts to be generated, that is, the program enable signal PROG is at a rising edge, and since the program signal generating circuit 300 is connected to the output terminal of the charge pump module 210, the second MOS switch transistor N2 of the program signal generating circuit 300 is turned on instantaneously at this time, and since the constant current source I1 generates the pull-down current, the potential of the output terminal of the charge pump module 210 is reduced to a low level, that is, the PULSE sequence signal PULSE and the high voltage signal SW provided by the charge pump module are reset to a low level. With the arrival of the next high level, i.e., in the period t11-t1, the PULSE control signal prog_interface is high, so that the high level of the high voltage signal SW generated by the charge pump module can be transferred to the bit line BL, thereby forming the high level period H of the PULSE sequence signal PULSE.

In the period t1-t12, the PULSE control signal prog_interface is low, so that the charge pump module and the bit line BL can be disconnected, thereby forming a low period L of the PULSE sequence signal PULSE.

The time length of t0-tn for different memory cells is variable, i.e. when there are more difficult bits to perform programming operation in the memory cells, the time length of t0-tn is longer, i.e. the number of times of programming operation and read detection operation is more; if the bits in the memory cell are all bits which are easier to program, the time length of t0-tn required by the memory cell is shorter, so that the flash memory programming operation method and the flash memory programming operation circuit provided by the embodiment of the application can reduce the time occupied by the programming operation while ensuring the reliability of the programming operation.

Referring to fig. 5 on the basis of any one of fig. 1 to 4, fig. 5 shows a flowchart of a flash memory programming method according to an embodiment of the present application, and the flash memory programming operation method includes the following steps:

step S1: providing a pulse sequence signal to a bit line of a memory cell, the pulse sequence signal comprising: the high level period and the low level period alternate in sequence in the time domain.

Step S2: the memory cell is caused to perform a program operation according to the program input data during a high level of the pulse sequence signal under control of a program enable signal.

Step S3: during a low level of the pulse sequence signal, causing the memory cell to perform a read detection operation; the read detect operation includes: and reading out the data stored in the memory cell, and comparing whether the data read out during the low level period is consistent with the programming input data.

Step S4: if so, stopping the programming operation.

Step S5: otherwise, the memory cell is made to perform the program operation again according to the program input data during the next high level period, and the read sensing operation is performed during the subsequent low level period until the read data is identical to the program input data, and the program operation is stopped.

The pulse sequence signal is reset to a low level period when the generation of the program enable signal is started.

As an embodiment, with continued reference to fig. 2, the memory cell is capable of performing a single program operation according to the program input data Din during a high level period H of the PULSE sequence signal PULSE, which is typically short in duration, about 1us; after a short one-time programming operation, the memory cell 100 immediately performs a read sensing operation, i.e., reads out the data stored in the memory cell 100 during a low level period L of the PULSE sequence signal PULSE, compares the read-out data with the program input data Din, if the read-out data is identical to the program input data Din, stops the programming operation, and if the read-out data is different from the program input data Din, performs the programming operation again according to the program input data Din during a high level period H of the PULSE sequence signal PULSE, and performs the read sensing operation during a subsequent low level period L until the read-out data is identical to the program input data Din. For example, if the memory cell 100 sequentially goes through the 10 high periods H and the 10 low periods L of the PULSE sequence signal PULSE and is not correctly read, the programming operation is stopped and the programming input data Din is replaced.

The total time length of the total programming operation time and the total time length of the reading detection operation time of different memory cells are changed, namely when bits which are difficult to perform programming operation exist in the memory cells, the total time length of the memory cells is longer, namely the times of the programming operation and the reading detection operation are more; if the bits in the memory cells are all bits which are easier to program, the total time required by the memory cells is shorter, so that the flash memory programming operation method and the flash memory programming operation circuit provided by the embodiment of the application can reduce the time occupied by the programming operation while ensuring the reliability of the programming operation.

It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While nevertheless, obvious variations or modifications may be made to the embodiments described herein without departing from the scope of the invention.

Claims

1. A method of flash memory programming operation, the method comprising:

2. The flash memory programming operation method of claim 1, further comprising:

3. The method of claim 1, wherein the pulse sequence signal is reset to a low level period when the generation of the program enable signal is started.

4. The method of claim 1, wherein a charge pump module is used to generate a high voltage signal that enables the memory cell to perform a program operation; the pulse control module is connected between the output end of the charge pump module and the bit line of the storage unit, and is periodically turned off according to a pulse control signal to convert the high-voltage signal into the pulse sequence signal.

5. The flash memory programming operation method of claim 4, wherein a duty cycle of the high voltage signal is smaller than a duty cycle of the pulse control signal, the duty cycle of the pulse control signal being equal to a duty cycle of the pulse sequence signal.

6. A flash memory programming operation circuit, the flash memory programming operation circuit comprising:

a memory cell on which a bit line is drawn;

7. The flash memory programming operation circuit of claim 6, wherein the pulse sequence generating unit comprises a charge pump module and a pulse control module;

8. The flash memory programming operation circuit of claim 6, wherein the programming signal generating circuit is further configured to reset the pulse sequence signal to a low level period when the generation of the programming permission signal is started.