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CN112051963B - Data writing method, memory control circuit unit and memory storage device - Google Patents

Data writing method, memory control circuit unit and memory storage device Download PDF

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Publication number
CN112051963B
CN112051963B CN201910489531.4A CN201910489531A CN112051963B CN 112051963 B CN112051963 B CN 112051963B CN 201910489531 A CN201910489531 A CN 201910489531A CN 112051963 B CN112051963 B CN 112051963B
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Prior art keywords
data
physical
unit
memory
physical erase
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CN201910489531.4A
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CN112051963A (en
Inventor
林纬
许祐诚
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Phison Electronics Corp
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Phison Electronics Corp
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)

Abstract

Data writing method, memory control circuit unit and memory storage device. The method comprises the following steps: receiving a plurality of data; writing the plurality of data into the first physical erasing unit by using a multi-page programming mode; writing at least one first data in the plurality of data into a second physical erasing unit by using a single page programming mode; verifying the data stored in the first physical erase unit; and when verification fails, performing write operation on the third physical erase unit according to the first data and the plurality of data by using a multi-page programming mode.

Description

Data writing method, memory control circuit unit and memory storage device
Technical Field
The invention relates to a data writing method, a memory control circuit unit and a memory storage device.
Background
Digital cameras, mobile phones and MP3 have grown very rapidly over the years, and consumer demand for storage media has also increased rapidly. Because the rewritable non-volatile memory has the characteristics of non-volatility, power saving, small volume, no mechanical structure, high reading and writing speed and the like, the memory is most suitable for portable electronic products such as notebook computers. Solid state disk is a memory storage device using flash memory as storage medium. Therefore, the flash memory industry has recently become a very popular ring in the electronics industry.
The NAND (NAND) type flash memory may be classified into a single Level Cell (Single Level Cell, SLC) type flash memory, a Multi Level Cell (MLC) type flash memory, and a third Level Cell (Trinary Level Cell, TLC) type flash memory according to the number of bits that each memory Cell may store, wherein each memory Cell of the SLC NAND type flash memory may store 1 bit of data (i.e., "1" and "0"), each memory Cell of the MLC NAND type flash memory may store 2 bits of data, and each memory Cell of the TLC NAND type flash memory may store 3 bits of data.
The memory management circuitry may write to the rewritable non-volatile memory module using a single page programming mode or a multi-page programming mode. The memory cells programmed in the single page programming mode are used to store 1 bit of data. The memory cells programmed in the multi-page programming mode are used to store a plurality of bits of data.
It is assumed that the memory management circuit is preset to write the data of a write command into the rewritable nonvolatile memory module using the multi-page programming mode. However, the reliability of data written using the multi-page programming mode is lower than that of the single-page programming mode. In other words, the data written using the multi-page programming mode may fail to be written, resulting in the written data having uncorrectable error bits. Therefore, in the conventional method, when the memory management circuit presets to write the data of the write command to the rewritable nonvolatile memory module using the multi-page programming mode, the memory management circuit also writes all the data corresponding to the write command to at least one physical erasing unit in the rewritable nonvolatile memory module using the single-page programming mode. The memory management circuit then verifies all the data of the write command written using the multi-page programming mode to determine if a write failure occurred while writing to one (or some) of the physical programming units. Assuming that a physical program unit is written with data using a multi-page program mode, when the data stored in the physical program unit has uncorrectable error bits (i.e., a write failure occurs), the memory management circuit uses the data previously written using the single-page program mode to recover the data. That is, in the foregoing example, the single page programming mode is used for data restoration and backup.
It should be noted that the process of backing up data using the single page programming mode can be time consuming as well as space for the rewritable non-volatile memory module. In addition, the memory management circuit verifies all the data of the write command written using the multi-page programming mode to determine whether a write failure occurred when writing to one (or some) of the physical programming units.
Disclosure of Invention
The invention provides a data writing method, a memory control circuit unit and a memory storage device, which can reduce the time required by data writing and verification.
The invention provides a data writing method, which is used for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, each entity erasing unit in the plurality of entity erasing units is provided with a plurality of entity programming units, and the data writing method comprises the following steps: receiving a plurality of data; writing the plurality of data into a first physical erase unit of the plurality of physical erase units using a multi-page programming mode; writing at least one first data of the plurality of data into a second physical erase unit of the plurality of physical erase units using a single page programming mode; verifying the plurality of data stored in the first physical erase unit; and when verification fails, performing a write operation on a third physical erase unit among the plurality of physical erase units according to the first data and the plurality of data using the multi-page programming mode.
In an embodiment of the present invention, the probability of a write failure of at least one first physical program unit in the first physical erase unit for storing the first data is higher than the probability of a write failure of other physical program units in the first physical erase unit.
In one embodiment of the invention, the method comprises: validating data stored in the first physical programming unit; when the data in the first entity programming unit does not have uncorrectable bits, marking at least one second entity programming unit in the second entity erasing unit for storing the first data as invalid; when there is an uncorrectable bit in a second data in the first physical program unit, writing the second data in the second physical program unit into the third physical erase unit according to the data in the other physical program units in the first physical erase unit and the data in the second physical program unit in the second physical erase unit by using the multi-page program mode.
In an embodiment of the invention, the first data is in an amount of thirty percent of the plurality of data.
In an embodiment of the present invention, the rewritable nonvolatile memory module includes n word lines, the n word lines are arranged in a sequence, and a plurality of memory cells on a same word line among the n word lines form at least one of the plurality of physical programming units. The first physical programming unit is formed by a plurality of first memory cells in the plurality of memory cells, and the plurality of first memory cells are located on at least one first word line in the n word lines, wherein n is a positive integer greater than zero.
In one embodiment of the present invention, the first word line is located in the 0 th to i th word lines, the j th to k th word lines, or the h-n-1 th word lines of the n word lines. Wherein i, j, k, h are each positive integers greater than zero and discontinuous with each other, i is less than j, j is less than k, k is less than h and h is less than n.
In one embodiment of the present invention, the step of receiving the plurality of data includes: receiving at least one writing instruction issued by the host system, wherein the writing instruction is used for indicating writing of the plurality of data into the rewritable nonvolatile memory module; and temporarily storing the data into a buffer memory.
The invention proposes a memory control circuit unit, is used for controlling a rewritable nonvolatile memory module, the said memory control circuit unit includes: host interface, memory interface and memory management circuitry. The host interface is used for being electrically connected to the host system. The memory interface is electrically connected to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module is provided with a plurality of physical erasing units, and each physical erasing unit in the plurality of physical erasing units is provided with a plurality of physical programming units. The memory management circuit is electrically connected to the host interface and the memory interface. The memory management circuit is configured to perform the steps of: receiving a plurality of data; writing the plurality of data into a first physical erase unit of the plurality of physical erase units using a multi-page programming mode; writing at least one first data of the plurality of data into a second physical erase unit of the plurality of physical erase units using a single page programming mode; verifying the plurality of data stored in the first physical erase unit; and when verification fails, performing a write operation on a third physical erase unit among the plurality of physical erase units according to the first data and the plurality of data using the multi-page programming mode.
In an embodiment of the present invention, the probability of a write failure of at least one first physical program unit in the first physical erase unit for storing the first data is higher than the probability of a write failure of other physical program units in the first physical erase unit.
In an embodiment of the present invention, the memory management circuit is further configured to verify the data stored in the first physical programming unit. When there is no uncorrectable bit in the data in the first physical program unit, the memory management circuit is further configured to mark at least one second physical program unit in the second physical erase unit for storing the first data as invalid. When there is an uncorrectable bit in a second data in the first physical program unit, the memory management circuit is further configured to write the second physical erase unit in the second physical erase unit according to the data in the other physical program units in the first physical erase unit and the data in the second physical program unit in the second physical erase unit.
In an embodiment of the invention, the first data is in an amount of thirty percent of the plurality of data.
In an embodiment of the present invention, the rewritable nonvolatile memory module includes n word lines, the n word lines are arranged in a sequence, and a plurality of memory cells on a same word line among the n word lines form at least one of the plurality of physical programming units. The first physical programming unit is formed by a plurality of first memory cells in the plurality of memory cells, and the plurality of first memory cells are located on at least one first word line in the n word lines, wherein n is a positive integer greater than zero.
In one embodiment of the present invention, the first word line is located in the 0 th to i th word lines, the j th to k th word lines, or the h-n-1 th word lines of the n word lines. Wherein i, j, k, h are each positive integers greater than zero and discontinuous with each other, i is less than j, j is less than k, k is less than h and h is less than n.
In an embodiment of the present invention, in operation of receiving the plurality of data, the memory management circuit is further configured to receive at least one write command issued by the host system, wherein the write command is configured to instruct writing the plurality of data to the rewritable nonvolatile memory module. The memory management circuit is further configured to temporarily store the plurality of data into a buffer memory.
The invention proposes a memory storage device comprising: the memory control circuit unit is connected with the interface unit, the rewritable nonvolatile memory module and the memory control circuit unit. The connection interface unit is used for being electrically connected to a host system. The rewritable nonvolatile memory module is provided with a plurality of physical erasing units, and each physical erasing unit in the plurality of physical erasing units is provided with a plurality of physical programming units. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable nonvolatile memory module. The memory control circuit unit is used for executing the following operations: receiving a plurality of data; writing the plurality of data into a first physical erase unit of the plurality of physical erase units using a multi-page programming mode; writing at least one first data of the plurality of data into a second physical erase unit of the plurality of physical erase units using a single page programming mode; verifying the plurality of data stored in the first physical erase unit; and when verification fails, performing a write operation on a third physical erase unit among the plurality of physical erase units according to the first data and the plurality of data using the multi-page programming mode.
In an embodiment of the present invention, the probability of a write failure of at least one first physical program unit in the first physical erase unit for storing the first data is higher than the probability of a write failure of other physical program units in the first physical erase unit.
In an embodiment of the invention, the memory control circuit unit is further configured to verify the data stored in the first physical programming unit. When there is no uncorrectable bit in the data in the first physical program unit, the memory control circuit unit is further configured to mark at least one second physical program unit for storing the first data in the second physical erase unit as invalid. When there is an uncorrectable bit in a second data in the first physical program unit, the memory control circuit unit is further configured to write the second physical erase unit in the second physical erase unit according to the data in the other physical program units in the first physical erase unit and the data in the second physical program unit in the second physical erase unit.
In an embodiment of the invention, the first data is in an amount of thirty percent of the plurality of data.
In an embodiment of the present invention, the rewritable nonvolatile memory module includes n word lines, the n word lines are arranged in a sequence, and a plurality of memory cells on a same word line among the n word lines form at least one of the plurality of physical programming units. The first physical programming unit is formed by a plurality of first memory cells in the plurality of memory cells, and the plurality of first memory cells are located on at least one first word line in the n word lines, wherein n is a positive integer greater than zero.
In one embodiment of the present invention, the first word line is located in the 0 th to i th word lines, the j th to k th word lines, or the h-n-1 th word lines of the n word lines. Wherein i, j, k, h are each positive integers greater than zero and discontinuous with each other, i is less than j, j is less than k, k is less than h and h is less than n.
In an embodiment of the present invention, in operation of receiving the plurality of data, the memory control circuit unit is further configured to receive at least one write command issued by the host system, wherein the write command is configured to instruct to write the plurality of data to the rewritable nonvolatile memory module. The memory control circuit unit is further configured to temporarily store the plurality of data into a buffer memory.
Based on the above, the data writing method, the memory control circuit unit and the memory storage device of the present invention can be used for backing up only a part of data when the data writing using the multi-page programming mode is preset, and only verifying a part of data in the physical programming unit during verifying the data written using the multi-page programming mode, thereby reducing the time required for writing and verifying the data.
In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention;
FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another example embodiment of the invention;
FIG. 3 is a schematic diagram of a host system and a memory storage device according to another example embodiment of the invention;
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;
FIGS. 5A and 5B are schematic diagrams illustrating an exemplary memory cell memory architecture and a physical erase unit according to the present exemplary embodiment;
FIG. 6A is a schematic block diagram of a memory control circuit unit according to an example embodiment of the invention;
FIG. 6B is a schematic diagram of a multi-frame encoding according to an example embodiment of the invention;
FIGS. 7 and 8 are schematic diagrams illustrating exemplary erase unit of a management entity according to an exemplary embodiment;
FIG. 9 is a schematic diagram illustrating writing data to a rewritable non-volatile memory module using a single page programming mode, according to an example;
FIG. 10 is a schematic diagram illustrating writing data to a rewritable non-volatile memory module using a multi-page programming mode according to an example;
FIGS. 11-12 are schematic diagrams illustrating an example of a data writing method according to an example of the present invention;
fig. 13 is a flowchart illustrating a data writing method according to an example of the present invention.
Reference numerals illustrate:
10: memory storage device
11: host system
110: system bus
111: processor and method for controlling the same
112: random access memory
113: read-only memory
114: data transmission interface
12: input/output (I/O) device
20: motherboard
201: portable disk
202: memory card
203: solid state disk
204: wireless memory storage device
205: global positioning system module
206: network interface card
207: wireless transmission device
208: keyboard with keyboard body
209: screen panel
210: horn with horn body
32: SD card
33: CF card
34: embedded memory device
341: embedded multimedia card
342: embedded multi-chip packaging storage device
402: connection interface unit
WL 0-WL 127: word line
404: memory control circuit unit
406: rewritable nonvolatile memory module
702: memory management circuit
704: host interface
706: memory interface
708: error checking and correcting circuit
710: buffer memory
712: power management circuit
801 (1) to 801 (r): position of
820: encoding data
810 (0) to 810 (E): entity programming unit
502: data area
504: idle zone
506: temporary storage area
508: substitution region
510 (0) to 510 (N): physical erasing unit
LBA (0) to LBA (H): logic unit
LZ (0) to LZ (M): logic area
D0 to D255: data
S1301: step of receiving a plurality of data
S1303: writing the plurality of data into the first physical erasing unit by using the multi-page programming mode
S1305: writing first data in the plurality of data into a second physical erasing unit by using a single page programming mode, wherein the probability of the write failure of a first physical programming unit for storing the first data in the first physical erasing unit is higher than that of the write failure of other physical programming units in the first physical erasing unit
S1307: verifying data stored in a first physical programming unit
S1309: marking a second physical program unit for storing the first data in the second physical erase unit as invalid
S1311: writing the third physical erase unit using the multi-page program mode according to the data in the other physical program units in the first physical erase unit and the data in the second physical program unit in the second physical erase unit
Detailed Description
Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable nonvolatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Memory storage devices are typically used with host systems so that the host system can write data to or read data from the memory storage device.
FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the invention. FIG. 2 is a schematic diagram of a host system, a memory storage device, and an I/O device according to another example embodiment of the invention.
Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a random access memory (random access memory, RAM) 112, a Read Only Memory (ROM) 113, and a data transfer interface 114. The processor 111, the random access memory 112, the read only memory 113, and the data transfer interface 114 are electrically connected to a system bus 110.
In the present exemplary embodiment, the host system 11 is electrically connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 is electrically connected to the I/O device 12 through the system bus 110. For example, host system 11 may transmit output signals to I/O device 12 or receive input signals from I/O device 12 via system bus 110.
In the present exemplary embodiment, the processor 111, the ram 112, the rom 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 can be electrically connected to the memory storage device 10 through a wired or wireless manner via the data transmission interface 114. The memory storage device 10 may be, for example, a flash drive 201, a memory card 202, a solid state disk (Solid State Drive, SSD) 203, or a wireless memory storage device 204. The wireless memory storage 204 may be, for example, a near field communication (Near Field Communication, NFC) memory storage, a wireless facsimile (WiFi) memory storage, a Bluetooth (Bluetooth) memory storage, or a Bluetooth low energy memory storage (iBeacon) or the like based on a variety of wireless communication technologies. In addition, the motherboard 20 may also be electrically connected to various I/O devices such as a global positioning system (Global Positioning System, GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 through the wireless transmission device 207.
In an example embodiment, the host system referred to is any system that can cooperate with substantially a memory storage device to store data. Although the host system is described in the above exemplary embodiment as a computer system, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, the host system 31 may be a system such as a digital camera, a video camera, a communication device, an audio player, a video player or a tablet computer, and the memory storage device 30 may be a variety of nonvolatile memory storage devices such as an SD card 32, a CF card 33 or an embedded storage device 34. The embedded memory device 34 includes embedded memory devices of various types, such as an embedded multimedia card (eMMC) 341 and/or an embedded multi-chip package memory device (embedded Multi Chip Package, eMCP) 342, which directly electrically connects the memory module to the substrate of the host system.
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.
Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404, and a rewritable nonvolatile memory module 406.
In the present exemplary embodiment, the connection interface unit 402 is compatible with the serial advanced technology attachment (Serial Advanced Technology Attachment, SATA) standard. However, it should be understood that the present invention is not limited thereto, and the connection interface unit 402 may be a Flash Memory Card (MMC) interface standard, an embedded multimedia Memory Card (Embedded Multimedia Card, eMMC) interface standard, a universal Digital (Universal Flash Storage, UFS) interface standard, an Ultra High Speed-I (UHS-I) interface standard, a Ultra High Speed-II (UHS-II) interface standard, a Memory Stick (MS) interface standard, a Multi-Chip Package (Multi-Chip Package) interface standard, a multimedia Card (MMC) interface standard, an embedded multimedia Card (Embedded Multimedia Card, eMMC) interface standard, a universal Flash Memory (Universal Flash Storage, UFS) interface standard, an embedded Multi-Chip Package (embedded Multi Chip Package, eMMC) interface standard, a Compact Flash Memory Card (Flash) interface standard, or other Flash drive-integrated standard, which are compliant with the parallel advanced technology attachment (Parallel Advanced Technology Attachment, PATA) standard. The connection interface unit 402 may be packaged with the memory control circuit unit 404 in a single chip, or the connection interface unit 402 may be disposed off-chip with the memory control circuit unit 404.
The memory control circuit unit 404 is configured to execute a plurality of logic gates or control instructions implemented in hardware or firmware, and perform operations of writing, reading, erasing, merging, etc. of data in the rewritable nonvolatile memory module 406 according to the instructions of the host system 11.
The rewritable nonvolatile memory module 406 is electrically connected to the memory control circuit unit 404, and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 has physical erase units 510 (0) through 510 (N). For example, the physical erase units 510 (0) -510 (N) may belong to the same memory die (die) or to different memory dies. Each physical erase unit has a plurality of physical program units, for example, in the exemplary embodiment of the present invention, each physical erase unit includes 258 physical program units, and the physical program units belonging to the same physical erase unit can be independently written and simultaneously erased. However, it should be understood that the present invention is not limited thereto, and each physical erasing unit may be composed of 64 physical programming units, 256 physical programming units or any other physical programming units.
In more detail, a physical erased cell is the minimum unit of erase. That is, each physically erased cell contains a minimum number of memory cells that are erased. The physical programming unit is the minimum unit of programming. That is, the physical programming unit is the smallest unit of write data. Each physical programming unit typically includes a data bit region and a redundancy bit region. The data bit area includes a plurality of physical access addresses for storing user data, and the redundant bit area is used for storing system data (e.g., control information and error correction codes). In the present exemplary embodiment, each physical programming unit includes 4 physical access addresses, and one physical access address has a size of 512 bytes (byte). However, in other exemplary embodiments, a greater or lesser number of physical access addresses may be included in the data bit region, and the present invention is not limited to the size and number of physical access addresses.
In an example embodiment of the invention, the rewritable nonvolatile memory module 406 is a complex level memory cell (Trinary Level Cell, TLC) NAND type flash memory module (i.e., a flash memory module that can store 3 bits of data in one memory cell). However, the invention is not limited thereto, and the rewritable nonvolatile memory module 406 may be a Multi Level Cell (MLC) NAND type flash memory module (i.e. a flash memory module capable of storing 2 bits of data in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.
FIGS. 5A and 5B are schematic diagrams illustrating an exemplary memory cell memory architecture and a physical erase unit according to the present exemplary embodiment.
Referring to fig. 5A, the memory state of each memory cell of the rewritable nonvolatile memory module 406 can be identified as "111", "110", "101", "100", "011", "010", "001" or "000" (as shown in fig. 5A), wherein the 1 st bit from the left is LSB, the 2 nd bit from the left is CSB and the 3 rd bit from the left is MSB. In addition, several memory cells arranged on the same word line may constitute 3 physical program cells, wherein the physical program cells composed of LSBs of the memory cells are referred to as lower physical program cells, the physical program cells composed of CSBs of the memory cells are referred to as middle physical program cells, and the physical program cells composed of MSBs of the memory cells are referred to as upper physical program cells.
Referring to FIG. 5B, a physical erase unit is formed by a plurality of physical program unit groups, wherein each physical program unit group includes a lower physical program unit, a middle physical program unit and an upper physical program unit formed by a plurality of memory cells arranged on the same word line. For example, in the physical erase unit, the 0 th physical program unit belonging to the lower physical program unit, the 1 st physical program unit belonging to the middle physical program unit, and the 2 nd physical program unit belonging to the upper physical program unit are regarded as one physical program unit group. Similarly, the 3 rd, 4 th and 5 th physical programming units are considered as a physical programming unit group, and other physical programming units are also divided into a plurality of physical programming unit groups according to the method.
FIG. 6A is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the invention.
Referring to FIG. 6A, the memory control circuit unit 404 includes a memory management circuit 702, a host interface 704, a memory interface 706, and an error checking and correcting circuit 708.
The memory management circuit 702 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 702 has a plurality of control commands, and the control commands are executed to perform writing, reading and erasing operations of data while the memory storage device 10 is in operation. The operation of the memory management circuit 702 or any of the circuit elements included in the memory control circuit unit 404 is described as follows, which is equivalent to describing the operation of the memory control circuit unit 404.
In the present exemplary embodiment, the control instructions of the memory management circuit 702 are implemented in firmware. For example, the memory management circuit 702 has a microprocessor unit (not shown) and a read-only memory (not shown), and the control instructions are burned into the read-only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading and erasing data.
In another example embodiment, the control instructions of the memory management circuit 702 may also be stored in program code form in a specific area of the rewritable non-volatile memory module 406 (e.g., a system area of the memory module dedicated to storing system data). In addition, the memory management circuit 702 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (boot code), and when the memory control circuit 404 is enabled, the microprocessor unit executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 702. Then, the microprocessor unit operates the control instructions to perform operations such as writing, reading and erasing of data.
Furthermore, in another example embodiment, the control instructions of the memory management circuit 702 may also be implemented in a hardware type. For example, the memory management circuit 702 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory cell management circuit, the memory write circuit, the memory read circuit, the memory erase circuit and the data processing circuit are electrically connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups thereof of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read instruction sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erase circuit is configured to issue an erase command sequence to the rewritable nonvolatile memory module 406 to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, read command sequence, and erase command sequence may each include one or more program codes or command codes and are used to instruct the rewritable nonvolatile memory module 406 to perform the corresponding write, read, erase, etc. In an example embodiment, the memory management circuitry 702 may also issue other types of sequences of instructions to the rewritable non-volatile memory module 406 to instruct the corresponding operations to be performed.
The host interface 704 is electrically connected to the memory management circuit 702 and is used for receiving and recognizing commands and data transmitted by the host system 11. That is, the instructions and data transmitted by the host system 11 are transmitted to the memory management circuit 702 through the host interface 704. In the present exemplary embodiment, host interface 704 is compliant with the SATA standard. However, it should be understood that the present invention is not limited thereto, and the host interface 704 may also be compatible with PATA standards, IEEE 1394 standards, PCI Express standards, USB standards, SD standards, UHS-I standards, UHS-II standards, MS standards, MMC standards, eMMC standards, UFS standards, CF standards, IDE standards, or other suitable data transfer standards.
The memory interface 706 is electrically connected to the memory management circuit 702 and is used to access the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format acceptable to the rewritable nonvolatile memory module 406 through the memory interface 706. Specifically, if the memory management circuit 702 is to access the rewritable nonvolatile memory module 406, the memory interface 706 transmits a corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence that indicates write data, a read instruction sequence that indicates read data, an erase instruction sequence that indicates erase data, and corresponding instruction sequences to indicate various memory operations (e.g., changing read voltage levels or performing garbage collection procedures, etc.). These sequences of instructions are, for example, generated by memory management circuitry 702 and transferred to rewritable non-volatile memory module 406 through memory interface 706. These instruction sequences may include one or more signals, or data, on a bus. Such signals or data may include instruction code or program code. For example, the read instruction sequence may include information such as a read identification code and a memory address.
The error checking and correcting circuit 708 is electrically connected to the memory management circuit 702 and is used for performing an error checking and correcting procedure to ensure the correctness of the data. Specifically, when the memory management circuit 702 receives a write command from the host system 11, the error checking and correcting circuit 708 generates a corresponding error correction code (error correcting code, ECC) and/or error checking code (error detecting code, EDC) for the data corresponding to the write command, and the memory management circuit 702 writes the data corresponding to the write command and the corresponding error correction code and/or error checking code into the rewritable nonvolatile memory module 406. Then, when the memory management circuit 702 reads data from the rewritable nonvolatile memory module 406, it reads the error correction code and/or the error check code corresponding to the data at the same time, and the error check and correction circuit 708 performs an error check and correction procedure on the read data according to the error correction code and/or the error check code.
In an exemplary embodiment, the memory control circuit unit 404 further includes a buffer memory 710 and a power management circuit 712.
The buffer memory 710 is electrically connected to the memory management circuit 702 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 712 is electrically connected to the memory management circuit 702 and is used for controlling the power of the memory storage device 10.
In the present exemplary embodiment, the error checking and correction circuit 708 may perform single-frame (single-frame) encoding for data stored in the same physical programming unit, or may perform multi-frame (multi-frame) encoding for data stored in multiple physical programming units. The single frame coding and the multi-frame coding can respectively adopt at least one of coding algorithms such as low density parity check correction codes (low density parity code, LDPC), BCH codes, convolutional codes (convolutional code) or turbo codes (turbo codes). Alternatively, in an exemplary embodiment, the multi-frame encoding may also employ a Reed-solomon codes (RS codes) algorithm or a exclusive-or (XOR) algorithm. In addition, in another exemplary embodiment, more encoding algorithms not listed above may be used, and will not be described here. Depending on the encoding algorithm employed, the error checking and correction circuit 708 may encode the data to be protected to generate a corresponding error correction code and/or error checking code. For convenience of explanation, the error correction codes and/or error check codes generated by encoding will be collectively referred to as encoded data hereinafter.
Fig. 6B is a schematic diagram of a multi-frame encoding according to an example embodiment of the invention.
Referring to fig. 6B, taking the example of encoding the data stored in the physical programming units 810 (0) to 810 (E) to generate the corresponding encoded data 820, at least a portion of the data stored in each of the physical programming units 810 (0) to 810 (E) can be regarded as a frame. In multi-frame encoding, the data in the physical programming units 810 (0) to 810 (E) is encoded based on the position of each bit (or bit group). For example bit b located at position 801 (1) 11 、b 21 、…、b p1 Will be encoded as bit b in encoded data 820 o1 Bit b located at position 801 (2) 12 、b 22 、…、b p2 Will be encoded as bit b in encoded data 820 o2 The method comprises the steps of carrying out a first treatment on the surface of the Similarly, bit b at position 801 (r) 1r 、b 2r 、…、b pr Will be encoded as bit b in encoded data 820 or . The data read from the physical programming units 810 (0) to 810 (E) can then be decoded based on the encoded data 820 in an attempt to correct errors that may exist in the read data.
In addition, in another example embodiment of fig. 6B, the data used to generate the encoded data 820 may also include redundancy bits (redundancy bits) corresponding to data bits (data bits) in the data stored by the physical programming units 810 (0) to 810 (E). Taking the data stored in the physical programming unit 810 (0) as an example, the redundancy bits are generated by, for example, single frame encoding the data bits stored in the physical programming unit 810 (0). In the present exemplary embodiment, it is assumed that when reading the data in the physical programming unit 810 (0), the data read from the physical programming unit 810 (0) can be decoded by using the redundancy bits (e.g., the encoded data encoded by a single frame) in the physical programming unit 810 (0) for error detection and correction. However, when decoding using the redundant bits in the physical programmer 810 (0) fails (e.g., the number of erroneous bits of the data stored in the physical programmer 810 (0) after decoding is greater than a threshold), a re-Read (Retry-Read) mechanism may be used to attempt to Read the correct data from the physical programmer 810 (0). Details of the re-reading mechanism are described later. When the correct data cannot be Read from the physical programming unit 810 (0) by the re-Read mechanism, the encoded data 820 and the data of the physical programming units 810 (1) to 810 (E) can be Read, and decoding is performed according to the encoded data 820 and the data of the physical programming units 810 (1) to 810 (E), so as to attempt to correct errors in the data stored in the physical programming unit 810 (0). That is, in the present exemplary embodiment, when decoding of encoded data generated using single frame encoding fails and reading of encoded data generated using a re-Read (Retry-Read) mechanism fails, decoding is performed using encoded data generated using multi-frame encoding.
FIGS. 7 and 8 are schematic diagrams illustrating an example of managing physically erased cells according to an example embodiment.
Referring to FIG. 7, the rewritable nonvolatile memory module 406 has physical erase units 510 (0) to 510 (N), and the memory management circuit 702 logically divides (partition) the data area 502, the idle area 504, the temporary storage area 506 and the replacement area 508.
The physical erase units logically belonging to the data area 502 and the spare area 504 are used to store data from the host system 11. Specifically, the physical erased cells of the data area 502 are considered to be physical erased cells of the stored data, and the physical erased cells of the spare area 504 are used to replace the physical erased cells of the data area 502. That is, when a write command and data to be written are received from the host system 11, the memory management circuit 702 extracts the physical erase unit from the spare area 504 and writes the data into the extracted physical erase unit to replace the physical erase unit of the data area 502.
The physical erase unit logically belonging to the temporary storage area 506 is used for recording system data. For example, the system data includes a logical-to-physical address mapping table, a manufacturer and model number for the rewritable nonvolatile memory module, a physical erase unit count for the rewritable nonvolatile memory module, a physical program unit count for each physical erase unit, and so on.
The physically erased cells logically belonging to the replacement area 508 are used for the replacement process of the bad physically erased cells to replace the damaged physically erased cells. Specifically, if the replacement area 508 still has normal physical erased cells and the physical erased cells of the data area 502 are damaged, the memory management circuit 302 extracts the normal physical erased cells from the replacement area 508 to replace the damaged physical erased cells.
In particular, the number of physically erased cells in the data area 502, the spare area 504, the temporary area 506, and the replacement area 508 may vary according to different memory specifications. In addition, it should be understood that during operation of the memory device 10, the grouping relationship of physical erase units associated with the data area 502, the spare area 504, the register area 506, and the replacement area 508 dynamically changes. For example, when a physically erased cell in the spare area 504 is damaged and replaced by a physically erased cell of the replacement area 508, the physically erased cell of the replacement area 508 is associated with the spare area 504.
Referring to FIG. 8, the memory management circuit 702 configures logical units LBA (0) -LBA (H) to map physical erased cells of the data area 502, wherein each logical unit has a plurality of logical sub-units to map physical programmed cells of corresponding physical erased cells. When the host system 11 wants to write data to the logic unit or update the data stored in the logic unit, the memory management circuit 702 extracts a physical erase unit from the spare area 504 to write data, so as to replace the physical erase unit of the data area 502. In the present example embodiment, the logical subunits may be logical pages or logical sectors.
In order to identify the physical erased cell in which the data for each logical unit is stored, in this example embodiment, the memory management circuit 702 records a mapping between logical units and physical erased cells. When the host system 11 wants to access data in a logical subunit, the memory management circuit 702 identifies the logical unit to which the logical subunit belongs, and accesses data in the physical erase unit mapped by the logical unit. For example, in the exemplary embodiment, the memory management circuit 702 stores a logical-to-physical address mapping table in the rewritable nonvolatile memory module 406 to record the physical erase unit mapped by each logical unit, and the memory management circuit 702 loads the logical-to-physical address mapping table into the buffer memory 710 for maintenance when data is to be accessed.
It should be noted that, since the capacity of the buffer memory 710 is limited, the memory management circuit 702 groups the logical units LBA (0) to LBA (H) into a plurality of logical areas LZ (0) to LZ (M), and configures a logical-to-physical address mapping table for each logical area. In particular, when the memory management circuit 702 wants to update the mapping of a logical unit, the logical-to-physical address mapping table corresponding to the logical area to which the logical unit belongs is loaded into the buffer memory 710 to be updated.
It should be noted that the memory management circuit 702 may write to the rewritable nonvolatile memory module 406 using a single page programming mode or a multi-page programming mode.
FIG. 9 is a schematic diagram illustrating writing data to a rewritable non-volatile memory module using a single page programming mode, according to an example.
Referring to fig. 9, when the memory storage device 10 receives a write command (also referred to as a first write command) from the host system 11, which indicates that the update data is stored in the 0 th to 257 th logical subunits of the logical unit LBA (0), the memory management circuit 702 extracts 3 physical erase units 510 (f+1), 510 (f+2), 510 (f+3) from the spare area 504 as a plurality of active physical erase units corresponding to the first write command, respectively. Assuming that the memory management circuit 702 performs writing using the single page programming mode, the memory management circuit 702 writes the data of the first writing command from the buffer memory 710 to the physical programming units of the physical erasing units 510 (f+1), 510 (f+2) and 510 (f+3) according to the first command sequence. Here, since the physical program units of the physical erase units 510 (f+1), 510 (f+2) and 510 (f+3) are programmed in the single page program mode, the memory cells of the physical program units constituting the physical erase units 510 (f+1), 510 (f+2) and 510 (f+3) are programmed to store 1 bit of data as described above. That is, in the single page programming mode, the lower physical program units of the physical erase units 510 (f+1), 510 (f+2) and 510 (f+3) are used to write data and the middle physical program units and the upper physical program units of the physical erase units 510 (f+1), 510 (f+2) and 510 (f+3) are not used to write data.
In detail, as shown in FIG. 9, the memory management circuit 702 sequentially writes the data of the 0 th to 257 th logical subunits to be stored in the logical unit LBA (0) to the lower physical programming units of the physical erase units 510 (F+1), 510 (F+2) and 510 (F+3). That is, the memory management circuit 702 uses the single page programming mode to write the data corresponding to the first write command from the buffer memory 710 into the lower physical program units of the physical erase units 510 (f+1), 510 (f+2) and 510 (f+3) in the rewritable nonvolatile memory module 406, and the middle physical program units and the upper physical program units of the physical erase units 510 (f+1), 510 (f+2) and 510 (f+3) are not used for writing data.
After writing the data corresponding to the first write command from the buffer memory 710 to the next physical program units of the physical erase units 510 (f+1), 510 (f+2) and 510 (f+3) in the rewritable nonvolatile memory module 406 using the single page program mode, the memory management circuit 702 associates the physical erase units 510 (f+1), 510 (f+2) and 510 (f+3) to the data area 502, and returns the write completion information to the host system 11 in response to the first write command issued by the host system 11.
FIG. 10 is a schematic diagram illustrating writing data to a rewritable non-volatile memory module using a multi-page programming mode, according to an example.
Assuming that the first write command indicates to store data to logical subunits 0-257 of logical unit LBA (0), the memory management circuit 702 first temporarily stores the data of the first write command into the buffer memory 710. Thereafter, referring to FIG. 10, the memory management circuit 702 can extract 1 physical erase unit 510 (F+4) from the idle region 504 as an active physical erase unit corresponding to the first write command. Assuming that the memory management circuit 702 performs writing using the multi-page programming mode, the memory management circuit 702 writes the data of the first write command from the buffer memory 710 to the physical programming unit of the physical erase unit 510 (f+4) according to the first command sequence. Here, since the physical erase unit 510 (f+4) is programmed in the multi-page programming mode, the memory cells of the physical program units constituting the physical erase unit 510 (f+4) are programmed to store a plurality of bits of data as described above. That is, in the multi-page program mode, the lower physical program unit, the middle physical program unit, and the upper physical program unit of the physical erase unit 510 (f+4) are used to write data.
In detail, as shown in fig. 10, the memory management circuit 702 sequentially writes the data of the 0 th to 257 th logical sub-units to be stored in the logical unit LBA (0) into the lower physical program unit, the middle physical program unit and the upper physical program unit of the physical erase unit 510 (f+4). That is, the memory management circuit 702 uses the multi-page programming mode to write the data corresponding to the first write command from the buffer memory 710 to the lower physical programming unit, the middle physical programming unit and the upper physical programming unit of the physical erase unit 510 (f+4) in the rewritable nonvolatile memory module 406.
After the data corresponding to the first write command is written from the buffer memory 710 to the lower, middle and upper physical program units of the physical erase unit 510 (f+4) in the rewritable nonvolatile memory module 406 using the multi-page program mode, the memory management circuit 702 associates the physical erase unit 510 (f+4) to the data area 502 and returns the write completion information to the host system 11 in response to the first write command issued by the host system 11.
It should be noted that, in one embodiment, it is assumed that the memory management circuit 702 is preset to write the data of a write command into the rewritable nonvolatile memory module 406 using the multi-page programming mode. However, the reliability of data written using the multi-page programming mode is lower than that of the single-page programming mode. In other words, the data written using the multi-page programming mode may fail to be written, resulting in the written data having uncorrectable error bits. Therefore, in the conventional method, when the memory management circuit 702 is preset to write the data of the write command to the rewritable nonvolatile memory module 406 using the multi-page programming mode, the memory management circuit 702 also writes all the data corresponding to the write command to at least one physical erasing unit in the rewritable nonvolatile memory module 406 using the single-page programming mode. The memory management circuit 702 then verifies all the data of the write command written using the multi-page programming mode to determine if a write failure occurred during writing to one (or some) of the physical programming unit(s). Assuming that a physical programmer is writing data using a multi-page programming scheme, the memory management circuit 702 performs data recovery using data previously written using a single-page programming scheme when the physical programmer has uncorrectable error bits (i.e., write failure). That is, in the foregoing example, the single page programming mode is used for data restoration and backup.
It should be noted that the process of backing up data using the single page programming mode can be time consuming as well as space in the rewritable non-volatile memory module 406. In addition, the memory management circuit 702 also takes a lot of time to verify all the data of the write command written using the multi-page programming mode to determine whether a write failure occurred when writing to one (or some) of the physical programming units.
Therefore, the present invention proposes a data writing method, when the memory management circuit 702 is preset to write in the multi-page programming mode, only a portion of the data needs to be backed up by the memory management circuit 702, and only a portion of the data in the physical programming unit needs to be verified in the process of verifying the data written in the multi-page programming mode, thereby reducing the time required for writing and verifying the data.
In more detail, fig. 11 to 12 are schematic diagrams illustrating an example of a data writing method according to an example of the present invention.
Assume that the memory management circuit 702 receives at least one write command issued by the host system 11, the write command being used to instruct writing of a plurality of data (e.g., data D0-D257) into the rewritable nonvolatile memory module 406. Memory management circuit 702 receives data D0-D257 corresponding to the write instruction. The memory management circuit 702 first temporarily stores the data D0-D257 into the buffer memory 710. Thereafter, referring to FIG. 11, the memory management circuit 702 can extract 1 physical erase unit 510 (F+5) from the idle region 504 as an active physical erase unit corresponding to the write command. Assuming that the memory management circuit 702 is preset to write using the multi-page programming mode, the memory management circuit 702 writes the data D0-D257 from the buffer memory 710 into the 0-257 physical programming units of the physical erase unit 510 (F+5). In detail, as shown in FIG. 11, the memory management circuit 702 sequentially writes the data D0-D255 into the lower physical program unit, the middle physical program unit and the upper physical program unit of the physical erase unit 510 (F+5).
In particular, in the embodiment of the present invention, the memory management circuit 702 may, for example, store a look-up table in advance to know which physical programming units on the word lines of the rewritable nonvolatile memory module 406 have a higher probability of write failure (e.g., the probability of write failure is higher than that of other physical programming units). In more detail, due to the process relationship, the physical programming units formed by the memory cells on some word lines have a high probability of writing failure, and the manufacturer of the rewritable nonvolatile memory module 406 can know the positions of the word lines (or the physical programming units) which are prone to writing failure in an experimental manner before the rewritable nonvolatile memory module 406 leaves the factory, so as to generate the lookup table.
Herein, the physical programming unit having a probability of writing failure higher than the threshold value is referred to as a "first physical programming unit". Assume that the rewritable nonvolatile memory module 406 includes n word lines in total, the n word lines are arranged in a sequence, and a plurality of memory cells on the same word line among the n word lines form at least one of the plurality of physical programming units. It is assumed that the plurality of memory cells (also referred to as first memory cells) in the rewritable nonvolatile memory module 406 form the aforementioned first physical programming unit, and the first memory cell bit is located on at least one word line (also referred to as first word line) of the aforementioned n word lines, where n is a positive integer greater than zero. In particular, in one embodiment, the first word line is located in the 0 th to i th word lines, the j th to k th word lines, or the h th to n-1 th word lines of the n word lines. Wherein i, j, k, h are each positive integers greater than zero and discontinuous with each other. i is less than j, j is less than k, k is less than h, and h is less than n.
For example, assume that the rewritable nonvolatile memory module 406 includes 96 word lines in total, and the first word line is located in the 0 th to 6 th word lines, 46 th to 49 th word lines, or 89 th to 95 th word lines of the 96 word lines. That is, in the present embodiment, i has a value of 6,j, k has a value of 49, h has a value of 89, and n has a value of 96. In other words, in the present embodiment, the probability of the write failure of the first word line of the n word lines, the middle word line of the n word lines, and the tail word line of the n word lines is higher than the threshold value.
Continuing with the example of FIG. 11, after sequentially writing the data D0-D257 into the lower physical program unit, the middle physical program unit, and the upper physical program unit of the physical erase unit 510 (F+5), the memory management circuit 702 assumes that the 3 rd to 5 th and 252 th physical program units of the physical erase unit 510 (F+5) belong to the first physical program unit (i.e., the probability of a write failure is higher than that of the other physical program units) according to the lookup table. The memory management circuit 702 extracts 1 physical erase unit 510 (f+6) from the spare area 504, and writes the data D3-D5, D252-D254 (also referred to as first data) from the buffer memory 710 into the 0, 3, 6, 9, 12, 15 physical program units (also referred to as second physical program units) of the physical erase unit 510 (f+6) using the single page program mode. It should be noted that the present invention is not limited to the amount of the first data. In one embodiment, the first data may be thirty percent of the plurality of data received from the host system 11 corresponding to the write command.
Next, the memory management circuit 702 verifies the data stored in the 3 rd to 5 th and 252 th to 254 th physical program units of the physical erase unit 510 (F+5) to determine whether there are uncorrectable error bits in the data.
Assuming that there are no uncorrectable error bits in the data stored in the 3 rd to 5 th and 252 th to 254 th physical program units of the physical erase unit 510 (f+5), the memory management circuit 702 marks the data stored in the 0 th, 3 rd, 6 th, 9 th, 12 th and 15 th physical program units of the physical erase unit 510 (f+6) as invalid.
Assuming that the data D3-D5 (also referred to as the second data) stored in the 3-5 th and 252-254 th physical program units of the physical erase unit 510 (F+5) has uncorrectable error bits, referring to FIG. 11 and FIG. 12, in one embodiment, the memory management circuit 702 copies the data D3-D5 from the 0-3 th and 6 th physical program units of the physical erase unit 510 (F+6) and copies the data D0-D2 and the data D6-D257 from the 0-2 th and 6-257 th physical program units of the physical erase unit 510 (F+5). The memory management circuit 702 sequentially writes the data D0-D2 copied from the 0 th to 2 nd physical program units of the physical erase unit 510 (F+5), the data D3-D5 copied from the 0 th, 3 rd and 6 th physical program units of the physical erase unit 510 (F+6), and the data D6-D257 copied from the 6 th to 257 th physical program units of the physical erase unit 510 (F+5) into the 0 th to 257 th physical program units of the physical erase unit 510 (F+7) (also referred to as the third physical erase unit) using the multi-page program mode.
In addition, assuming that the data D3-D5 in the 3 rd to 5 th physical program units of the physical erase unit 510 (f+5) has uncorrectable error bits, referring to fig. 11 and 12, in another embodiment, the memory management circuit 702 may copy the data D3-D5 and the data D252-D254 from the 0 th, 3 rd, 6 th, 9 th, 12 th, 15 th physical program units of the physical erase unit 510 (f+6) and copy the data D0-D2, the data D6-D251 and the data D55-D257 from the 0 th to 2 th, 6 th to 251 th, 255 th to 257 th physical program units of the physical erase unit 510 (f+5). Thereafter, the memory management circuit 702 sequentially writes the data D0-D2 copied from the 0-2 physical program units of the physical erase unit 510 (F+5), the data D3-D5 copied from the 0, 3, 6 physical program units of the physical erase unit 510 (F+6), the data D6-D251 copied from the 6-251 physical program units of the physical erase unit 510 (F+5), the data D252-D254 copied from the 9, 12, 15 physical program units of the physical erase unit 510 (F+6), and the data D255-D257 copied from the 255-257 physical program units of the physical erase unit 510 (F+5) into the 0-257 physical program units of the physical erase unit 510 (F+7) using the multi-page program mode.
It should be noted that the foregoing examples are described with respect to a plural-level memory cell (Trinary Level Cell, TLC) NAND flash memory module (i.e., a flash memory module capable of storing 3 bits of data in one memory cell). However, the present invention is not limited thereto, and in other embodiments, the data writing method of the present invention can be used for Multi Level Cell (MLC) NAND type flash memory modules, quad-Level Cell (QLC) NAND type flash memory modules, or other memory modules with the same characteristics.
Fig. 13 is a flowchart illustrating a data writing method according to an example of the present invention.
Referring to fig. 13, in step S1301, the memory management circuit 702 receives a plurality of data. In step S1303, the memory management circuit 702 writes the plurality of data to the first physical erase unit using the multi-page programming mode. In step S1305, the memory management circuit 702 writes the first data in the plurality of data to the second physical erase unit using the single page programming mode. The probability of the write failure of the first physical programming unit for storing the first data in the first physical erasing unit is higher than that of the write failure of the other physical programming units in the first physical erasing unit. After that, in step S1307, the memory management circuit 702 verifies the data stored in the first entity programming unit. When the verification is successful, in step S1309, the memory management circuit 702 marks the second physical program unit for storing the first data in the second physical erase unit as invalid. When the verification fails, in step S1311, the memory management circuit 702 writes the data in the second physical erase unit into the third physical erase unit according to the data in the other physical program units in the first physical erase unit and the data in the second physical erase unit.
In summary, the data writing method, the memory control circuit unit and the memory storage device of the present invention can be used for backing up only a portion of data when the programming mode is preset, and only verifying a portion of data in the physical programming unit during verifying the data written in the programming mode, thereby reducing the time required for writing and verifying the data.
Although the invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather may be modified or altered somewhat by persons skilled in the art without departing from the spirit and scope of the invention.

Claims (21)

1. A data writing method for a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of physical erase units, each physical erase unit of the plurality of physical erase units has a plurality of physical program units, the data writing method comprising:
receiving a plurality of data;
writing the plurality of data to a first physical erase unit of the plurality of physical erase units using a multi-page programming mode;
Writing at least one first data of the plurality of data into a second physical erase unit of the plurality of physical erase units using a single page programming mode;
verifying the plurality of data stored in the first physical erase unit; and
when verification fails, writing the at least one first data of the second physical erase unit and other data of the plurality of data of the first physical erase unit into a third physical erase unit of the plurality of physical erase units by using the multi-page programming mode according to the at least one first data of the second physical erase unit and the plurality of data of the first physical erase unit.
2. The data writing method according to claim 1, wherein
The probability of the write failure of at least one first physical programming unit used for storing the at least one first data in the first physical erasing unit is higher than that of the write failure of other physical programming units in the first physical erasing unit.
3. The data writing method according to claim 2, the method comprising:
validating data stored in the first physical programming unit;
When the data in the first physical programming unit does not have uncorrectable bits, marking at least one second physical programming unit in the second physical erasing unit for storing the at least one first data as invalid;
when the at least one first data in the first physical program unit has uncorrectable bits, writing the data in the other physical program units in the first physical erase unit and the data in the at least one second physical program unit in the second physical erase unit into the third physical erase unit by using the multi-page program mode.
4. The data writing method according to claim 1, wherein the at least one first data is thirty percent of the plurality of data.
5. The data writing method according to claim 2, wherein the rewritable nonvolatile memory module includes n word lines arranged in order, a plurality of memory cells on the same one of the n word lines forming at least one of the plurality of physical programming units, wherein
The first physical programming unit is formed by a plurality of first memory cells in the plurality of memory cells, and the plurality of first memory cells are located on at least one first word line in the n word lines, wherein n is a positive integer greater than zero.
6. The data writing method according to claim 5, wherein
The first word line is positioned in the 0 th to i th word lines, the j th to k th word lines or the h-n-1 th word lines of the n word lines,
wherein i, j, k, h are each positive integers greater than zero and discontinuous with each other,
where i is less than j, j is less than k, k is less than h, and h is less than n.
7. The data writing method according to claim 1, wherein the step of receiving the plurality of data includes:
receiving at least one writing instruction issued by a host system, wherein the writing instruction is used for indicating writing of the plurality of data into the rewritable nonvolatile memory module; and
the data are temporarily stored in a buffer memory.
8. A memory control circuit unit for controlling a rewritable nonvolatile memory module, the memory control circuit unit comprising:
the host interface is used for being electrically connected to a host system;
the memory interface is used for being electrically connected to the rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module is provided with a plurality of entity erasing units, and each entity erasing unit in the plurality of entity erasing units is provided with a plurality of entity programming units;
A memory management circuit electrically connected to the host interface and the memory interface,
wherein the memory management circuit is configured to receive a plurality of data,
wherein the memory management circuit is further configured to write the plurality of data to a first physically erased cell of the plurality of physically erased cells using a multi-page programming mode,
wherein the memory management circuit is further configured to write at least a first data of the plurality of data to a second physically erased cell of the plurality of physically erased cells using a single page programming mode,
wherein the memory management circuit is further configured to verify the plurality of data stored in the first physically erased cell,
when the verification fails, the memory management circuit is further configured to write other data of the at least one first data of the second physical erase unit and the plurality of data of the first physical erase unit to a third physical erase unit of the plurality of physical erase units using the multi-page programming mode according to the at least one first data of the second physical erase unit and the plurality of data of the first physical erase unit.
9. The memory control circuit unit of claim 8, wherein a probability of a write failure of at least one first physical program cell of the first physical erase cell for storing the at least one first data is higher than a probability of a write failure of other physical program cells of the first physical erase cell.
10. The memory control circuit unit of claim 9, wherein
The memory management circuitry is also to verify data stored in the first physical programming unit,
when there is no uncorrectable bit in the data in the first physical program unit, the memory management circuit is further configured to mark at least one second physical program unit for storing the at least one first data in the second physical erase unit as invalid,
when the at least one first data in the first physical program unit has uncorrectable bits, the memory management circuit is further configured to write the data in the other physical program units in the first physical erase unit and the data in the at least one second physical program unit in the second physical erase unit into the third physical erase unit using the multi-page program mode.
11. The memory control circuit unit of claim 8, wherein the amount of the at least one first data is thirty percent of the amount of the plurality of data.
12. The memory control circuit unit of claim 9, wherein the rewritable nonvolatile memory module includes n word lines arranged in a sequence, a plurality of memory cells on a same one of the n word lines forming at least one of the plurality of physical programming units, wherein
The first physical programming unit is formed by a plurality of first memory cells in the plurality of memory cells, and the plurality of first memory cells are located on at least one first word line in the n word lines, wherein n is a positive integer greater than zero.
13. The memory control circuit unit of claim 12, wherein
The first word line is positioned in the 0 th to i th word lines, the j th to k th word lines or the h-n-1 th word lines of the n word lines,
wherein i, j, k, h are each positive integers greater than zero and discontinuous with each other,
where i is less than j, j is less than k, k is less than h, and h is less than n.
14. The memory control circuit unit of claim 8, wherein in operation of receiving the plurality of data,
The memory management circuit is also configured to receive at least one write instruction issued by the host system, wherein the write instruction is configured to instruct writing the plurality of data to the rewritable non-volatile memory module,
the memory management circuit is also used for temporarily storing the data into a buffer memory.
15. A memory storage device, comprising:
the connection interface unit is used for being electrically connected to the host system;
a rewritable nonvolatile memory module, wherein the rewritable nonvolatile memory module has a plurality of physical erasing units, and each physical erasing unit in the plurality of physical erasing units has a plurality of physical programming units; and
a memory control circuit unit electrically connected to the connection interface unit and the rewritable nonvolatile memory module,
wherein the memory control circuit unit is used for receiving a plurality of data,
wherein the memory control circuit unit is further configured to write the plurality of data to a first physical erase unit of the plurality of physical erase units using a multi-page programming mode,
wherein the memory control circuit unit is further configured to write at least a first data of the plurality of data to a second physically erased cell of the plurality of physically erased cells using a single page programming mode,
Wherein the memory control circuit unit is further configured to verify the plurality of data stored in the first physical erase unit,
when the verification fails, the memory control circuit unit is further configured to write other data of the at least one first data of the second physical erase unit and the plurality of data of the first physical erase unit to a third physical erase unit of the plurality of physical erase units using the multi-page programming mode according to the at least one first data of the second physical erase unit and the plurality of data of the first physical erase unit.
16. The memory storage device of claim 15, wherein a probability of a write failure of at least one first physical program cell of the first physical erase cell for storing the at least one first data is higher than a probability of a write failure of other physical program cells of the first physical erase cell.
17. The memory storage device of claim 16, wherein
The memory control circuit unit is also configured to verify data stored in the first physical programming unit,
when there is no uncorrectable bit in the data in the first physical program unit, the memory control circuit unit is further configured to mark at least one second physical program unit for storing the at least one first data in the second physical erase unit as invalid,
When the at least one first data in the first physical program unit has uncorrectable bits, the memory control circuit unit is further configured to write the data in the other physical program units in the first physical erase unit and the data in the at least one second physical program unit in the second physical erase unit into the third physical erase unit using the multi-page program mode.
18. The memory storage device of claim 15, wherein the amount of the at least one first data is thirty percent of the amount of the plurality of data.
19. The memory storage device of claim 16, wherein the rewritable nonvolatile memory module comprises n word lines arranged in sequence, a plurality of memory cells on a same one of the n word lines forming at least one of the plurality of physical programming units, wherein
The first physical programming unit is formed by a plurality of first memory cells in the plurality of memory cells, and the plurality of first memory cells are located on at least one first word line in the n word lines, wherein n is a positive integer greater than zero.
20. The memory storage device of claim 19, wherein
The first word line is positioned in the 0 th to i th word lines, the j th to k th word lines or the h-n-1 th word lines of the n word lines,
wherein i, j, k, h are each positive integers greater than zero and discontinuous with each other,
where i is less than j, j is less than k, k is less than h, and h is less than n.
21. The memory storage device of claim 15, wherein in operation of receiving the plurality of data,
the memory control circuit unit is also used for receiving at least one writing instruction issued by the host system, wherein the writing instruction is used for indicating the writing of the plurality of data to the rewritable nonvolatile memory module,
the memory control circuit unit is also used for temporarily storing the data into a buffer memory.
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