CN112018073B

CN112018073B - Semiconductor structure and preparation method thereof

Info

Publication number: CN112018073B
Application number: CN202011106407.4A
Authority: CN
Inventors: 张国伟; 周儒领; 吴佳特
Original assignee: Jingxincheng Beijing Technology Co Ltd
Current assignee: Jingxincheng Beijing Technology Co Ltd
Priority date: 2020-10-16
Filing date: 2020-10-16
Publication date: 2021-04-09
Anticipated expiration: 2040-10-16
Also published as: CN112018073A

Abstract

The invention discloses a semiconductor structure and a preparation method thereof, wherein the semiconductor structure comprises: a substrate; the conducting wire layer is positioned on the substrate; the dielectric layer is positioned on the wire layer; the groove is positioned in the dielectric layer, the bottom end of the groove is connected with the wire layer, and the side wall of the groove has an inclination angle; the barrier layer is positioned on the dielectric layer and the wire layer at the bottom end of the groove; the metal layer is positioned in the groove and on the barrier layer; a plurality of protective layers on the metal layer; a via hole in the plurality of protective layers. The invention can effectively improve the condition that impurities are left on the side wall of the through hole, thereby effectively reducing the damage to the probe when the wafer is electrically tested.

Description

Semiconductor structure and preparation method thereof

Technical Field

The invention relates to the technical field of semiconductors, in particular to a semiconductor structure and a preparation method thereof.

Background

At present, in a redistribution layer structure in the prior art, after a trench is formed, a metal layer is often deposited into the trench, but after the metal layer is deposited, a notch, that is, a pore described herein, exists at an opening at the top end of the trench, so that, on this basis, other semiconductor layers are continuously deposited, and when a through hole for a probe to be inserted during a wafer electrical test (WAT) is formed, impurities remain on a sidewall of the through hole, and the remaining impurities damage a tip of the probe used for the wafer electrical test (WAT), thereby affecting the life of the probe. The residue of impurities can also lead to poor contacts during subsequent packaging processes.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, the present invention provides a semiconductor structure and a method for manufacturing the same, wherein a thicker metal material, such as an aluminum material, is filled in a trench during trench filling, so that a vertical distance from a bottom end of a hole to a barrier layer at a bottom of the trench is greater than a thickness of a dielectric layer, and thus, after planarization processing, an opening at a top end of the trench is a horizontal structure, which is beneficial to subsequently forming a through hole with a relatively small right angle or a relatively small gradient, and in an etching process step, a situation that impurities remain on a sidewall of the through hole is effectively improved.

To achieve the above and other objects, the present invention provides a semiconductor structure comprising:

a substrate;

the conducting wire layer is positioned on the substrate;

the dielectric layer is positioned on the wire layer;

the groove is positioned in the dielectric layer, the bottom end of the groove is connected with the wire layer, and the side wall of the groove has an inclination angle;

the barrier layer is positioned on the dielectric layer and the wire layer at the bottom end of the groove;

the metal layer is positioned in the groove and on the barrier layer;

a plurality of protective layers on the metal layer;

a through hole in the plurality of protective layers;

the bottom of the through hole is connected with the metal layer, and the diameter of the through hole is larger than the caliber of the opening at the top end of the groove;

the metal layer comprises a metal filling layer and a metal additional layer, the metal filling layer is located in the groove, and the metal additional layer is located on the barrier layer and the metal filling layer at the groove.

In one embodiment, the substrate is a wafer or other semiconductor structure including devices or circuits.

In one embodiment, the dielectric layer includes:

the anti-diffusion layer is positioned on the wire layer; and

and the silicon oxide layer is positioned on the diffusion preventing layer.

In one embodiment, the thickness of the silicon oxide layer is 800-2000 nm. The thickness of the anti-diffusion layer is 10-25 nanometers.

In one embodiment, the material of the diffusion preventing layer is silicon carbonitride or a phosphorus silicon compound.

In one embodiment, the plurality of protective layers includes at least:

a first protective layer on the metal layer;

a second protective layer on the first protective layer; and

and the third protective layer is positioned on the second protective layer.

In an embodiment, the first protection layer is made of titanium nitride, the second protection layer is made of silicon dioxide, and the third protection layer is made of silicon nitride. The first protective layer is used for protecting the metal layer.

In one embodiment, the first protective layer has a thickness of 5-10 nm. The thickness of the second protective layer is 200-500 nm. The thickness of the third protective layer is 200-500 nm.

In an embodiment, the material of the metal additional layer is the same as the material of the metal filling layer, and the thickness of the metal additional layer is 1000-1450 nm.

In one embodiment, the conductive line layer is a copper conductive line layer.

In one embodiment, the metal layer is made of aluminum or tungsten.

The invention also aims to provide a preparation method of the semiconductor structure, which at least comprises the following steps:

providing a substrate;

forming a conducting wire layer on the substrate;

forming a dielectric layer on the conductor layer;

forming a groove in the dielectric layer, wherein the bottom end of the groove is connected with the wire layer, and the side wall of the groove has an inclination angle;

forming a barrier layer on the dielectric layer and the conductor layer at the bottom end of the groove;

forming a metal layer in the trench and on the barrier layer;

forming a plurality of protective layers on the metal layer;

forming through holes in the plurality of protective layers;

In one embodiment, the step of forming the metal layer in the trench and on the barrier layer includes:

filling the groove with metal filler to form a groove filling layer, wherein the groove filling layer is provided with a pore;

with the barrier layer as a stop layer, carrying out planarization treatment on the groove filling layer to obtain the metal filling layer;

forming an additional layer of metal on the barrier layer and the metal fill layer at the trench;

wherein, the difference between the vertical distance from the bottom end of the pore to the barrier layer at the bottom of the groove and the thickness of the dielectric layer is 20-40% of the thickness of the dielectric layer.

In the invention, a thicker metal material, such as an aluminum material, is filled in the groove to form the groove filling layer, so that the vertical distance from the bottom of the hole to the barrier layer at the bottom of the groove is greater than the thickness of the dielectric layer, and the opening at the top of the groove is in a horizontal structure after the groove filling layer is flattened, thereby being beneficial to the subsequent formation of the through hole with a slower right angle or gradient. When Wafer Acceptance Test (WAT) is performed, the semiconductor structure of the invention can greatly reduce the influence on the probe, thereby prolonging the service life of the probe. In the subsequent packaging process, the occurrence of poor contact phenomenon can be greatly reduced. The semiconductor structure is provided with the metal filling layer positioned in the groove and the metal additional layer, so that the through hole is formed in the subsequent etching process. The through hole is for example a through hole with a larger caliber, so that the etching and the detection are convenient. The invention can effectively improve the condition that the probe is damaged and further improve the measurement precision. The invention has the advantages of easily understood principle, compact structure and the like.

Drawings

FIG. 1: in an embodiment of the present invention, the substrate, the wire layer, and the dielectric layer are schematically configured;

FIG. 2: a schematic view of the trench in one embodiment of the present invention;

FIG. 3: a schematic view of the barrier layer in one embodiment of the invention;

FIG. 4: a schematic view of the trench filling layer in an embodiment of the present invention;

FIG. 5: a schematic view of the metal filling layer in an embodiment of the invention;

FIG. 6: a schematic diagram of the metal additional layer in an embodiment of the invention;

FIG. 7: a schematic diagram of the plurality of protective layers in one embodiment of the invention;

FIG. 8: a schematic diagram after forming the through hole in an embodiment of the invention;

FIG. 9: the flow chart of the preparation method of the semiconductor structure in one embodiment of the invention is schematic.

Description of the symbols

100. A substrate; 101. a conductor layer; 102. a dielectric layer; 103. a trench; 104. a barrier layer; 105. a metal layer; 106. a plurality of protective layers; 107. a through hole; 108. a trench filling layer; 1021. a diffusion preventing layer; 1022. a silicon oxide layer; 1051. a metal filling layer; 1052. an additional layer of metal; 1061. a first protective layer; 1062. a second protective layer; 1063. a third protective layer; A. and (4) pores.

Detailed Description

The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.

It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.

In the present invention, it should be noted that, as the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, their indicated orientations or positional relationships are based on the orientations or positional relationships shown in the drawings, and are only for convenience of describing the present application and simplifying the description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first" and "second," if any, are used for descriptive and distinguishing purposes only and are not to be construed as indicating or implying relative importance.

In the invention, when the groove is filled, a thicker layer of metal material, such as aluminum material, is filled to form the groove filling layer, so that the vertical distance from the bottom end of the hole to the barrier layer at the bottom of the groove is greater than the thickness of the dielectric layer, and the opening at the top end of the groove is in a horizontal structure after the groove filling layer is subjected to planarization treatment, thereby being beneficial to the subsequent formation of the through hole with a right angle or a slower gradient.

Referring to fig. 1 to 8, the present invention provides a semiconductor structure including, but not limited to, a substrate 100, a conductive layer 101, a dielectric layer 102, a trench 103, a barrier layer 104, a metal layer 105, a plurality of passivation layers 106 and a via 107. When Wafer Acceptance Test (WAT) is performed, the semiconductor structure of the invention can greatly reduce the influence on the probe.

Referring to fig. 1, in one embodiment, the substrate 100 is a wafer or other semiconductor structure including devices or circuits. The wire layer 101 is located on the substrate 100, and the wire layer 101 is, for example, a copper wire layer.

Referring to fig. 1 and 2, in an embodiment, the dielectric layer 102 includes, but is not limited to, a diffusion-preventing layer 1021 and a silicon oxide layer 1022, the diffusion-preventing layer 1021 is located on the wire layer 101, and the silicon oxide layer 1022 is located on the diffusion-preventing layer 1021. The diffusion preventing layer 1021 is located on the wire layer 101, and the material of the diffusion preventing layer 1021 is, for example, silicon carbonitride or a phosphorus silicon compound. The thickness of the diffusion barrier 1021 is, for example, 10 nm to 25 nm, specifically, for example, 10 nm, 15 nm, 20 nm, or 25 nm, or other thicknesses suitable for the diffusion barrier 1021. The diffusion preventing layer 1021 prevents the wire layer 101 from diffusing. The silicon oxide layer 1022 is located on the diffusion barrier 1021, and the thickness of the silicon oxide layer 1022 is, for example, 800-2000 nm, specifically, 800 nm, 900 nm, 1000 nm, 1200 nm, 1500 nm, 1800 nm, 2000 nm, or other thicknesses suitable for the silicon oxide layer 1022. And etching the diffusion preventing layer 1021 and the silicon oxide layer 1022 to form the trench 103. The trench 103 is located in the dielectric layer 102, specifically, the trench 103 is located on the diffusion barrier 1021 and the silicon oxide layer 1022, a top end of the trench 103 is open, a bottom end of the trench 103 is connected to the wire layer 101, and a sidewall of the trench 103 has an inclined angle.

Referring to fig. 1 to 3, in an embodiment, the barrier layer 104 is located on the dielectric layer 102 and the wiring layer 101 at the bottom of the trench 103. Specifically, the barrier layer 104 covers the dielectric layer 102, the inner wall and the bottom of the trench 103. The barrier layer 104 functions to prevent diffusion of atoms, and the thickness of the barrier layer 104 is, for example, 30 nm to 60 nm, specifically, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, or other thicknesses suitable for the barrier layer 104. The material of the barrier layer 104 is tantalum nitride, for example.

Referring to fig. 1 to 7, in one embodiment, the metal layer 105 is located in the trench 103 and on the barrier layer 104. The metal layer 105 includes, but is not limited to, a metal fill layer 1051 and an additional layer of metal 1052, the metal fill layer 1051 is located within the trench 103, the additional layer of metal 1052 is located on the barrier layer 104 and at the metal fill layer 1051. The material of the additional metal layer 1052 is the same as that of the metal filling layer 1051, for example. The thickness of the additional metal layer 1052 is, for example, 1000 nm 1450 nm, specifically, 1000 nm, 1050 nm, 1100 nm, 1150 nm, 1200 nm, 1250 nm, 1300 nm, 1350 nm, 1400 nm, 1450 nm, or other suitable thicknesses for the additional metal layer 1052. The metal layer 105 is made of, for example, aluminum or tungsten, i.e., the metal filling layer 1051 and the additional metal layer 1052 are made of aluminum or tungsten.

Referring to fig. 1 to 7, in an embodiment, the plurality of protection layers 106 include, but are not limited to, a first protection layer 1061, a second protection layer 1062, and a third protection layer 1063. The first protection layer 1061 is located on the metal layer 105, the second protection layer 1062 is located on the first protection layer 1061, and the third protection layer 1062 is located on the second protection layer 1062. The first protection layer 1061 is made of, for example, titanium nitride, the second protection layer 1062 is made of, for example, silicon dioxide, and the third protection layer 1063 is made of, for example, silicon nitride. The first protection layer 1061 is used to protect the metal layer 105, and in particular, the first protection layer 1061 is located on the additional metal layer 1052. The thickness of the first protection layer 1061 is, for example, 5 to 10 nm, specifically, for example, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, or other thicknesses suitable for the first protection layer 1062. The thickness of the second protection layer 1062 is, for example, 200 nm, 500 nm, specifically, 200 nm, 300 nm, 400 nm, 500 nm, or other thicknesses suitable for the first protection layer 1061. The thickness of the third protection layer 1063 is, for example, 200 nm, 500 nm, specifically, 200 nm, 300 nm, 400 nm, 500 nm, or other thicknesses suitable for the third protection layer 1063. The second protection layer 1062 and the third protection layer 1063 are passivation protection layers of the whole chip, and can isolate oxygen and water vapor.

Referring to fig. 1 to 8, in an embodiment, the via 107 is located in the protective layers 106, and the via 107 includes a plurality of trenches 103, for example. The top end of the through hole 107 is open, the bottom of the through hole 107 is connected with the metal layer 105, the bottom of the through hole 107 is of a horizontal structure, and the diameter of the through hole 107 is larger than the caliber of the top end opening of the groove 103.

Referring to fig. 9, in an embodiment, a method for fabricating a semiconductor structure includes the following steps:

s1, providing a substrate;

s2, forming a lead layer on the substrate;

s3, forming a dielectric layer on the conducting wire layer;

s4, forming a groove in the dielectric layer, wherein the bottom end of the groove is connected with the conducting wire layer, and the side wall of the groove has an inclination angle;

s5, forming a barrier layer on the dielectric layer and the wire layer at the bottom end of the groove;

s6, forming a metal layer in the groove and on the barrier layer;

s7, forming a plurality of protective layers on the metal layer;

and S8, forming through holes in the protective layers.

Specifically, in step S1, the substrate 100 is, for example, a wafer or a semiconductor structure including devices or circuits. The wire layer 101 is located on the substrate 100, and the wire layer 101 is, for example, a copper wire layer.

Specifically, in steps S2 to S4, the structures of the conductive line layer 101, the dielectric layer 102 and the trench 103 are described above, and are not repeated herein.

Specifically, in step S6, the step of forming the metal layer in the trench and on the barrier layer includes: filling the trench 103 with a metal filling material to form a trench filling layer 108, where the trench filling layer 108 has a void a, and with the barrier layer 104 as a stop layer, performing planarization treatment on the trench filling layer 108 to obtain the metal filling layer 1051, and forming an additional metal layer 1052 on the barrier layer 104 and the metal filling layer 1051 at the trench 103, where a difference between a vertical distance from a bottom end of the void a to the barrier layer 104 at the bottom of the trench 103 and a thickness of the dielectric layer 102 is 20% to 40% of the thickness of the dielectric layer 102, specifically, for example, 20%, 25%, 30%, 35% and 40%, and within this range, cost can be saved, and the subsequent formation of the via 107 is facilitated. For example, the vertical distance from the bottom of the void a to the barrier layer 104 at the bottom of the trench 103 is H2, and the thickness of the dielectric layer 102 is H1, so that 20% or less (H2-H1)/H1% or less than 40% is obtained.

Specifically, in step S6, after the trench filling layer 108 is planarized, the opening at the top end of the trench 103 is a straight or horizontal structure, i.e., the void a is removed, and then a metal additional layer 10652 is formed, so as to form the via 107 in the subsequent etching process.

Specifically, in step S8, a patterned photoresist layer is formed on the protection layers 106, and then the protection layers 106 are etched with the first protection layer 1061 as a stop layer, but finally, the metal additional layer 1052 is also partially etched, so that the bottom of the via 107 is connected to the metal additional layer 1052, that is, the bottom of the via 107 is the metal additional layer 1052. The diameter of the through hole 107 is larger than the caliber of the top opening of the groove 103. In the etching process, the through hole 107 has a small aspect ratio, which facilitates etching, so that no redundant impurities remain on two side walls of the through hole 107, and in addition, the through hole 107 has a large aperture, which facilitates subsequent wafer electrical test (WAT).

Specifically, in steps S3 to S7, the dielectric layer 102, the barrier layer 104, the metal additional layer 1052 and the plurality of protective layers 106 are formed by, for example, Atomic Layer Deposition (ALD), and in other embodiments, wet oxidation, Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), remote plasma CVD (rpcvd), plasma enhanced CVD (pecvd), metal organic CVD (mocvd), sputtering, plating, other suitable processes and/or combinations thereof may also be performed. Specifically, if a chemical vapor deposition method (CVD) is used, for example, one of Atmospheric Pressure Chemical Vapor Deposition (APCVD), Low Pressure Chemical Vapor Deposition (LPCVD), or Plasma Enhanced Chemical Vapor Deposition (PECVD) is used.

In summary, the present invention provides a semiconductor structure and a method for manufacturing the same, wherein the method for manufacturing the semiconductor structure includes filling a thicker layer of metal material, such as aluminum material, into the trench to form the trench filling layer, so that a vertical distance from a bottom end of the hole to the barrier layer at the bottom of the trench is greater than a thickness of the dielectric layer, and thus, after the trench filling layer is planarized, an opening at a top end of the trench is of a horizontal structure, which is beneficial to subsequently forming the through hole with a relatively slow right angle or gradient, and effectively improves a condition that impurities remain on a sidewall of the through hole in an etching process step. When Wafer Acceptance Test (WAT) is performed, the semiconductor structure of the invention can greatly reduce the influence on the probe, thereby prolonging the service life of the probe. In the subsequent packaging process, the occurrence of poor contact phenomenon can be greatly reduced. The semiconductor structure is provided with the metal filling layer positioned in the groove and the metal additional layer, so that the through hole is formed in the subsequent etching process. The through hole is for example a through hole with a larger caliber, so that the etching and the detection are convenient. The invention can effectively improve the condition that the probe is damaged and further improve the measurement precision. The invention has the advantages of easily understood principle, compact structure and the like.

The above description is only a preferred embodiment of the present application and a description of the applied technical principle, and it should be understood by those skilled in the art that the scope of the present invention related to the present application is not limited to the technical solution of the specific combination of the above technical features, and also covers other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the inventive concept, for example, the technical solutions formed by mutually replacing the above features with (but not limited to) technical features having similar functions disclosed in the present application.

Other technical features than those described in the specification are known to those skilled in the art, and are not described herein in detail in order to highlight the innovative features of the present invention.

Claims

1. A method for manufacturing a semiconductor structure, comprising at least the steps of:

providing a substrate;

forming a conducting wire layer on the substrate;

forming a dielectric layer on the conductor layer;

forming a metal layer in the trench and on the barrier layer;

forming a plurality of protective layers on the metal layer;

forming through holes in the plurality of protective layers;

the metal layer comprises a metal filling layer and a metal additional layer, the metal filling layer is positioned in the groove, and the metal additional layer is positioned on the barrier layer and the metal filling layer at the groove;

wherein the step of forming the metal layer in the trench and on the barrier layer comprises:

2. The method of claim 1, wherein the substrate is a wafer or other semiconductor structure containing devices or circuits.

3. The method of claim 1, wherein the dielectric layer comprises:

the anti-diffusion layer is positioned on the wire layer; and

and the silicon oxide layer is positioned on the diffusion preventing layer.

4. The method as claimed in claim 3, wherein the silicon oxide layer has a thickness of 800-2000 nm.

5. The method as claimed in claim 3, wherein the diffusion barrier layer is made of silicon carbonitride or a phosphorus-silicon compound.

6. The method of claim 1, wherein the plurality of protective layers comprises at least:

a first protective layer on the metal layer;

a second protective layer on the first protective layer; and

and the third protective layer is positioned on the second protective layer.

7. The method as claimed in claim 6, wherein the first passivation layer is made of titanium nitride,

the second protective layer is made of silicon dioxide, and the third protective layer is made of silicon nitride.

8. The method of claim 1, wherein the additional metal layer is made of the same material as the metal filling layer, and the thickness of the additional metal layer is 60-150 nm.