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CN112002715B - Array substrate and display panel - Google Patents

Array substrate and display panel Download PDF

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Publication number
CN112002715B
CN112002715B CN202010969690.7A CN202010969690A CN112002715B CN 112002715 B CN112002715 B CN 112002715B CN 202010969690 A CN202010969690 A CN 202010969690A CN 112002715 B CN112002715 B CN 112002715B
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Prior art keywords
layer
array substrate
pad
metal layer
spaced
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CN202010969690.7A
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CN112002715A (en
Inventor
唐维
曹志浩
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Wuhan China Star Optoelectronics Technology Co Ltd
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Wuhan China Star Optoelectronics Technology Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1339Gaskets; Spacers; Sealing of cells
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1345Conductors connecting electrodes to cell terminals
    • G02F1/13458Terminal pads

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Power Engineering (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Optics & Photonics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

The invention discloses an array substrate and a display panel. The array substrate is provided with a binding region, and the binding region comprises a substrate layer, a first metal layer, an interlayer insulating layer, a second metal layer, a passivation layer and a conducting layer which are sequentially stacked from bottom to top; the interlayer insulating layer is provided with a plurality of grooves and a plurality of through holes; the second metal layer is provided with a plurality of spaced wires and a wire changing part, and the spaced wires are arranged in the groove. According to the invention, the groove is formed in the interlayer insulating layer corresponding to the position of the spaced routing, and the spaced routing is arranged in the groove, so that the height difference between the spaced routing and the bonding pad for binding is increased, the phenomenon that conductive particles in the bound conductive adhesive are pressed on the spaced routing to be mutually connected to form a short circuit when the bound conductive adhesive is dislocated is avoided, and the product yield is improved.

Description

Array substrate and display panel
Technical Field
The application relates to the technical field of display, in particular to an array substrate and a display panel.
Background
In a manufacturing process of a Liquid Crystal Display (LCD), after an array substrate and a color filter substrate (T/C) are laminated and cut into a small-sized display screen, an integrated circuit chip (IC), a Flexible Printed Circuit (FPC), and the like need to be bound to the display screen for subsequent signal input or processing.
As shown in fig. 1 and 2, fig. 1 is a schematic structural diagram of an integrated circuit chip and a flexible circuit board bonded on a conventional array substrate. FIG. 2 is a cross-sectional view of the integrated circuit chip of FIG. 1 with bonding conductive. The array substrate 90 will form the bonding Pad 91 (Pad) for binding in the front stage substrate process, when binding the integrated circuit chip 92 or the flexible circuit board 93, firstly paste the conductive adhesive (ACF adhesive) 94 on the bonding Pad 91 of the array substrate 90, wherein the conductive adhesive 94 is composed of the insulating adhesive 941 and the non-connected conductive particles 942, then paste the Pad 921 on the integrated circuit chip 92 or the flexible circuit board 93 and the bonding Pad 91 on the array substrate by the alignment of the positioning mark, the paste is completed by the heating and pressing action, and the conductive particles 942 in the conductive adhesive 94 above the bonding Pad 91 are pressed and connected for conduction, thus realizing the binding and conduction connection. The conductive particles 942 are also present at other positions for binding, but the conductive particles 942 are not sufficiently pressed and are not connected to each other, so that the adjacent pads 91 are kept in an insulated state.
As shown in fig. 3, 4 and 5, fig. 3 isbase:Sub>A schematic plan view ofbase:Sub>A bonding region, fig. 4 isbase:Sub>A schematic plan view of an output pin bonding region 9102 of the integrated circuit chip in fig. 3, and fig. 5 isbase:Sub>A schematic cross-sectional view atbase:Sub>A-base:Sub>A in fig. 4. The bonding area of the conventional array substrate 90 is mainly divided into a bonding ic chip area 910 and a bonding flexible circuit board area 920, wherein the bonding ic chip area 910 is subdivided into an ic chip input pin bonding area 9101 adjacent to one side of the bonding flexible circuit board area 920 and an ic chip output pin bonding area 9102 far away from one side of the bonding flexible circuit board area 920. The array substrate 90 includes a buffer layer 911, an insulating layer 912, a first metal layer 913, an interlayer insulating layer 914, a second metal layer 915, a passivation layer 916, and a conductive layer 917 sequentially stacked from bottom to top, wherein a lower portion of the second metal layer 915 is electrically connected to the first metal layer 913, and an upper portion of the second metal layer 915 is electrically connected to the conductive layer 917, so that the first metal layer 913, the second metal layer 915, and the conductive layer 917 form a bonding pad 91. Not only is the bonding pad 91 used for bonding set in the output pin bonding area 9102 of the integrated circuit chip, and the bonding pad 91 is electrically connected with the output pin of the integrated circuit chip, but also other routing lines are arranged between the adjacent bonding pads 91 in order to save space, for example, the routing lines of other pads which are arranged in a vertically staggered manner or the routing lines used for display testing are collectively called as the interval routing lines 95. The spacer wires 95 are disposed on the same layer as the second metal layer 915, and the spacer wires 95 are disposed between the interlayer insulating layer 914 and the passivation layer 916.
As shown in fig. 6, fig. 6 is a schematic cross-sectional structure diagram illustrating the existence of alignment shift during the bonding process on the conventional array substrate. In the manufacturing process, there is a problem of misalignment in binding alignment. If the array substrate 90 has a problem of misalignment when the integrated circuit chip 92 or the flexible circuit board 93 is bonded, after the misalignment, the conductive adhesive 94 between the pad 921 of the integrated circuit chip 92 or the flexible circuit board 93 and the pad 91 of the array substrate is pressed during the bonding, and if the distance between the pad 91 of the array substrate and the spacing trace 95 is too short, the conductive particles 942 between the pad 921 of the integrated circuit chip 92 or the flexible circuit board 93 and the spacing trace 95 are also pressed to be connected with each other, and a short circuit occurs, resulting in abnormal display. In addition, the damaged passivation layer 916 on the spacer trace 95 is damaged by pressure, which exposes the spacer trace 95, and the spacer trace 95 loses insulation protection and is shorted with the bonding pad 91 of the array substrate 90 nearby by the conductive particles 942.
Disclosure of Invention
The invention provides an array substrate and a display panel, which can solve the technical problem of abnormal display caused by the fact that conductive adhesive conductive particles above spaced wires are pressed to be mutually connected to generate short circuit due to the fact that gaps between the spaced wires and a gasket are too small when binding alignment deviation occurs.
The invention provides an array substrate, which is provided with a binding region, wherein the binding region comprises a substrate layer, a first metal layer, an interlayer insulating layer, a second metal layer, a passivation layer and a conducting layer which are sequentially stacked from bottom to top; specifically, the first metal layer is arranged on the substrate layer and is provided with a plurality of pad bottoms arranged at intervals; the interlayer insulating layer is arranged on the first metal layer and is provided with a plurality of grooves and a plurality of through holes; the grooves are correspondingly arranged between the bottoms of the two adjacent bonding pads; the through hole is arranged corresponding to the bottom of the bonding pad; the second metal layer is arranged on the interlayer insulating layer and is provided with a plurality of spaced routing lines and line changing parts; the spaced routing lines are arranged in the grooves and are distributed along the extending direction of the grooves; the wire replacing part is arranged in the through hole and electrically connected with the bottom of the bonding pad; the passivation layer is arranged on the interlayer insulating layer and completely covers the second metal layer; the conducting layer is arranged on the passivation layer and provided with a plurality of bonding pad tops; the top of the bonding pad is in one-to-one correspondence with the wire replacing parts and is electrically connected with the wire replacing parts.
Further, one groove is arranged between the bottoms of two adjacent bonding pads.
Furthermore, a plurality of grooves are formed between the bottoms of two adjacent bonding pads, and one interval routing line is arranged in each groove.
Further, two spaced routing lines are arranged between the bottoms of two adjacent bonding pads.
Furthermore, a plurality of wire changing parts are correspondingly arranged on the bottom of one bonding pad; the plurality of wire replacing parts are arranged at intervals along the extending direction of the bottom of the bonding pad.
Further, the groove is arranged in parallel with the bottom of the bonding pad.
Further, the distance between the bottoms of two adjacent bonding pads is 20um-25um; the width of each interval routing line is 3-4 um; the distance between two adjacent spaced wires is 3.5-4.5 um; the recess with the minimum distance of pad bottom is 5.5um-6.5um.
Further, the substrate layer comprises a buffer layer and an insulating layer; the insulating layer is arranged on the buffer layer; the first metal layer is arranged on the insulating layer.
Further, the distance between the upper surface of the passivation layer above the spacing trace and the upper surface of the conductive layer is 6000 angstroms to 8500 angstroms.
Further, the material of the first metal layer comprises molybdenum; the interlayer insulating layer comprises a silicon oxide layer and a silicon nitride layer; the second metal layer is made of Ti/Al/Ti.
The invention further provides a display panel, which comprises the array substrate.
The array substrate and the display panel have the advantages that the grooves are formed in the interlayer insulating layers corresponding to the positions of the spaced wires, and the spaced wires are arranged in the grooves, so that the height difference between the spaced wires and the bonding pads for binding is increased, the phenomenon that conductive particles in the bound conductive adhesive are pressed on the spaced wires to be mutually connected to form a short circuit when the binding is staggered is avoided, and the product yield is improved.
Drawings
The technical solutions and other advantages of the present application will become apparent from the following detailed description of specific embodiments of the present application when taken in conjunction with the accompanying drawings.
Fig. 1 is a schematic structural diagram of a conventional array substrate after an integrated circuit chip and a flexible circuit board are bonded to the substrate;
FIG. 2 is a cross-sectional view of a conventional array substrate with bonding vias of the integrated circuit chip of FIG. 1;
fig. 3 is a schematic plan view illustrating a circuit trace in a bonding area of a conventional array substrate;
FIG. 4 is a schematic diagram of a planar structure of the output pin bonding area of the integrated circuit chip shown in FIG. 3 of the conventional array substrate;
FIG. 5 isbase:Sub>A schematic cross-sectional view taken along line A-A in FIG. 4 ofbase:Sub>A conventional array substrate;
fig. 6 is a schematic cross-sectional view illustrating a conventional array substrate with alignment deviation during bonding;
fig. 7 is a schematic plan view of an array substrate in embodiment 1 of the present invention;
FIG. 8 is a schematic cross-sectional view at B-B in FIG. 7 in example 1 of the present invention;
fig. 9 is a schematic plan view of an array substrate in embodiment 2 of the present invention;
fig. 10 is a schematic cross-sectional view at C-C in fig. 9 in embodiment 2 of the present invention.
The components in the figure are identified as follows:
1. a substrate layer, 2, a first metal layer, 3, an interlayer insulating layer, 4, a second metal layer,
5. passivation layer, 6, conductive layer, 10, pad structure, 11, buffer layer,
12. insulating layer, 21, bottom of pad, 31, grooves, 32, vias,
41. spacing routing, 42, line changing part, 61, bonding pad top, 100 and array substrate.
Detailed Description
The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. It should be apparent that the described embodiments are only a few embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Example 1
Referring to fig. 7 and 8, in embodiment 1 of the invention, an array substrate 100 is provided with a bonding region, where the bonding region includes a substrate layer 1, a first metal layer 2, an interlayer insulating layer 3, a second metal layer 4, a passivation layer 5, and a conductive layer 6, which are sequentially stacked from bottom to top.
Specifically, the first metal layer 2 is arranged on the substrate layer 1 and provided with a plurality of pad bottoms 21 arranged at intervals; the interlayer insulating layer 3 is arranged on the first metal layer 2 and is provided with a plurality of grooves 31 and a plurality of through holes 32; the groove 31 is correspondingly arranged between the bottoms 21 of two adjacent bonding pads; the via hole 32 is arranged corresponding to the pad bottom 21; the second metal layer 4 is arranged on the interlayer insulating layer 3 and is provided with a plurality of spaced routing lines 41 and a line changing part 42; the spacing wire 41 is arranged in the groove 31 and is arranged along the extending direction of the groove 31; the wire replacing part 42 is arranged in the through hole 32 and electrically connected with the pad bottom 21; the passivation layer 5 is arranged on the interlayer insulating layer 3 and completely covers the second metal layer 4; the conductive layer 6 is arranged on the passivation layer 5 and is provided with a plurality of pad tops 61; the pad tops 61 and the wire-changing portions 42 are arranged in a one-to-one correspondence and electrically connected. Wherein the pad bottom 21, the wire exchange portion 42 and the pad top 61 form the pad structure 10. An integrated circuit chip or a flexible circuit board is bonded on the pad structure 10.
In the present embodiment, one groove 31 is provided between two adjacent pad bottoms 21. Such a groove 31 can reduce the height of the plurality of spacing traces 41 disposed between two adjacent pad bottoms 21.
In this embodiment, a plurality of wire replacement parts 42 are correspondingly arranged on one pad bottom part 21; the plurality of wire replacement parts 42 are arranged at intervals along the extending direction of the pad bottom part 21.
In this embodiment, the groove 31 is disposed parallel to the pad bottom 21. So that the spacing traces 41 in the groove 31 are also arranged in parallel with the pad bottom 21.
In this embodiment, the distance between two adjacent pad bottoms 21 is 20um to 25um, preferably 23.5um; the width of each of the spaced traces 41 is 3um to 4um, preferably 3.75um; the distance between two adjacent spaced wires 41 is 3.5um to 4.5um, preferably 4um; the minimum distance between the groove 31 and the bottom 21 of the pad is 5.5um to 6.5um, preferably 6um.
In this embodiment, the substrate layer 1 includes a buffer layer 11 and an insulating layer 12; the insulating layer 12 is arranged on the buffer layer 11; the first metal layer 2 is disposed on the insulating layer 12. The buffer layer 11 is made of silicon oxide or silicon nitride. The buffer layer 11 includes a silicon oxide layer and a silicon nitride layer, and has a thickness of 3000 angstroms.
In this embodiment, the material of the first metal layer 2 includes molybdenum, and the thickness of the molybdenum is 2700 a to 3300 a. The interlayer insulating layer 3 is made of silicon oxide and has a thickness of 1200 angstroms. The material of the second metal layer 4 comprises Ti/Al/Ti, and the thickness of the second metal layer is 4400 angstroms. The passivation layer 5 is made of silicon nitride and has a thickness of 1000 angstroms. The material of the conductive layer 6 includes indium tin oxide, and the thickness of the indium tin oxide is 500 angstroms.
In this embodiment, a distance between the upper surface of the passivation layer 5 above the spacing trace 41 and the upper surface of the conductive layer 6 is 6000 angstroms to 8500 angstroms, preferably 8200 angstroms.
In the prior art, when the bonding alignment is shifted, all the partial pads that are shifted out can cause the conductive particles of the conductive adhesive above the spacer trace 41 to be pressed and connected with each other to generate a short circuit, because the gap between the spacer trace 41 and the pad is too small, the gap is 2200 angstroms, wherein the overall film thickness of the array substrate is about 17800 angstroms, and the overall film thickness at the spacer trace 41 is about 15600 angstroms.
On the basis of the prior art, the groove 31 is formed in the interlayer insulating layer 3 corresponding to the position of the space routing 41, and the space routing 41 is arranged in the groove 31, so that the height difference between the space routing 41 and the pad for binding is increased, as shown in fig. 7 and 8, the thickness of the film at the position of the space routing 41 after the hole is opened is about 11600 angstroms, the difference between the film and the pad is as high as 8200 angstroms, even if the position is shifted, because the gap is enough, the deviated pad cannot crush conductive particles between the pad and the pad, and the phenomenon that the conductive particles in the bound conductive adhesive are also pressed on the space routing 41 to be mutually connected to cause short circuit when the binding dislocation occurs can be avoided, and the product yield is improved.
Example 2
Referring to fig. 9 and 10, embodiment 2 includes most of the technical features of embodiment 1, and the difference is that in embodiment 2, a plurality of grooves 31 are disposed between two adjacent pad bottoms 21, and one spacing trace 41 is disposed in each groove 31. One of the grooves 31 is not provided between two adjacent pad bottoms 21 in embodiment 1.
In this embodiment, set up two between two adjacent pad bottoms 21 interval line 41, then correspond and set up two between two adjacent pad bottoms 21 recess 31, adjacent two the distance between recess 31 is 3.5um-4.5um, preferably 4um.
Example 3
In embodiment 3, a receiving groove (not shown) may be further disposed on the substrate layer 1 corresponding to the groove 31, so as to further increase a height difference between the spaced trace 41 and the bonding pad for binding, thereby avoiding that the conductive particles in the binding conductive adhesive are also pressed on the spaced trace 41 and are mutually connected to form a short circuit when the binding is dislocated, and improving the yield of products.
The present invention also provides a display panel including the array substrate 100 described above.
Compared with the prior art, the beneficial effects of the display panel provided by the embodiment of the invention are the same as the beneficial effects of the array substrate 100 provided by the above technical scheme, and are not repeated herein.
The display panel provided by the above embodiment may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, or a navigator.
The array substrate and the display panel have the advantages that the grooves are formed in the interlayer insulating layers corresponding to the positions of the spaced wires, and the spaced wires are arranged in the grooves, so that the height difference between the spaced wires and the bonding pads for binding is increased, the phenomenon that conductive particles in the bound conductive adhesive are pressed on the spaced wires to be mutually connected to form a short circuit when the binding is staggered is avoided, and the product yield is improved.
The array substrate and the display panel provided by the invention are described in detail above, and the principle and the implementation of the invention are explained in the present document by applying specific examples, and the description of the above examples is only used to help understanding the technical scheme and the core idea of the invention; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims (9)

1. An array substrate is provided with a binding region, and the array substrate is characterized in that the binding region comprises:
a substrate layer;
the first metal layer is arranged on the substrate layer and is provided with a plurality of bonding pad bottoms which are arranged at intervals;
the interlayer insulating layer is arranged on the first metal layer and is provided with a plurality of grooves and a plurality of through holes; the grooves are correspondingly arranged between the bottoms of the two adjacent bonding pads; the through hole is arranged corresponding to the bottom of the bonding pad; a plurality of grooves are formed between the bottoms of two adjacent bonding pads, and one interval routing is arranged in each groove;
the second metal layer is arranged on the interlayer insulating layer and is provided with a plurality of spaced routing lines and line changing parts; the spaced routing lines are arranged in the grooves and are distributed along the extending direction of the grooves; the wire replacing part is arranged in the through hole and electrically connected with the bottom of the bonding pad; the passivation layer is arranged on the interlayer insulating layer and completely covers the second metal layer, and a gap is reserved between the upper surface of the passivation layer and the upper surface of the interval routing; and
the conducting layer is arranged on the passivation layer and is provided with a plurality of bonding pad tops; the top of the bonding pad and the wire changing part are arranged in a one-to-one correspondence mode and are electrically connected.
2. The array substrate of claim 1, wherein one of the grooves is disposed between the bottoms of two adjacent pads.
3. The array substrate of claim 1, wherein two of the spaced traces are disposed between two adjacent pad bottoms.
4. The array substrate of claim 1, wherein a plurality of the wire-changing portions are correspondingly arranged on the bottom of one of the bonding pads; the plurality of wire replacing parts are arranged at intervals along the extending direction of the bottom of the bonding pad.
5. The array substrate of claim 1, wherein the groove is disposed parallel to the bottom of the pad.
6. The array substrate of claim 1, wherein the distance between the bottoms of two adjacent pads is 20um to 25um; the width of each interval routing line is 3-4 um; the distance between two adjacent spaced wires is 3.5-4.5 um; the recess with the minimum distance of pad bottom is 5.5um-6.5um.
7. The array substrate of claim 1, wherein the substrate layer comprises:
a buffer layer; and
the insulating layer is arranged on the buffer layer;
the first metal layer is arranged on the insulating layer.
8. The array substrate of claim 1, wherein a distance between an upper surface of the passivation layer above the spacer trace and an upper surface of the conductive layer is 6000 angstroms to 8500 angstroms.
9. A display panel comprising the array substrate of any one of claims 1-8.
CN202010969690.7A 2020-09-15 2020-09-15 Array substrate and display panel Active CN112002715B (en)

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Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112563290A (en) * 2020-12-02 2021-03-26 深圳市华星光电半导体显示技术有限公司 Pixel structure, preparation method thereof and display device
CN112599574B (en) * 2020-12-10 2022-07-12 武汉华星光电半导体显示技术有限公司 Display module and display device
CN113193017B (en) * 2021-04-21 2023-05-05 武汉华星光电技术有限公司 Display panel and display device
CN114185210A (en) * 2021-12-03 2022-03-15 武汉华星光电技术有限公司 Array substrate and display panel
CN114255658B (en) * 2021-12-16 2023-03-17 武汉华星光电技术有限公司 Display panel and display device
CN114898662B (en) * 2022-05-06 2023-09-26 武汉天马微电子有限公司 Module and substrate
CN118020021A (en) * 2022-09-01 2024-05-10 京东方科技集团股份有限公司 Connection structure, display panel, manufacturing method, detection circuit and display device

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110854175A (en) * 2019-11-26 2020-02-28 京东方科技集团股份有限公司 Array substrate, preparation method thereof and display panel
CN111458916A (en) * 2020-05-12 2020-07-28 京东方科技集团股份有限公司 Liquid crystal display module, manufacturing method and display panel

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102375894B1 (en) * 2015-03-27 2022-03-17 삼성디스플레이 주식회사 Display device and method for manufacturing the same
KR101951939B1 (en) * 2016-08-26 2019-02-25 엘지디스플레이 주식회사 Display Device
KR102582466B1 (en) * 2016-09-21 2023-09-25 삼성디스플레이 주식회사 Display device
US10707429B2 (en) * 2016-12-28 2020-07-07 Shanghai Tianma AM-OLED Co., Ltd. Flexible display panel and flexible display apparatus
US10591788B2 (en) * 2017-07-10 2020-03-17 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Array substrate and liquid crystal display panel

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110854175A (en) * 2019-11-26 2020-02-28 京东方科技集团股份有限公司 Array substrate, preparation method thereof and display panel
CN111458916A (en) * 2020-05-12 2020-07-28 京东方科技集团股份有限公司 Liquid crystal display module, manufacturing method and display panel

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